db21554.c revision 88b44bf4e73233af70877930178dbff7f1c2992b
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * CDDL HEADER START
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * The contents of this file are subject to the terms of the
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Common Development and Distribution License (the "License").
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * You may not use this file except in compliance with the License.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * or http://www.opensolaris.org/os/licensing.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * See the License for the specific language governing permissions
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * and limitations under the License.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * When distributing Covered Code, include this CDDL HEADER in each
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * If applicable, add the following below this CDDL HEADER, with the
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76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * CDDL HEADER END
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Use is subject to license terms.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Copyright 2012 Garrett D'Amore <garrett@damore.org>. All rights reserved.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Intel 21554 PCI to PCI bus bridge nexus driver for sun4u platforms.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Please note that 21554 is not a transparent bridge.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * This driver can be used when the 21554 bridge is used like a
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * transparent bridge. The host OBP or the OS PCI Resource Allocator
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * (during a hotplug/hotswap operation) must represent this device
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * as a nexus and do the device tree representation of the child
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * nodes underneath.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Interrupt routing of the children must be done as per the PCI
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * specifications recommendation similar to that of a transparent
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Address translations from secondary across primary can be 1:1
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * or non 1:1. Currently only 1:1 translations are supported.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Configuration cycles are indirect. Memory and IO cycles are direct.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi#include <sys/pci/db21554_config.h> /* 21554 configuration space registers */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi#include <sys/pci/db21554_csr.h> /* 21554 control status register layout */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi#include <sys/pci/db21554_ctrl.h> /* driver private control structure */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi#include <sys/pci/db21554_debug.h> /* driver debug declarations */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi#define DB_MODINFO_DESCRIPTION "Intel/21554 pci-pci nexus"
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi/* ioctl definitions */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi/* Default values for secondary cache line and latency timer */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi/* complete chip status information */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchitypedef struct db_pci_data {
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * The next set of variables are control parameters for debug purposes only.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Changing the default values as assigned below are not recommended.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * In some cases, the non-default values are mostly application specific and
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * hence may not have been tested yet.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * db_conf_map_mode : specifies the access method used for generating
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * configuration cycles. Default value indicates
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * the indirect configuration method.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * db_io_map_mode : specifies the access method used for generating
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * IO cycles. Default value indicates the direct
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * db_pci_own_wait : For indirect cycles, indicates the wait period
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * for acquiring the bus, when the bus is busy.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * db_pci_release_wait:For indirect cycles, indicates the wait period
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * for releasing the bus when the bus is busy.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * db_pci_max_wait : max. wait time when bus is busy for indirect cycles
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * db_set_latency_timer_register :
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * when 1, the driver overwrites the OBP assigned
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * latency timer register setting for every child
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * device during child initialization.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * db_set_cache_line_size_register :
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * when 1, the driver overwrites the OBP assigned
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * cache line register setting for every child
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * device during child initialization.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * db_use_config_own_bit:
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * when 1, the driver will use the "config own bit"
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * for accessing the configuration address and data
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic uint32_t db_pci_own_wait = DB_PCI_WAIT_MS;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic uint32_t db_pci_release_wait = DB_PCI_WAIT_MS;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic uint32_t db_pci_max_wait = DB_PCI_TIMEOUT;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic uint32_t db_conf_map_mode = DB_CONF_MAP_INDIRECT_CONF;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic uint32_t db_io_map_mode = DB_IO_MAP_DIRECT;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic uint32_t db_set_latency_timer_register = 1;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic uint32_t db_set_cache_line_size_register = 1;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Properties that can be set via .conf files.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * By default, we forward SERR# from secondary to primary. This behavior
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * can be controlled via a property "serr-fwd-enable", type integer.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Values are 0 or 1.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 0 means 'do not forward SERR#'.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 1 means forwards SERR# to the host. Should be the default.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * The next set of parameters are performance tuning parameters.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * These are in the form of properties settable through a .conf file.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * In case if the properties are absent the following defaults are assumed.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * These initial default values can be overwritten via /etc/system also.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * -1 means no setting is done ie. we either get OBP assigned value
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * or reset values (at hotplug time for example).
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi/* primary latency timer: property "p-latency-timer" : type integer */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int8_t p_latency_timer = DEF_INVALID_REG_VAL;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi/* secondary latency timer: property "s-latency-timer": type integer */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Currently on the secondary side the latency timer is not
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * set by the serial PROM which causes performance degradation.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Set the secondary latency timer register.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int8_t s_latency_timer = DB_SEC_LATENCY_TIMER_VAL;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi/* primary cache line size: property "p-cache-line-size" : type integer */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int8_t p_cache_line_size = DEF_INVALID_REG_VAL;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi/* secondary cache line size: property "s-cache-line-size" : type integer */
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Currently on the secondary side the cache line size is not
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * set by the serial PROM which causes performance degradation.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Set the secondary cache line size register.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int8_t s_cache_line_size = DB_SEC_CACHELN_SIZE_VAL;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * control primary posted write queue threshold limit:
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * property "p-pwrite-threshold" : type integer : values are 0 or 1.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 1 enables control. 0 does not, and is the default reset value.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int8_t p_pwrite_threshold = DEF_INVALID_REG_VAL;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * control secondary posted write queue threshold limit:
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * property "s-pwrite-threshold" : type integer : values are 0 or 1.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 1 enables control. 0 does not, and is the default reset value.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int8_t s_pwrite_threshold = DEF_INVALID_REG_VAL;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * control read queue threshold for initiating delayed read transaction
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * on primary bus.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * property "p-dread-threshold" : type integer: values are
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 0 : reset value, default behavior: at least 8DWords free for all MR
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 1 : reserved
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 2 : at least one cache line free for MRL and MRM, 8 DWords free for MR
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 3 : at least one cache line free for all MR
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int8_t p_dread_threshold = DEF_INVALID_REG_VAL;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * control read queue threshold for initiating delayed read transaction
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * on secondary bus.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * property "s-dread-threshold" : type integer: values are
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 0 : reset value, default behavior: at least 8DWords free for all MR
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 1 : reserved
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 2 : at least one cache line free for MRL and MRM, 8 DWords free for MR
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 3 : at least one cache line free for all MR
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int8_t s_dread_threshold = DEF_INVALID_REG_VAL;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * control how 21554 issues delayed transactions on the target bus.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * property "delayed-trans-order" : type integer: values are 0 or 1.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 1 means repeat transaction on same target on target retries.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * 0 is the reset/default value, and means enable round robin based
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * reads on other targets in read queue on any target retries.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int8_t delayed_trans_order = DEF_INVALID_REG_VAL;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * In case if the system DVMA information is not available, as it is
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * prior to s28q1, the system dvma range can be set via these parameters.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic uint32_t db_dvma_start = DB_DVMA_START;
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi * Default command register settings for all PCI nodes this nexus initializes.
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic void db_get_perf_parameters(db_ctrl_t *dbp);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic void db_set_perf_parameters(db_ctrl_t *dbp);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic void db_set_dvma_range(db_ctrl_t *dbp);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_pci_map(dev_info_t *, dev_info_t *, ddi_map_req_t *,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi void *, void *);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_intr_ops(dev_info_t *dip, dev_info_t *rdip,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic dev_info_t *db_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic void db_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic void db_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_open(dev_t *dev_p, int flag, int otyp, cred_t *cred_p);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_close(dev_t dev, int flag, int otyp, cred_t *cred_p);
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic int db_ioctl(dev_t dev, int cmd, intptr_t arg, int flag,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic dev_info_t *db_lookup_child_name(db_ctrl_t *dbp, char *name,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic void db_pci_get_header(ddi_acc_handle_t config_handle,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchistatic void db_pci_get_conf_regs(ddi_acc_handle_t config_handle,
76ca3cb000306bc4052fe820a7e4a6998dbcf932Robert Mustacchi#endif /* DB_DEBUG */
(void *)&modldrv,
static void *db_state;
const void *impl_data);
* register/unregister our callback.
_init(void)
int rc;
return (rc);
_fini(void)
int rc;
return (rc);
int rc;
return (rc);
infocmd);
switch (infocmd) {
case DDI_INFO_DEVT2DEVINFO:
case DDI_INFO_DEVT2INSTANCE:
return (rc);
int range_size;
switch (cmd) {
case DDI_ATTACH:
!= DDI_SUCCESS) {
!= DDI_SUCCESS) {
!= DDI_SUCCESS) {
case DDI_RESUME:
return (rc);
switch (cmd) {
case DDI_DETACH :
return (DDI_FAILURE);
case DDI_SUSPEND :
return (rc);
~P_PW_THRESHOLD) |
~S_PW_THRESHOLD) |
p_offset = 0;
s_offset = 0;
for (i = 0; i < rcount; i++) {
if (i != rcount) {
regval);
regval);
regval);
* Step 5: enable downstream/upstream I/O (through CSR space)
regval);
regval);
int dvma_prop_len;
== DDI_SUCCESS) {
dvma_size[0] = 0;
dvma_size[0] = 0;
#ifdef DEBUG
db_allocd = 0;
if (dvma_size[0]) {
dvma_bar[0] = 0;
#ifdef DB_SEC_SETUP_WRITE
#ifdef DB_SEC_SETUP_WRITE
return (ENXIO);
return (EBUSY);
return (EBUSY);
return (ENXIO);
int *rval_p)
#ifdef DB_DEBUG
#ifdef DB_DEBUG
return (rc);
return (rc);
== DB_INVAL_VEND) {
return (rc);
return (rc);
return (rc);
switch (cmd) {
case DEVCTL_DEVICE_GETSTATE:
case DEVCTL_DEVICE_ONLINE:
case DEVCTL_DEVICE_OFFLINE:
case DEVCTL_BUS_GETSTATE:
return (EFAULT);
switch (cmd) {
case DEVCTL_DEVICE_RESET:
case DEVCTL_BUS_QUIESCE:
case DEVCTL_BUS_UNQUIESCE:
case DEVCTL_BUS_RESET:
case DEVCTL_BUS_RESETALL:
return (rc);
#ifdef DB_DEBUG
static dev_info_t *
return (cdip);
return (cdip);
return (NULL);
case DDI_MT_RNUMBER :
!= DDI_SUCCESS)
return (DDI_FAILURE);
return (DDI_FAILURE);
case DDI_MT_REGSPEC :
return (DDI_FAILURE);
instance);
sizeof (db_acc_pvt_t));
return (DDI_SUCCESS);
return (DDI_FAILURE);
switch (addr_space_type) {
case PCI_ADDR_CONFIG :
if (db_conf_map_mode &
(uint32_t *)
(uint32_t *)
(uint8_t *)
(uint8_t *)
(uint32_t *)
(uint8_t *)
(uint8_t *)
if (db_conf_map_mode &
(uint32_t *)
(uint32_t *)
(uint8_t *)
(uint8_t *)
(uint32_t *)
(uint32_t *)
(uint8_t *)
(uint8_t *)
case PCI_ADDR_IO :
offset);
offset);
return (DDI_SUCCESS);
#ifdef DB_DEBUG
char *db_ctlop_name[] = {
switch (ctlop) {
case DDI_CTLOPS_REPORTDEV :
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_INITCHILD :
case DDI_CTLOPS_UNINITCHILD :
return (DDI_SUCCESS);
case DDI_CTLOPS_SIDDEV :
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE :
case DDI_CTLOPS_NREGS :
return (DDI_FAILURE);
static dev_info_t *
return (cdip);
goto done;
goto done;
return (DDI_FAILURE);
done:
char **unit_addr;
return (DDI_FAILURE);
return (DDI_FAILURE);
return (DDI_SUCCESS);
return (DDI_FAILURE);
if (func != 0)
return (DDI_SUCCESS);
uint_t n;
return (DDI_FAILURE);
extern int pci_allow_pseudo_children;
return (DDI_FAILURE);
if (pci_allow_pseudo_children) {
return (DDI_SUCCESS);
return (DDI_NOT_WELL_FORMED);
return (DDI_FAILURE);
return (DDI_SUCCESS);
int length;
int value;
return (value);
return (DDI_SUCCESS);
return (DDI_SUCCESS);
return (DDI_FAILURE);
statep++;
return (DDI_SUCCESS);
if (!dip) {
return (DDI_SUCCESS);
static uint8_t
static uint16_t
static uint32_t
static uint32_t
static uint8_t
static uint16_t
static uint32_t
if (db_use_config_own_bit) {
* check if (upstream/downstream)configuration address own
#ifdef DEBUG
wait_count = 0;
if (db_use_config_own_bit) {
#ifdef DEBUG
return (data);
static uint64_t
if (db_use_config_own_bit) {
* check if (upstream/downstream)configuration address own
#ifdef DEBUG
wait_count = 0;
if (db_use_config_own_bit) {
#ifdef DEBUG
data);
#ifdef DEBUG
char *s = NULL;
switch (func_id) {
if (s && !dip_no_disp) {
return (ENXIO);