db21554.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Intel 21554 PCI to PCI bus bridge nexus driver for sun4u platforms.
* Please note that 21554 is not a transparent bridge.
* This driver can be used when the 21554 bridge is used like a
* transparent bridge. The host OBP or the OS PCI Resource Allocator
* as a nexus and do the device tree representation of the child
* nodes underneath.
* Interrupt routing of the children must be done as per the PCI
* specifications recommendation similar to that of a transparent
* bridge.
* Address translations from secondary across primary can be 1:1
* or non 1:1. Currently only 1:1 translations are supported.
* Configuration cycles are indirect. Memory and IO cycles are direct.
*/
/*
* INCLUDES
*/
#include <sys/autoconf.h>
#include <sys/ddi_impldefs.h>
#include <sys/ddi_subrdefs.h>
/*
* DEFINES.
*/
#define DB_DEBUG
#define DB_MODINFO_DESCRIPTION "Intel/21554 pci-pci nexus:v%I%"
#define DB_DVMA_START 0xc0000000
#define DB_DVMA_LEN 0x20000000
#ifdef DB_DEBUG
/* ioctl definitions */
#define DB_PCI_READ_CONF_HEADER 1
#define DEF_INVALID_REG_VAL -1
/* Default values for secondary cache line and latency timer */
#define DB_SEC_LATENCY_TIMER_VAL 0x40
#define DB_SEC_CACHELN_SIZE_VAL 0x10
/* complete chip status information */
typedef struct db_pci_data {
char name[256];
#endif
/*
* LOCALS
*/
/*
* The next set of variables are control parameters for debug purposes only.
* Changing the default values as assigned below are not recommended.
* In some cases, the non-default values are mostly application specific and
* hence may not have been tested yet.
*
* db_conf_map_mode : specifies the access method used for generating
* configuration cycles. Default value indicates
* the indirect configuration method.
* db_io_map_mode : specifies the access method used for generating
* IO cycles. Default value indicates the direct
* method.
* db_pci_own_wait : For indirect cycles, indicates the wait period
* for acquiring the bus, when the bus is busy.
* db_pci_release_wait:For indirect cycles, indicates the wait period
* for releasing the bus when the bus is busy.
* db_pci_max_wait : max. wait time when bus is busy for indirect cycles
* db_set_latency_timer_register :
* when 1, the driver overwrites the OBP assigned
* latency timer register setting for every child
* device during child initialization.
* db_set_cache_line_size_register :
* when 1, the driver overwrites the OBP assigned
* cache line register setting for every child
* device during child initialization.
* db_use_config_own_bit:
* when 1, the driver will use the "config own bit"
* for accessing the configuration address and data
* registers.
*/
static uint32_t db_use_config_own_bit = 0;
/*
* Properties that can be set via .conf files.
*/
/*
* By default, we forward SERR# from secondary to primary. This behavior
* can be controlled via a property "serr-fwd-enable", type integer.
* Values are 0 or 1.
* 0 means 'do not forward SERR#'.
* 1 means forwards SERR# to the host. Should be the default.
*/
/*
* The next set of parameters are performance tuning parameters.
* These are in the form of properties settable through a .conf file.
* In case if the properties are absent the following defaults are assumed.
*
* -1 means no setting is done ie. we either get OBP assigned value
* or reset values (at hotplug time for example).
*/
/* primary latency timer: property "p-latency-timer" : type integer */
/* secondary latency timer: property "s-latency-timer": type integer */
/*
* Currently on the secondary side the latency timer is not
* set by the serial PROM which causes performance degradation.
* Set the secondary latency timer register.
*/
/* primary cache line size: property "p-cache-line-size" : type integer */
/* secondary cache line size: property "s-cache-line-size" : type integer */
/*
* Currently on the secondary side the cache line size is not
* set by the serial PROM which causes performance degradation.
* Set the secondary cache line size register.
*/
/*
* control primary posted write queue threshold limit:
* property "p-pwrite-threshold" : type integer : values are 0 or 1.
* 1 enables control. 0 does not, and is the default reset value.
*/
/*
* control secondary posted write queue threshold limit:
* property "s-pwrite-threshold" : type integer : values are 0 or 1.
* 1 enables control. 0 does not, and is the default reset value.
*/
/*
* control read queue threshold for initiating delayed read transaction
* on primary bus.
* property "p-dread-threshold" : type integer: values are
*
* 0 : reset value, default behavior: at least 8DWords free for all MR
* 1 : reserved
* 2 : at least one cache line free for MRL and MRM, 8 DWords free for MR
* 3 : at least one cache line free for all MR
*/
/*
* control read queue threshold for initiating delayed read transaction
* on secondary bus.
* property "s-dread-threshold" : type integer: values are
*
* 0 : reset value, default behavior: at least 8DWords free for all MR
* 1 : reserved
* 2 : at least one cache line free for MRL and MRM, 8 DWords free for MR
* 3 : at least one cache line free for all MR
*/
/*
* control how 21554 issues delayed transactions on the target bus.
* property "delayed-trans-order" : type integer: values are 0 or 1.
* 1 means repeat transaction on same target on target retries.
* reads on other targets in read queue on any target retries.
*/
/*
* In case if the system DVMA information is not available, as it is
* prior to s28q1, the system dvma range can be set via these parameters.
*/
/*
* Default command register settings for all PCI nodes this nexus initializes.
*/
static uint16_t db_command_default =
void **result);
void *, void *);
void *result);
struct bus_ops db_bus_ops = {
0,
0,
0,
0,
0,
0,
NULL,
0,
};
#ifdef DB_DEBUG
int instance);
db_conf_regs_t *cr);
#endif /* DB_DEBUG */
#ifdef DEBUG
static void
#endif
db_open, /* open */
db_close, /* close */
nulldev, /* strategy */
nulldev, /* print */
nulldev, /* dump */
nulldev, /* read */
nulldev, /* write */
db_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
db_prop_op, /* cb_prop_op */
NULL, /* streamtab */
CB_REV, /* rev */
nodev, /* int (*cb_aread)() */
nodev /* int (*cb_awrite)() */
};
static struct dev_ops db_dev_ops = {
DEVO_REV, /* devo_rev */
0, /* refcnt */
db_getinfo, /* info */
nulldev, /* identify */
nulldev, /* probe */
db_attach, /* attach */
db_detach, /* detach */
nulldev, /* reset */
&db_cb_ops, /* driver operations */
&db_bus_ops, /* bus operations */
};
/*
* Module linkage information for the kernel.
*/
&mod_driverops, /* Type of module */
&db_dev_ops /* driver ops */
};
static struct modlinkage modlinkage = {
(void *)&modldrv,
};
/* soft state pointer and structure template. */
static void *db_state;
/*
* forward function declarations:
*/
static void db_uninitchild(dev_info_t *);
/*
* FMA error callback
* Register error handling callback with our parent. We will just call
* our children's error callbacks and return their status.
*/
const void *impl_data);
/*
* register/unregister our callback.
*/
int
_init(void)
{
int rc;
sizeof (db_ctrl_t), 1)) == 0) &&
return (rc);
}
int
_fini(void)
{
int rc;
return (rc);
}
int
{
int rc;
return (rc);
}
/*ARGSUSED*/
static int
{
int rc = DDI_FAILURE;
infocmd);
switch (infocmd) {
case DDI_INFO_DEVT2DEVINFO:
rc = DDI_SUCCESS;
} else
break;
case DDI_INFO_DEVT2INSTANCE:
rc = DDI_SUCCESS;
break;
default:
break;
}
return (rc);
}
static int
{
int rc = DDI_SUCCESS;
};
int range_size;
char name[32];
switch (cmd) {
case DDI_ATTACH:
rc = DDI_FAILURE;
break;
}
/*
* Cannot use pci_config_setup here as we'd need
* to get a pointer to the address map to be able
* to set the bus private handle during child map
* operation.
*/
!= DDI_SUCCESS) {
"%s#%d: cannot map configuration space",
rc = DDI_FAILURE;
break;
}
!= DDI_SUCCESS) {
rc = DDI_FAILURE;
break;
}
/* map memory CSR space */
rc = DDI_FAILURE;
break;
}
!= DDI_SUCCESS) {
rc = DDI_FAILURE;
break;
}
/*
* map IO CSR space. We need this map to initiate
* indirect configuration transactions as this is a better
* option than doing through configuration space map.
*/
rc = DDI_FAILURE;
break;
}
"%s#%d: could not register with hotplug",
} else {
/*
* create minor node for devctl interfaces
*/
DDI_NT_NEXUS, 0) != DDI_SUCCESS) {
rc = DDI_FAILURE;
break;
}
}
&range_size) != DDI_SUCCESS) {
"%s#%d: cannot get bus-range property",
(void) pcihp_uninit(dip);
else
rc = DDI_FAILURE;
break;
}
}
break;
case DDI_RESUME:
/*
* Get the soft state structure for the bridge.
*/
(void) db_restore_config_regs(dbp);
break;
default:
break;
}
return (rc);
}
static int
{
int rc = DDI_SUCCESS;
char name[32];
switch (cmd) {
case DDI_DETACH :
return (DDI_FAILURE);
else
break;
case DDI_SUSPEND :
"%s#%d: Ignoring Child state Suspend Error",
}
break;
default :
rc = DDI_FAILURE;
break;
}
return (rc);
}
static void
{
}
static void
{
else
~P_PW_THRESHOLD) |
~S_PW_THRESHOLD) |
/* primary delayed read threshold. 0x01 is reserved ?. */
((dbp->p_dread_threshold &
DREAD_THRESHOLD_VALBITS)<<2)));
/* secondary delayed read threshold. 0x01 is reserved ?. */
((dbp->s_dread_threshold &
DREAD_THRESHOLD_VALBITS)<<4)));
}
static void
{
/*
* determine orientation of drawbridge and enable
* Upstream or Downstream path.
*/
/*
* if PIF is set correctly, use it to determine orientation
*/
if (pif & 0xff) {
if (pif & DB_PIF_SECONDARY_TO_HOST) {
"db_orientation: pif secondary\n");
return;
}
if (pif & DB_PIF_PRIMARY_TO_HOST) {
"db_orientation: pif primary\n");
return;
}
/* otherwise, fall through */
}
/*
* otherwise, test the chip directly by trying to write
* downstream mem1 setup register, only writeable from
* secondary.
*/
DB_CONF_DS_IO_MEM1_SETUP)), ~mem1);
/* we couldn't write it, orientation is primary */
else {
/*
* we could write it, therefore orientation secondary.
* restore mem1 value.
*/
}
} else {
}
}
static void
{
/*
* Step 0:
* setup the primary and secondary offset and enable
* values based on the orientation of 21554.
*/
p_offset = 0;
} else {
s_offset = 0;
}
/*
* Step 1:
* setup latency timer and cache line size parameters
* which are used for child initialization.
*/
"db_enable_io: latency %d, cache line size %d\n",
/*
* Step 2: program command reg on both primary and secondary
* interfaces.
*/
/*
* Step 3:
* set up translated base registers, using the primary/
* secondary interface pci configuration Base Address
* Registers (BAR's).
*/
/* mem0 translated base is setup for primary orientation only. */
/*
* And only if the 21554 device node property indicates
* the size of base0 register to be larger than csr map
* space, DB_CSR_SIZE=4K.
*
* Note : Setting up 1:1 translations only (for now:), i.e.
* no look up table.
*/
&length) != DDI_PROP_SUCCESS) {
"Failed to read reg property\n");
return;
}
/* Find device node's base0 reg property and check its size */
for (i = 0; i < rcount; i++) {
if ((offset == PCI_CONF_BASE0) &&
break;
}
/*
* set up mem0 translated base, if base0 register was
* found and its size was larger than csr map space.
*/
if (i != rcount) {
"db_enable_io: setting up MEM0_TR_BASE\n");
"db_enable_io: MEM0_TR_BASE set value = %x\n",
}
}
/*
* Step 4: enable downstream (for primary orientation) or upstream
* (for secondary orientation) bits in Configuration Control
* and Status register, if not already enabled.
*/
regval);
regval);
}
regval);
/*
* Step 5: enable downstream/upstream I/O (through CSR space)
*/
regval);
DB_CSR_IO_CSR), regval);
}
regval);
/*
* Step 6: if 21554 orientation is primary to host,
* forward SERR# to host.
*/
"db_enable_io: CHIP_CTRL0 value before: %x\n", regval);
"db_enable_io: CHIP_CTRL0 value after: %x\n", regval);
}
/*
* Step 7: if orientation is secondary, make sure primary lockout
* disable is reset.
*/
"db_enable_io: chip ctrl (0x%x) before\n", regval);
"db_enable_io: chip ctrl (0x%x) after\n", regval);
}
}
/*
* Set DVMA Address Range.
* This code is common to both orientations of the nexus driver.
*/
static void
{
uint32_t dvma_start = 0;
int dvma_prop_len;
/*
* Need to traverse up the tree looking for a
* "virtual-dma" property that specifies the
* HPB DVMA range.
*/
== DDI_SUCCESS) {
dvma_start = dvma_prop[0];
} else {
/*
* For initial implementation, lets avoid a warning since this
* change has not been implemented in the host-pci nexus
* driver.
*/
"%s#%d: Could not get \"virtual-dma\" property",
}
/* Validate DVMA size programming and system requirements. */
else
dvma_size[0] = 0;
} else {
else
dvma_size[0] = 0;
}
#ifdef DEBUG
" with system requirements",
#endif
db_allocd = 0;
/* now, program the correct DVMA range over the 2 BARs. Max 4GB */
if (dvma_size[0]) {
}
/*
* It does not serve any purpose to set the other DVMA register
* when we have already met the memory requirements so leave it
* disabled.
*/
}
/* In case of secondary orientation, DVMA BAR0 is 0. */
dvma_bar[0] = 0;
}
/* configure the setup register and DVMA BARs. */
if (dvma_bar[0] != 0xFFFFFFFF) {
#ifdef DB_SEC_SETUP_WRITE
/*
* No need to program the setup register
* as the PROM would have done it.
*/
#endif
/*
* when translations are to be provided, this will
* change.
*/
DB_SCONF_DS_IO_MEM1, dvma_bar[0]);
}
#ifdef DB_SEC_SETUP_WRITE
/*
* No need to program the setup register
* as the PROM would have done it.
*/
#endif
/*
* when translations are to be provided, this will
* change.
*/
}
} else {
if (dvma_bar[0] != 0xFFFFFFFF) {
#ifdef DB_CONF_P2S_WRITE_ENABLED /* primary to secondary write enabled */
/*
* We have a problem with this setup, because the
* US_MEM1 setup register cannot be written from the
* primary interface...!!! Hence in this configuration,
* we cannot dynamically program the DVMA range!
*/
DB_CONF_US_IO_MEM0_SETUP) & 0xF)) |
0x80000000));
#endif
/*
* when translations are to be provided, this will
* change.
*/
DB_PCONF_US_IO_MEM0, dvma_bar[0]);
}
#ifdef DB_CONF_P2S_WRITE_ENABLED /* primary to secondary write enabled */
/*
* We have a problem with this setup, because the
* US_MEM1 setup register cannot be written from the
* primary interface...!!! Hence in this configuration,
* we cannot dynamically program the DVMA range!
*/
#endif
/*
* when translations are to be provided, this will
* change.
*/
}
}
}
/*ARGSUSED*/
static int
{
return (ENXIO);
/*
* check for debug node
*/
return (0);
/*
* Handle the open by tracking the device state.
*/
return (EBUSY);
}
} else {
return (EBUSY);
}
}
return (0);
}
/*ARGSUSED*/
static int
{
return (ENXIO);
/*
* check for debug node
*/
return (0);
return (0);
}
/*ARGSUSED*/
static int
int *rval_p)
{
int rc = DDI_SUCCESS;
#ifdef DB_DEBUG
#endif
struct devctl_iocdata *dcp;
#ifdef DB_DEBUG
/*
* try this first whether were SECONDARY_NEXUS or not
*/
if (cmd == DB_PCI_READ_CONF_HEADER) {
sizeof (db_pci_data_t), mode)) {
return (rc);
}
} else {
== (dev_info_t *)NULL) {
return (rc);
} else {
if (ddi_getprop(DDI_DEV_T_ANY,
"vendor-id", DB_INVAL_VEND)
== DB_INVAL_VEND) {
/* non PCI device */
return (rc);
}
}
}
/* if it is the drawbridge itself, read sec header */
}
sizeof (db_pci_data_t), mode)) {
return (rc);
}
return (rc);
}
#endif /* DB_DEBUG */
/*
* if secondary nexus (hotplug), then use pcihp_ioctl to do everything
*/
/*
* if not secondary nexus, we do DEVCTL_DEVICE and DEVCTL_BUS ourselves
*/
/*
* We can use the generic implementation for these ioctls
*/
switch (cmd) {
case DEVCTL_DEVICE_GETSTATE:
case DEVCTL_DEVICE_ONLINE:
case DEVCTL_DEVICE_OFFLINE:
case DEVCTL_BUS_GETSTATE:
}
/*
* read devctl ioctl data
*/
return (EFAULT);
switch (cmd) {
case DEVCTL_DEVICE_RESET:
break;
case DEVCTL_BUS_QUIESCE:
if (bus_state == BUS_QUIESCED)
break;
break;
case DEVCTL_BUS_UNQUIESCE:
if (bus_state == BUS_ACTIVE)
break;
break;
case DEVCTL_BUS_RESET:
break;
case DEVCTL_BUS_RESETALL:
break;
default:
}
return (rc);
}
#ifdef DB_DEBUG
static dev_info_t *
{
do {
if (instance != -1) {
return (cdip);
} else
return (cdip);
}
break;
}
}
return (NULL);
}
static void
{
hdr_off + PCI_CONF_CIS);
hdr_off + PCI_CONF_ROM);
}
static void
{
}
#endif /* DB_DEBUG */
/*
* Function: db_pci_map
*
* Note: Only memory accesses are direct. IO could be direct
* or indirect. Config accesses are always indirect.
* The question here is, does the "assigned-addresses"
* property entry represents the addresses in the
* local domain or the host domain itself.
* Strictly speaking, the assumption should be that
* it is in the local domain, as the transactions
* upstream or downstream are automatically
* translated by the bridge chip anyway.
*
* Return values:
* DDI_SUCCESS: map call by child device success
* DDI_FAILURE: map operation failed.
*/
static int
{
register dev_info_t *pdip;
/* get map type. check for config space */
case DDI_MT_RNUMBER :
/* get the reg number */
DDI_PROP_DONTPASS, "reg",
!= DDI_SUCCESS)
return (DDI_FAILURE);
/* this is a DDI_ME_RNUMBER_RANGE error */
return (DDI_FAILURE);
}
/* FALLTHROUGH */
case DDI_MT_REGSPEC :
/*
* Intercept config space accesses only. All other
* requests go to the parent.
*/
/* if we do direct map IO, then lets break here */
if ((db_io_map_mode & DB_IO_MAP_DIRECT) &&
(addr_space_type == PCI_ADDR_IO))
break;
if ((addr_space_type != PCI_ADDR_CONFIG) &&
(addr_space_type != PCI_ADDR_IO))
break;
/*
* User mapping requests not legal for indirect
*/
return (DDI_FAILURE);
instance);
/* get our common access handle */
/* Check for unmap operation */
/*
* free up memory allocated for our
* private access handle.
*/
db_pvt = (db_acc_pvt_t *)
"unmap rdip=%lx\n", rdip);
sizeof (db_acc_pvt_t));
/*
* space.
*/
return (DDI_SUCCESS);
}
if (addr_space_type == PCI_ADDR_CONFIG) {
/* Config space access range check */
if ((offset >= PCI_CONF_HDR_SIZE) ||
(len > PCI_CONF_HDR_SIZE) ||
return (DDI_FAILURE);
}
}
/* define the complete access handle */
/* allocate memory for our private handle */
/* record the device address for future use */
/*
* We should keep the upstream or
* downstream info in our own ah_bus_private
* structure, so that we do not waste our
* time in the actual IO routines, figuring out
* if we should use upstream or downstream
* So, check orientation and setup registers
* right now.
*/
switch (addr_space_type) {
case PCI_ADDR_CONFIG :
if (db_conf_map_mode &
"INDIRECT_CONF\n");
(uint32_t *)
(uint32_t *)
(uint8_t *)
(uint8_t *)
} else {
"DIRECT_CONF\n");
(uint32_t *)
(uint8_t *)
(uint8_t *)
}
} else {
"secondary\n");
if (db_conf_map_mode &
"INDIRECT_CONF\n");
(uint32_t *)
(uint32_t *)
(uint8_t *)
(uint8_t *)
} else {
"DIRECT_CONF\n");
(uint32_t *)
(uint32_t *)
(uint8_t *)
(uint8_t *)
}
}
break;
case PCI_ADDR_IO :
/* ap->ahi_acc_attr |= DDI_ACCATTR_IO_SPACE; */
} else {
"secondary\n");
}
break;
default :
"PCI_ADDR unknown\n");
break;
}
/* make and store a type 0/1 address in the *addrp */
offset);
"access mode type 0\n");
} else {
offset);
"access mode type 1\n");
}
return (DDI_SUCCESS);
default :
break;
}
}
#ifdef DB_DEBUG
char *db_ctlop_name[] = {
"DDI_CTLOPS_DMAPMAPC",
"DDI_CTLOPS_INITCHILD",
"DDI_CTLOPS_UNINITCHILD",
"DDI_CTLOPS_REPORTDEV",
"DDI_CTLOPS_REPORTINT",
"DDI_CTLOPS_REGSIZE",
"DDI_CTLOPS_NREGS",
"DDI_CTLOPS_NINTRS",
"DDI_CTLOPS_SIDDEV",
"DDI_CTLOPS_SLAVEONLY",
"DDI_CTLOPS_AFFINITY",
"DDI_CTLOPS_IOMIN",
"DDI_CTLOPS_PTOB",
"DDI_CTLOPS_BTOP",
"DDI_CTLOPS_BTOPR",
"DDI_CTLOPS_RESERVED1",
"DDI_CTLOPS_RESERVED2",
"DDI_CTLOPS_RESERVED3",
"DDI_CTLOPS_INTR_HILEVEL",
"DDI_CTLOPS_XLATE_INTRS",
"DDI_CTLOPS_DVMAPAGESIZE",
"DDI_CTLOPS_POWER",
"DDI_CTLOPS_ATTACH",
"DDI_CTLOPS_DETACH",
"DDI_CTLOPS_POKE",
"DDI_CTLOPS_PEEK"
};
#endif
static int
{
if ((ctlop >= DDI_CTLOPS_DMAPMAPC) &&
(ctlop <= DDI_CTLOPS_DETACH)) {
} else {
}
switch (ctlop) {
case DDI_CTLOPS_REPORTDEV :
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_INITCHILD :
case DDI_CTLOPS_UNINITCHILD :
return (DDI_SUCCESS);
case DDI_CTLOPS_SIDDEV :
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE :
case DDI_CTLOPS_NREGS :
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
/* fall through */
default :
}
}
static dev_info_t *
{
;
return (cdip);
}
static int
{
goto done;
/*
* If the interrupt-map property is defined at this
* node, it will have performed the interrupt
* translation as part of the property, so no
* rotation needs to be done.
*/
goto done;
/*
* Use the devices reg property to determine it's
* PCI bus number and device number.
*/
return (DDI_FAILURE);
/* Spin the interrupt */
else
done:
/* Pass up the request to our parent. */
}
static int
{
if (ndi_dev_is_persistent_node(child) == 0) {
char **unit_addr;
/* name .conf nodes by "unit-address" property" */
return (DDI_FAILURE);
}
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/* name hardware nodes by "reg" property */
(int **)&pci_rp, &n) != DDI_SUCCESS)
return (DDI_FAILURE);
/* get the device identifications */
if (func != 0)
else
return (DDI_SUCCESS);
}
static int
{
char name[MAXNAMELEN];
uint_t n;
return (DDI_FAILURE);
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
extern int pci_allow_pseudo_children;
/*
* Try to merge the properties from this prototype
* node into real h/w nodes.
*/
/*
* Merged ok - return failure to remove the node.
*/
return (DDI_FAILURE);
}
/* workaround for ddivs to run under PCI */
if (pci_allow_pseudo_children) {
return (DDI_SUCCESS);
}
/*
* The child was not merged into a h/w node,
* but there's not much we can do with it other
* than return failure to cause the node to be removed.
*/
return (DDI_NOT_WELL_FORMED);
}
return (DDI_FAILURE);
}
/*
* Determine the configuration header type.
*/
/*
* Support for the "command-preserve" property.
*/
DDI_PROP_DONTPASS, "command-preserve", 0);
"initializing device vend=%x, devid=%x\n",
/*
* If the device has a bus control register then program it
* based on the settings in the command register.
*/
}
/*
* Initialize cache-line-size configuration register if needed.
*/
"cache-line-size", 0) == 0) {
if (n != 0) {
"cache-line-size", n);
}
}
/*
* Initialize latency timer configuration registers if needed.
*/
"latency-timer", 0) == 0) {
dbp->latency_timer);
} else {
}
if (n != 0) {
"latency-timer", n);
}
"\nChild Device latency %x\n", latency_timer);
}
return (DDI_SUCCESS);
}
static void
{
/*
* Strip the node to properly convert it back to prototype form
*/
}
static int
{
int length;
int value;
/* get child "reg" property */
if (value != DDI_SUCCESS)
return (value);
/*
* free the memory allocated by ddi_getlongprop ().
*/
/*
* No need to create any 1275 properties here, because either
* the OBP creates them or the hotplug framework creates it
* during a hotplug operation. So lets return here.
*/
return (DDI_SUCCESS);
}
/*
* db_save_config_regs
*
* This routine saves the state of the configuration registers of all
* immediate child nodes.
*
* used by: db_detach() on suspends
*
* return value: DDI_SUCCESS: ALl children state saved.
* DDI_FAILURE: Child device state could not be saved.
*/
static int
{
int i;
i++;
}
dbp->config_state_index = i;
if (!i) {
/* no children */
return (DDI_SUCCESS);
}
/* i now equals the total number of child devices */
if (!dbp->db_config_state_p) {
"%s#%d: No memory to save state for child %s#%d\n",
return (DDI_FAILURE);
}
continue;
"%s#%d: can't config space for %s#%d",
continue;
}
statep++;
}
return (DDI_SUCCESS);
}
/*
* db_restore_config_regs
*
* This routine restores the state of the configuration registers of
* all immediate child nodes.
*
* used by: db_attach() on resume
*
* return value: none
*/
static int
{
int i;
if (!dip) {
"%s#%d: skipping bad dev info (index %d)",
continue;
}
"%s#%d: can't config space for %s#%d",
continue;
}
}
dbp->config_state_index = 0;
return (DDI_SUCCESS);
}
/* put a type 0/1 address on the bus */
static void
{
else /* type 1 cycle */\
}
/* Get 8bits data off the 32bit data */
static uint8_t
{
}
/* Get 16bits data off the 32bit data */
static uint16_t
{
}
/* merge 8bit data into the 32bit data */
static uint32_t
{
}
/* merge 16bit data into the 32bit data */
static uint32_t
{
}
/*
* For the next set of PCI configuration IO calls, we need
* to make sure we own the bus before generating the config cycles,
* using the drawbridge's semaphore method.
*/
/*
* Function to read 8 bit data off the PCI configuration space behind
* the 21554's host interface.
*/
static uint8_t
{
}
/*
* Function to read 16 bit data off the PCI configuration space behind
* the 21554's host interface.
*/
static uint16_t
{
}
/*
* Function to read 32 bit data off the PCI configuration space behind
* the 21554's host interface.
*/
static uint32_t
{
uint32_t wait_count = 0;
if (db_use_config_own_bit) {
/*
* check if (upstream/downstream)configuration address own
* bit set. With this set, we cannot proceed.
*/
#ifdef DEBUG
#endif
if (++wait_count == db_pci_max_wait) {
/*
* the man page for pci_config_* routines do
* Not specify any error condition values.
*/
"%s#%d: pci config bus own error",
dbp->db_pci_err_count++;
return ((uint32_t)DB_CONF_FAILURE);
}
}
wait_count = 0;
}
if (db_use_config_own_bit) {
#ifdef DEBUG
#endif
if (++wait_count == db_pci_max_wait) {
/*
* the man page for pci_config_* routines do
* not specify any error condition values.
*/
"%s#%d: pci config bus release error",
dbp->db_pci_err_count++;
return ((uint32_t)DB_CONF_FAILURE);
}
}
}
return (data);
}
/*
* Function to read 64 bit data off the PCI configuration space behind
* the 21554's host interface.
*/
static uint64_t
{
}
/*
* Function to write 8 bit data into the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
}
/*
* Function to write 16 bit data into the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
}
/*
* Function to write 32 bit data into the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
uint32_t wait_count = 0;
if (db_use_config_own_bit) {
/*
* check if (upstream/downstream)configuration address own
* bit set. with this set, we cannot proceed.
*/
#ifdef DEBUG
#endif
if (++wait_count == db_pci_max_wait) {
/*
* Since the return value is void here,
* we may need to print a message, as this
* could be a serious situation.
*/
"%s#%d: pci config bus own error",
dbp->db_pci_err_count++;
return;
}
}
wait_count = 0;
}
if (db_use_config_own_bit) {
#ifdef DEBUG
#endif
if (++wait_count == db_pci_max_wait) {
/*
* the man page for pci_config_* routines do
* Not specify any error condition values.
*/
"%s#%d: pci config bus release error",
dbp->db_pci_err_count++;
return;
}
data);
}
}
}
/*
* Function to write 64 bit data into the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
}
/*
* Function to rep read 8 bit data off the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
if (flags == DDI_DEV_AUTOINCR)
else
}
/*
* Function to rep read 16 bit data off the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
if (flags == DDI_DEV_AUTOINCR)
else
}
/*
* Function to rep read 32 bit data off the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
if (flags == DDI_DEV_AUTOINCR)
else
}
/*
* Function to rep read 64 bit data off the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
if (flags == DDI_DEV_AUTOINCR)
else
}
/*
* Function to rep write 8 bit data into the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
if (flags == DDI_DEV_AUTOINCR)
else
}
/*
* Function to rep write 16 bit data into the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
if (flags == DDI_DEV_AUTOINCR)
else
}
/*
* Function to rep write 32 bit data into the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
if (flags == DDI_DEV_AUTOINCR)
else
}
/*
* Function to rep write 64 bit data into the PCI configuration space behind
* the 21554's host interface.
*/
static void
{
if (flags == DDI_DEV_AUTOINCR)
else
}
#ifdef DEBUG
static void
{
char *s = NULL;
uint_t dip_no_disp = 0;
if (func_id & DB_DONT_DISPLAY_DIP) {
dip_no_disp = 1;
}
if (db_debug_funcs & func_id) {
switch (func_id) {
case DB_INIT: s = "_init"; break;
case DB_FINI: s = "_fini"; break;
case DB_INFO: s = "_info"; break;
case DB_GETINFO: s = "getinfo"; break;
case DB_ATTACH: s = "attach"; break;
case DB_DETACH: s = "detach"; break;
case DB_CTLOPS: s = "ctlops"; break;
case DB_INITCHILD: s = "initchild"; break;
case DB_REMOVECHILD: s = "removechild"; break;
case DB_INTR_OPS: s = "intr_ops"; break;
case DB_PCI_MAP: s = "map"; break;
case DB_SAVE_CONF_REGS: s = "save_conf_regs"; break;
case DB_REST_CONF_REGS: s = "restore_conf_regs"; break;
case DB_INTR: s = "intr"; break;
case DB_OPEN: s = "open"; break;
case DB_CLOSE: s = "close"; break;
case DB_IOCTL: s = "ioctl"; break;
case DB_DVMA: s = "set_dvma_range"; break;
default: s = "PCI debug unknown"; break;
}
if (s && !dip_no_disp) {
ddi_get_instance(dip), s);
}
}
}
#endif
{
return (ENXIO);
}
/*
* Initialize our FMA resources
*/
static void
{
/*
* Request our capability level and get our parents capability
* and ibc.
*/
/*
* clear any outstanding error bits
*/
/*
* Register error callback with our parent.
*/
}
/*
* Breakdown our FMA resources
*/
static void
{
/*
* Clean up allocated fm structures
*/
}
/*
* Initialize FMA resources for children devices. Called when
* child calls ddi_fm_init().
*/
/*ARGSUSED*/
static int
{
}
/*
* FMA registered error callback
*/
static int
{
}
static void
{
}
/* ARGSUSED */
static void
{
}