142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * CDDL HEADER START
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * The contents of this file are subject to the terms of the
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Common Development and Distribution License (the "License").
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * You may not use this file except in compliance with the License.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * See the License for the specific language governing permissions
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * and limitations under the License.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * When distributing Covered Code, include this CDDL HEADER in each
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * If applicable, add the following below this CDDL HEADER, with the
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * fields enclosed by brackets "[]" replaced with your own identifying
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * information: Portions Copyright [yyyy] [name of copyright owner]
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * CDDL HEADER END
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Use is subject to license terms.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Assembly code support for the Cheetah+ module
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#pragma ident "%Z%%M% %I% %E% SMI"
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if !defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* TRAPTRACE */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if !defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Panther version to reflush a line from both the L2 cache and L3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * cache by the respective indexes. Flushes all ways of the line from
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * each cache.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * l2_index Index into the L2$ of the line to be flushed. This
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * register will not be modified by this routine.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * l3_index Index into the L3$ of the line to be flushed. This
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * register will not be modified by this routine.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * scr2 scratch register.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * scr3 scratch register.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Panther version of ecache_flush_line. Flushes the line corresponding
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * to physaddr from both the L2 cache and the L3 cache.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * physaddr Input: Physical address to flush.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Output: Physical address to flush (preserved).
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * l2_idx_out Input: scratch register.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Output: Index into the L2$ of the line to be flushed.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * l3_idx_out Input: scratch register.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Output: Index into the L3$ of the line to be flushed.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * scr3 scratch register.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * scr4 scratch register.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#define PN_ECACHE_FLUSH_LINE(physaddr, l2_idx_out, l3_idx_out, scr3, scr4) \
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* !lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala{return 0;}
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! since we disable interrupts, we don't need to do kpreempt_disable()
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala rdpr %pstate, %o2
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala andn %o2, PSTATE_IE, %g1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala wrpr %g0, %g1, %pstate ! disable interrupts
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Save current DCU state. Turn off IPS
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala setx DCU_IPS_MASK, %g2, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala andn %g1, %o3, %g4
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g4, [%g0]ASI_DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala clr %o5 ! assume success
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %g2, %g3)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! Check if line is invalid; if so, NA it.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ldxa [%o0]ASI_L2_TAG, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala btst 0x7, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala bnz %xcc, 2f
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %o1, [%o0]ASI_L2_TAG
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala membar #Sync ! still on same cache line
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! now delay 15 cycles so we don't have hazard when we return
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! UNPARK-SIBLING_CORE is 7 instructions, so we cross a cache boundary
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Restore the DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala{return 0;}
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! since we disable interrupts, we don't need to do kpreempt_disable()
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala rdpr %pstate, %o2
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala andn %o2, PSTATE_IE, %g1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala wrpr %g0, %g1, %pstate ! disable interrupts
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Save current DCU state. Turn off IPS
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala setx DCU_IPS_MASK, %g2, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala andn %g1, %o3, %g4
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g4, [%g0]ASI_DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala flush %g0 /* flush required after changing the IC bit */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %o5, %g2)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala clr %o5 ! assume success
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! Check that line is in NA state; if so, INV it.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ldxa [%o0]ASI_L2_TAG, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala and %o3, 0x7, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala cmp %o3, 0x5
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! now delay 15 cycles so we don't have hazard when we return
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala mov 16, %o1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala brnz,pt %o1, 1b
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! UNPARK-SIBLING_CORE is 7 instructions
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Restore the DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g1, [%g0]ASI_DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala wrpr %g0, %o2, %pstate !restore pstate
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala mov %o5, %o0
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaunretire_l2_end:
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala SET_SIZE(unretire_l2)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaretire_l3(uint64_t tag_addr, uint64_t pattern)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala{return 0;}
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ENTRY(retire_l3)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaretire_l3_start:
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! since we disable interrupts, we don't need to do kpreempt_disable()
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Save current DCU state. Turn off IPS
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala flush %g0 /* flush required after changing the IC bit */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! now delay 15 cycles so we don't have hazard when we return
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala mov 16, %o1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala brnz,pt %o1, 1b
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! UNPARK-SIBLING_CORE is 7 instructions, so we cross a cache boundary
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Restore the DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g1, [%g0]ASI_DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala wrpr %g0, %o2, %pstate !restore pstate
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala mov %o5, %o0
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! It is OK to have STATE as NA (if so, nothing to do!)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala and %o3, 0x7, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala cmp %o3, 0x5
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala be,a,pt %xcc, 9b
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala inc %o5 ! indicate was already NA
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! Hmm. Not INV, not NA
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaretire_l3_end:
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala SET_SIZE(retire_l3)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaunretire_l3(uint64_t tag_addr, uint64_t pattern)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala{return 0;}
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ENTRY(unretire_l3)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaunretire_l3_start:
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! since we disable interrupts, we don't need to do kpreempt_disable()
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Save current DCU state. Turn off IPS
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala flush %g0 /* flush required after changing the IC bit */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala dec %o5 ! indicate not NA
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g0, [%o0]ASI_EC_DIAG
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala membar #Sync
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! now delay 15 cycles so we don't have hazard when we return
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Restore the DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaretire_l2_alternate(uint64_t tag_addr, uint64_t pattern)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala{return 0;}
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! since we disable interrupts, we don't need to do kpreempt_disable()
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala rdpr %pstate, %o2
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala andn %o2, PSTATE_IE, %g1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala wrpr %g0, %g1, %pstate ! disable interrupts
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Save current DCU state. Turn off IPS
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala setx DCU_IPS_MASK, %g2, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala andn %g1, %o3, %g4
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g4, [%g0]ASI_DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala clr %o5 ! assume success
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %g2, %g3)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! Check if line is invalid; if so, NA it.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ldxa [%o0]ASI_L2_TAG, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala btst 0x7, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala bnz %xcc, 2f
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %o1, [%o0]ASI_L2_TAG
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala membar #Sync ! still on same cache line
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! now delay 15 cycles so we don't have hazard when we return
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! UNPARK-SIBLING_CORE is 7 instructions, so we cross a cache boundary
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Restore the DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaunretire_l2_alternate(uint64_t tag_addr, uint64_t pattern)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala{return 0;}
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! since we disable interrupts, we don't need to do kpreempt_disable()
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala rdpr %pstate, %o2
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala andn %o2, PSTATE_IE, %g1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala wrpr %g0, %g1, %pstate ! disable interrupts
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Save current DCU state. Turn off IPS
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala setx DCU_IPS_MASK, %g2, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala andn %g1, %o3, %g4
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g4, [%g0]ASI_DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala flush %g0 /* flush required after changing the IC bit */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %o5, %g2)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala clr %o5 ! assume success
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! Check that line is in NA state; if so, INV it.
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ldxa [%o0]ASI_L2_TAG, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala and %o3, 0x7, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala cmp %o3, 0x5
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! now delay 15 cycles so we don't have hazard when we return
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala mov 16, %o1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala brnz,pt %o1, 1b
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! UNPARK-SIBLING_CORE is 7 instructions
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Restore the DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g1, [%g0]ASI_DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala wrpr %g0, %o2, %pstate !restore pstate
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala mov %o5, %o0
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala SET_SIZE(unretire_l2_alternate)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaretire_l3_alternate(uint64_t tag_addr, uint64_t pattern)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala{return 0;}
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ENTRY(retire_l3_alternate)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! since we disable interrupts, we don't need to do kpreempt_disable()
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Save current DCU state. Turn off IPS
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala flush %g0 /* flush required after changing the IC bit */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! now delay 15 cycles so we don't have hazard when we return
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala mov 16, %o1
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala brnz,pt %o1, 1b
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! UNPARK-SIBLING_CORE is 7 instructions, so we cross a cache boundary
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Restore the DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g1, [%g0]ASI_DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala wrpr %g0, %o2, %pstate !restore pstate
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala mov %o5, %o0
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! It is OK to have STATE as NA (if so, nothing to do!)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala and %o3, 0x7, %o3
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala cmp %o3, 0x5
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala be,a,pt %xcc, 9b
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala inc %o5 ! indicate was already NA
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! Hmm. Not INV, not NA
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala SET_SIZE(retire_l3_alternate)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaunretire_l3_alternate(uint64_t tag_addr, uint64_t pattern)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala{return 0;}
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ENTRY(unretire_l3_alternate)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! since we disable interrupts, we don't need to do kpreempt_disable()
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Save current DCU state. Turn off IPS
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala flush %g0 /* flush required after changing the IC bit */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala dec %o5 ! indicate not NA
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala stxa %g0, [%o0]ASI_EC_DIAG
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala membar #Sync
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala ! now delay 15 cycles so we don't have hazard when we return
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Restore the DCU
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaget_ecache_dtags_tl1(uint64_t afar, ch_cpu_logout_t *clop)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaget_l2_tag_tl1(uint64_t tag_addr, uint64_t tag_data_ptr)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Now read the tag data
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#if defined(lint)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala/*ARGSUSED*/
142c9f13e148d687426ed2d4e8bd93717eeaebbcbalaget_l3_tag_tl1(uint64_t tag_addr, uint64_t tag_data_ptr)
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala * Now read the tag data
142c9f13e148d687426ed2d4e8bd93717eeaebbcbala#endif /* lint */