pcf8584.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* pcf8584.c is the nexus driver for all pcf8584 controller
* implementations. It supports both interrupt and polled
* mode operation, but defaults to interrupt.
*/
#include <sys/archsystm.h>
#include <sys/platform_module.h>
/*
* static function declarations
*/
static struct bus_ops pcf8584_busops = {
nullbusmap, /* bus_map */
NULL, /* bus_get_intrspec */
NULL, /* bus_add_intrspec */
NULL, /* bus_remove_intrspec */
NULL, /* bus_map_fault */
ddi_no_dma_map, /* bus_dma_map */
ddi_no_dma_allochdl, /* bus_dma_allochdl */
ddi_no_dma_freehdl, /* bus_dma_freehdl */
ddi_no_dma_bindhdl, /* bus_dma_bindhdl */
ddi_no_dma_unbindhdl, /* bus_unbindhdl */
ddi_no_dma_flush, /* bus_dma_flush */
ddi_no_dma_win, /* bus_dma_win */
ddi_no_dma_mctl, /* bus_dma_ctl */
pcf8584_bus_ctl, /* bus_ctl */
ddi_bus_prop_op, /* bus_prop_op */
NULL, /* bus_get_eventcookie */
NULL, /* bus_add_eventcall */
NULL, /* bus_remove_eventcall */
NULL, /* bus_post_event */
0, /* bus_intr_ctl */
0, /* bus_config */
0, /* bus_unconfig */
0, /* bus_fm_init */
0, /* bus_fm_fini */
0, /* bus_fm_access_enter */
0, /* bus_fm_access_exit */
0, /* bus_power */
i_ddi_intr_ops /* bus_intr_op */
};
struct cb_ops pcf8584_cb_ops = {
pcf8584_open, /* open */
pcf8584_close, /* close */
nodev, /* strategy */
nodev, /* print */
nodev, /* dump */
nodev, /* read */
nodev, /* write */
pcf8584_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
ddi_prop_op, /* cb_prop_op */
0, /* streamtab */
};
static struct dev_ops pcf8584_ops = {
0,
};
&mod_driverops, /* Type of module. This one is a driver */
"I2C Nexus Driver %I%", /* Name of the module. */
&pcf8584_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
&modldrv,
};
/*
* pcf8584 soft state
*/
static void *pcf8584_state;
};
/*
* The "interrupt_priorities" property is how a driver can specify a SPARC
* PIL level to associate with each of its interrupt properties. Most
* self-identifying busses have a better mechanism for managing this, but I2C
* doesn't.
*/
int pcf8584_pil = PCF8584_PIL;
#ifdef DEBUG
int pcf8584_print_lvl = 0;
static kmutex_t msg_buf_lock;
static char msg_buff[1024];
#define PCF8584_DDB(command) \
do { \
{ command; } \
} while (0)
static void
{
if (flags & pcf8584_print_lvl) {
if (pcf8584_print_lvl & PRT_PROM) {
} else {
if (pcf8584_print_lvl & PRT_BUFFONLY) {
} else {
}
}
}
}
#else
#define PCF8584_DDB(command) \
do { \
} while (0)
#endif
int
_init(void)
{
int status;
if (status != 0) {
return (status);
}
}
return (status);
}
int
_fini(void)
{
int status;
}
return (status);
}
/*
* The loadable-module _info(9E) entry point
*/
int
{
}
static void
{
}
}
}
}
"interrupt-priorities");
}
}
}
static int
{
/*
* Allocate soft state structure.
*/
return (DDI_FAILURE);
}
"interrupt-priorities") != 1) {
DDI_PROP_CANSLEEP, "interrupt-priorities",
sizeof (pcf8584_pil));
}
goto bad;
}
} else {
if (ddi_get_iblock_cookie(dip, 0,
(void *)i2c->pcf8584_icookie);
} else {
i2c->pcf8584_name);
}
} else {
}
}
/*
* For polled mode, still initialize a cv and mutex
*/
}
DDI_NT_NEXUS, 0) == DDI_FAILURE) {
i2c->pcf8584_name);
goto bad;
}
return (DDI_SUCCESS);
bad:
return (DDI_FAILURE);
}
static int
{
switch (cmd) {
case DDI_ATTACH:
return (pcf8584_doattach(dip));
case DDI_RESUME:
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
}
}
static int
{
switch (cmd) {
case DDI_DETACH:
return (DDI_SUCCESS);
case DDI_SUSPEND:
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
}
}
/*ARGSUSED*/
static int
{
int instance;
/*
* Make sure the open is for the right file type
*/
return (EINVAL);
return (ENXIO);
/*
* Enforce exclusive access
*/
if (i2c->pcf8584_open) {
return (EBUSY);
} else
return (0);
}
/*ARGSUSED*/
static int
{
int instance;
/*
* Make sure the close is for the right file type
*/
return (EINVAL);
return (ENXIO);
i2c->pcf8584_open = 0;
return (0);
}
/*ARGSUSED*/
static int
int *rvalp)
{
struct devctl_iocdata *dcp;
int rv;
return (ENXIO);
/*
* read devctl ioctl data
*/
return (EFAULT);
}
switch (cmd) {
case DEVCTL_BUS_DEV_CREATE:
break;
case DEVCTL_DEVICE_REMOVE:
break;
default:
}
return (rv);
}
static int
{
switch (op) {
case DDI_CTLOPS_INITCHILD:
case DDI_CTLOPS_UNINITCHILD:
return (DDI_SUCCESS);
return (DDI_SUCCESS);
case DDI_CTLOPS_DMAPMAPC:
case DDI_CTLOPS_POKE:
case DDI_CTLOPS_PEEK:
case DDI_CTLOPS_IOMIN:
case DDI_CTLOPS_REPORTINT:
case DDI_CTLOPS_SIDDEV:
case DDI_CTLOPS_SLAVEONLY:
case DDI_CTLOPS_AFFINITY:
case DDI_CTLOPS_PTOB:
case DDI_CTLOPS_BTOP:
case DDI_CTLOPS_BTOPR:
case DDI_CTLOPS_INTR_HILEVEL:
case DDI_CTLOPS_XLATE_INTRS:
case DDI_CTLOPS_DVMAPAGESIZE:
return (DDI_FAILURE);
default:
}
}
/*
* pcf8584_suspend() is called before the system suspends. Existing
* transfer in progress or waiting will complete, but new transfers are
* effectively blocked by "acquiring" the bus.
*/
static void
{
int instance;
}
/*
* pcf8584_resume() is called when the system resumes from CPR. It releases
* the hold that was placed on the i2c bus, which allows any real
* transfers to continue.
*/
static void
{
int instance;
}
/*
* pcf8584_acquire() is called by a thread wishing to "own" the I2C bus.
* It should not be held across multiple transfers. If the 'force' flag
* is set, do not try to acquire mutex or do cv_wait.
*/
static void
{
if (force) {
return;
}
while (i2c->pcf8584_busy) {
}
/*
* On systems where OBP shares a pcf8584 controller with the
* OS, plat_shared_i2c_enter will serialize access to the
* pcf8584 controller. Do not grab this lock during CPR
* suspend as the CPR thread also acquires this muxex
* through through prom_setprop which causes recursive
* mutex enter.
*
* dip == NULL during CPR.
*/
}
}
/*
* pcf8584_release() is called to release a hold made by pcf8584_acquire().
*/
static void
{
if (force) {
i2c->pcf8584_busy = 0;
return;
}
i2c->pcf8584_busy = 0;
}
}
/*
* if pcf8584_b_reg exists, it means the current bus controller signals
* are multiplexed into more than a single bus. Select the bus needed
* by writing to the mux register.
*/
static void
{
int bus;
/*
* The existence of pcf8584_b_reg means the bus registers
* are multiplexed.
*/
i2c->pcf8584_b_reg));
"transmitting bus number %d\n", bus));
}
}
/*
* pcf8584_type_to_state() converts a transfer type to the
* next state of the I2C state machine based on the requested
* transfer type.
*/
static enum tran_state
{
switch (i2c_flags) {
case I2C_WR:
return (TRAN_STATE_WR);
case I2C_RD:
return (TRAN_STATE_DUMMY_RD);
case I2C_WR_RD:
return (TRAN_STATE_WR_RD);
}
/*NOTREACHED*/
}
/*
* pcf8584_put_s1() writes out cmd to register S1.
*/
static void
{
/*
* read status to make sure write is flushed
*/
}
/*
* pcf8584_put_s0() writes out data to register S0.
*/
static void
{
/*
* read status to make sure write is flushed
*/
}
/*
* pcf8584_get_s0() reads from register S0.
*/
static uint8_t
{
}
/*
* pcf8584_get_s1() reads from register S1.
*/
static uint8_t
{
}
/*
* If the previous transaction was a write, the stop
* bit may not make it out on the wire before
* the next transaction startes. And unfortunately, there
* is no interrupt after the stop bit is written, so this
* function will poll to make sure the BBC is ready.
*/
static int
{
int usecwaits = 0;
if (usecwaits++ == 100) {
/* Try initializing the bus */
delay(1);
(void) pcf8584_get_s0(i2c);
"!%s: cleared bus busy. addr=0x%x",
return (I2C_SUCCESS);
} else {
"!%s bus busy after init addr=0x%x",
return (I2C_FAILURE);
}
}
drv_usecwait(1);
}
return (I2C_SUCCESS);
}
static int
{
"!%s bus error; Controller = 0x%x "
return (I2C_FAILURE);
return (I2C_FAILURE);
/*
* No error logged here, because this may be benign.
* Cf. the "Alert Response Address" feature of SMBUS.
*/
return (I2C_FAILURE);
}
return (I2C_SUCCESS);
}
static void
{
}
static int
{
int len;
int err;
char name[30];
ddi_node_name(cdip)));
DDI_PROP_CANSLEEP, "#address-cells",
return (DDI_FAILURE);
}
if (err != DDI_PROP_SUCCESS ||
return (DDI_FAILURE);
}
if (cell_size == 1) {
} else if (cell_size == 2) {
} else {
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
static void
{
ddi_node_name(cdip)));
}
static void
{
/*
* The default case is to set the clock divisor to the least common
* denominator to avoid over clocking the I2C bus. Assume that
* BBC based systems are using the Safari clock as input, so select
* the clk divisor based on it.
*/
int clock_freq;
root_node = ddi_root_node();
DDI_PROP_DONTPASS, "clock-frequency", 0);
if (clock_freq < 105000000) {
clk_div = 0x00;
} else if (clock_freq < 160000000) {
clk_div = 0x10;
} else {
clk_div = 0x1C;
}
}
/* set I2C clock speed */
/*
* Multi-Master: Wait for a period of time equal to the
* longest I2C message. This accounts for the case
* where multiple controllers and, if this particular one
* is "lagging", misses the BB(bus busy) condition.
* We wait 200 ms since the longest transaction at this time
* on the i2c bus is a 256 byte read from the seprom which takes
* about 75 ms. Some additional buffer does no harm to the driver.
*/
}
/*
* pcf8584_setup_regs() is called to map in registers specific to
* the pcf8584.
*/
static int
{
int nregs;
return (DDI_FAILURE);
}
if (ddi_regs_map_setup(dip, 0,
return (DDI_FAILURE);
}
/*
* If i2c controller is on BBC, then s1 comes before s0.
*/
} else {
}
if (nregs > 1) {
if (ddi_regs_map_setup(dip,
DDI_SUCCESS) {
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
}
/*
* pcf8584_free_regs() frees any registers previously
* allocated.
*/
static void
{
}
}
}
static void
{
}
/*
* i2_nexus_dip_to_addr() takes a dip and returns an I2C address.
*/
static int
{
return (ppvt->pcf8584_ppvt_addr);
}
/*
* pcf8584_intr() is the interrupt service routine registered during
* attach, and remains registered even if the driver is in POLLED mode. So if
* this is called from POLLED mode, it needs to return without doing
* any work to prevent the I2C bus from entering an unknown state.
*/
static uint_t
{
/*
* It is necessary to check both whether the hardware is interrupting
* and that there is a current transaction for the bus in progress.
* Checking just one but not the other will lead to a panic on xcal
* since both controllers share the same ino, and also because OBP
* shares a controller with the kernel even while the kernel is running.
*/
return (DDI_INTR_UNCLAIMED);
}
return (DDI_INTR_UNCLAIMED);
}
} else
return (DDI_INTR_CLAIMED);
}
/*
* Interrupt occurs after a byte is transmitted or received, indicating
* the device is ready to be serviced.
*/
static int
{
int dummy_read;
switch (i2c->pcf8584_tran_state) {
case TRAN_STATE_DUMMY_DATA:
"TRAN_STATE_DUMMY DATA: write dummy %x\n", DUMMY_DATA));
return (I2C_COMPLETE);
}
return (I2C_PENDING);
case TRAN_STATE_START:
"TRAN_STATE_START failure\n"));
return (I2C_COMPLETE);
}
/* Set read bit if this is a read transaction */
}
"TRAN_STATE_START: write addr: %x\n", addr));
return (I2C_PENDING);
case TRAN_STATE_WR:
"TRAN_STATE_WR failure\n"));
return (I2C_COMPLETE);
}
/* check to see if at end of buffer */
if (tp->i2c_w_resid == 0) {
"TRAN_STATE_WR: write STOP\n"));
return (I2C_COMPLETE);
}
tp->i2c_w_resid--]);
"TRAN_STATE_WR: write data %x\n",
return (I2C_PENDING);
case TRAN_STATE_DUMMY_RD:
return (I2C_COMPLETE);
}
/*
* The first read is always a dummy read, because reading S0
* is what starts bit shifting and ACK on the I2c bus.
* This byte is accessed during the next read, which starts
* another 8 bit bus shift.
*
* special case for 1 byte reads: Clear the ACK bit
* here since this read causes the last and only byte
* to be sent on the I2C bus.
*/
}
/*
* dummy read
*/
"TRAN_STATE_DUMMY_RD: read dummy %d\n", dummy_read));
return (I2C_PENDING);
case TRAN_STATE_RD:
"TRAN_STATE_RD failure\n"));
return (I2C_COMPLETE);
}
/*
* If resid == 1, the last byte has already been shifted into
* the accumulator. Send the stop bit. This also prevents the
* last S0 read from shifting in another byte from the I2C bus.
*/
}
/*
* If resid == 2, then the next read will cause the I2C bus to
* start shifting in the last byte on the I2C bus, which we
* don't want to be ACK'd, so clear the ACK bit.
*/
}
"TRAN_STATE_RD: returning. i2c_rlen = %d "
tp->i2c_r_resid]));
if (--tp->i2c_r_resid == 0) {
return (I2C_COMPLETE);
}
return (I2C_PENDING);
case TRAN_STATE_WR_RD:
return (I2C_COMPLETE);
}
"TRAN_STATE_WR_RD sending STOP\n"));
return (I2C_COMPLETE);
}
if (tp->i2c_w_resid != 0) {
tp->i2c_w_resid--]);
"TRAN_STATE_WR_RD: write data %x\n",
} else {
"TRAN_STATE_WR_RD: write addr "
}
return (I2C_PENDING);
default:
return (I2C_COMPLETE);
}
}
/*
* pcf8584_transfer() is the function that is registered with
* I2C services to be called from pcf8584_transfer() for each transfer.
*
* This function starts the transfer, and then waits for the
* interrupt or polled thread to signal that the transfer has
* completed.
*/
int
{
int saved_mode, took_over = 0;
extern int do_polled_io;
/*
* If we're explicitly asked to do polled io (or if we are panic'ing),
* we need to usurp ownership of the I2C bus, bypassing any other
* waiters.
*/
took_over = 1;
} else {
/*
* See if someone else had intruded and taken over the bus
* between the 'pcf8584_acquire' and 'mutex_enter' above.
* If so, we'll have to start all over again.
*/
goto begin;
}
}
if (took_over)
else {
}
}
/*
* Bus selection must be followed by pcf8584_bbn_ready(),
* otherwise the bus can be switched before the stop
* bit is written out, causing the stop bit to get
* sent to the wrong (new) bus. This causes the
* previous bus to permanently hang waiting for the
* stop bit.
*/
"FIRST WRITE DUMMY ADDR: write %x\n", DUMMY_ADDR));
/*
* Update transfer status so any polled i/o request coming in
* after this will complete this transfer for us, before issuing
* its own.
*/
if (took_over)
else {
/*
* Release the I2C bus only if we still own it. If we don't
* own it (someone usurped it from us while we were waiting),
* we still need to drop the lock that serializes access to
* the pcf8584 controller on systems where OBP shares the
* controller with the OS.
*/
else if (&plat_shared_i2c_exit && dip)
}
return (tp->i2c_result);
}
static void
{
int completed = I2C_PENDING;
while (completed != I2C_COMPLETE) {
}
drv_usecwait(1);
}
}
/*
* pcf8584_take_over() grabs the I2C bus and other resources by force and
* flushes any pending transaction. This is called if a polled i/o
* request comes in.
*/
static void
{
/*
* We need to flush out any currently pending transaction before
* issuing ours.
*/
if (i2c->pcf8584_busy) {
if (i2c->pcf8584_cur_tran &&
}
}
/*
* Since pcf8584_acquire() is by default a good citizen that
* will wait its turn to acquire the I2C bus, we need to set
* the 'force' flag on.
*/
}
/*
* pcf8584_give_up() returns all resources that were taken over forcefully
*/
static void
{
/*
* Note that pcf8584_release only wakes up threads waiting to acquire
* the I2C bus. We still need to wake up the waiter from whom we
* usurped the bus.
*/
if (waiter)
}