fpc-impl-4u.c revision 110e73f9b5ccaa10e26a8f79807001a5da72604e
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/pci_tools.h>
#include <fpc.h>
#include <fpc-impl.h>
#define CHIP_COMPATIBLE_NAME "pciex108e,80f0"
#define BANK_ADDR_MASK 0x7FFFFF
#define PCIE_BANK 0
#define JBUS_BANK 1
typedef struct px_regs {
} px_regs_t;
/* There is one of these for every root nexus device found */
typedef struct fire4u_specific {
char *nodename;
typedef struct fire_counter_handle_impl {
static uint64_t counter_select_offsets[] = {
};
/*
* The following event and offset arrays is organized by grouping in major
* order the fire_perfcnt_t register types, and in minor order the register
* numbers within that type.
*/
static uint64_t counter_reg_offsets[] = {
};
/*
* Add the following to one of the LPU_LINK_PERFORMANCE_COUNTERx offsets to
* write a value to that counter.
*/
#define LPU_LINK_PERFCTR_WRITE_OFFSET 0x8
/*
* Note that LPU_LINK_PERFORMANCE_COUNTER_CONTROL register is hard-reset to
* zeros and this is the value we want. This register isn't touched by this
* module, and as long as it remains untouched by other modules we're OK.
*/
static ldi_ident_t ldi_identifier;
int
{
int status;
credentials = crget();
if (status == 0)
}
int
{
int index;
char *name;
int nodename_size;
char *compatible = NULL;
int regs_length = 0;
return (DDI_SUCCESS);
return (DDI_SUCCESS);
}
/* Get register banks. */
goto bad_regs_p;
}
goto bad_regs_length;
}
if (index == 0)
else
*avail |= PCIE_B_REGS_AVAIL;
return (DDI_SUCCESS);
if (regs_p)
if (nodename)
return (DDI_FAILURE);
}
void
fpc_platform_node_fini(void *arg)
{
return;
}
/*ARGSUSED*/
void
{
if (ldi_identifier_valid)
if (credentials)
}
{
if ((handle_impl->devspec =
}
return ((fire_perfreg_handle_t)-1);
} else {
return ((fire_perfreg_handle_t)handle_impl);
}
}
int
{
return (SUCCESS);
}
int
{
int rval;
int ioctl_rval;
} else {
/*
* Note that a pcie_bank_base isn't needed. Pcie register
* offsets are already relative to the start of their bank. No
* base needs to be subtracted to get the relative offset that
* pcitool ioctls want.
*/
}
/* Read original value. */
}
return (rval);
}
int
{
int rval;
int ioctl_rval;
int command =
/*
* Note that stated PCIE offsets are relative to the beginning of their
* register bank, while JBUS offsets are absolute.
*/
} else {
}
}
}
return (rval);
}