/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1999-2001 by Sun Microsystems, Inc.
* All rights reserved.
*/
/*
* Platform Power Management
*
* Register and bit definitions of the power-related parts
*/
#ifndef _SYS_XCALPPM_REG_H
#define _SYS_XCALPPM_REG_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Registers accessed by the ppm driver. These registers actually come
* from different ASICs on the system and are collected for us
* by the prom into a single device node. These registers are:
*
* BBC E* Control Register (other registers like E* Assert Change Time
* or E* PLL Settle Time are offseted from this address)
* Mode Auxio Register
* SuperI/O Configuration Register
* SuperI/O GPIO Registers
*/
struct xcppmreg {
};
struct xcppmhndl {
};
/*
* Register offsets
*/
/*
* Definitions for the RIO Mode Auxio register
*/
/*
* Index for SuperIO Configuration 2 register
*/
/*
* GPIO Data Port 1 bit assignments
*/
/*
* GPIO Data Port 2 bit assignments
*/
/*
* BBC timing registers are set according to "bbc_delay" variable
* and adjusted based on current clock speed.
*/
extern int bbc_delay; /* microsec */
/*
* BBC E* Control Reg bit masks
*/
/*
* register access IO
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_XCALPPM_REG_H */