hpc3130_dak.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2000-2001, 2003 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_HPC3130_DAK_H
#define _SYS_HPC3130_DAK_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(_KERNEL)
/* masks */
#define HPC3130_GCR 0x00
#define HPC3130_STATUS 0x01
#define HPC3130_CONTROL 0x02
#define HPC3130_ATTEN 0x03
#define HPC3130_EVENT_STATUS 0x06
#define HPC3130_INTERRUPT 0x07
#define HPC3130_NO_REGISTER 0xff
/*
* masks
*/
/*
* more masks
*/
/* (R/W) Logical level of SLOTRST# (used to reset a slot) */
#define HPC3130_SLOTRST 0x01
/* (R/W) Logical level of CLKON# (used to control clock signal) */
#define HPC3130_CLKON 0x02
/* (R/W) Logical level of REQ64ON# signal */
#define HPC3130_REQ64 0x04
/* (R/W) Logical level of SLOTREQ64# signal */
#define HPC3130_SLOTREQ64 0x08
/* (R/W) Bus control (for auto sequence level==1?disconnect:connect */
#define HPC3130_BUS_CTL 0x10
/* (R/W) Logical level of power control on the slot */
#define HPC3130_SLTPWRCTL 0x20
#define HPC3130_ATTN0 0x00
#define HPC3130_ATTN1 0x01
#define HPC3130_LED_FAULT HPC3130_ATTN1
#define HPC3130_LED_OK2REM HPC3130_ATTN0
#define HPC3130_ATTN_OFF 0x00
#define HPC3130_ATTN_FST 0x02
#define HPC3130_ATTN_ON 0x03
/*
* These two macros map between the Hot Plug Services LED constants
* HPC3130 hardware.
*/
static char hpc3130_to_hpc_led_map[] = {
};
static char hpc3130_from_hpc_led_map[] = {
};
#define HPC3130_MAX_SLOT 0x4
/*
* This structure defines an element of the controller's
* slot table array
*/
typedef struct hpc3130_slot_table_entry hpc3130_slot_table_entry_t;
typedef struct hpc3130_callback_arg hpc3130_callback_arg_t;
struct hpc3130_callback_arg {
};
struct hpc3130_slot_table_entry {
char nexus[MAXNAMELEN];
};
/*
* The soft state structure
*/
struct hpc3130_unit {
/*
* the following fields hold the value of the "slot-table"
* property for this controller
*/
/*
* the following fields represent the array of hot-plug
* slots derived from the "slot-table" property
*/
/*
* Mutex associated with this structure
*/
/*
* Trap interrupt cookie
*/
/*
* Open flag
*/
int hpc3130_oflag;
/*
* An integer field describing the type
*/
/*
* A place to put the name of this driver
* What gets put here is "hpc3130n" - where
* n is the instance number.
*/
char hpc3130_name[16];
/*
* The handle within the I2C nexus that this instance
* represents.
*/
/*
* condition variable used to throttle power OK signal
*/
/*
* Present vector - if B_TRUE there is a card in the corresponding
* slot.
*/
/*
* Power vector - if B_TRUE, then power is applied to the slot
*/
/*
* Enable vector - if B_TRUE the slot is enabled.
*/
/*
* LED state indicators.
*/
char fault_led[HPC3130_MAX_SLOT];
char ok2rem_led[HPC3130_MAX_SLOT];
/* For poll(9e)/ioctl(HPC3130_GET_SOFT_EVENT */
};
typedef struct hpc3130_unit hpc3130_unit_t;
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_HPC3130_DAK_H */