* pan_disable_ism_large_pages and pan_disable_large_pages are the Panther- * specific versions of disable_ism_large_pages and disable_large_pages, * and feed back into those two hat variables at hat initialization time, * for Panther-only systems. * disable_large_pages. Ditto for pan_disable_large_pages. * Note that the Panther and Ch/Jaguar ITLB do not support 32M/256M pages. * The function returns the USIII+(i)-IV+ mmu-specific values for the * hat's disable_large_pages and disable_ism_large_pages variables. * Currently the hat's disable_large_pages and disable_ism_large_pages * already contain the generic sparc 4 page size info, and the return * values are or'd with those values. * If a platform is running with only Ch+ or Jaguar, and then someone DR's * in a Panther board, the Panther mmu will not like it if one of the already * running threads is context switched to the Panther and tries to program * a 512K or 4M page into the T512_1. So make these platforms pay the price * and follow the Panther DTLB restrictions by default. :) * The mmu_init_mmu_page_sizes code below takes care of heterogeneous * platforms that don't support DR, like daktari. * The effect of these restrictions is to limit the allowable values in * sfmmu_pgsz[0] and sfmmu_pgsz[1], since these hat variables are used in * mmu_set_ctx_page_sizes to set up the values in the sfmmu_cext that * are used at context switch time. The value in sfmmu_pgsz[0] is used in * P_pgsz0 and sfmmu_pgsz[1] is used in P_pgsz1, as per Figure F-1-1 * IMMU and DMMU Primary Context Register in the Panther Implementation * Supplement and Table 15-21 DMMU Primary Context Register in the #
endif /* MIXEDCPU_DR_SUPPORTED */ * init_mmu_page_sizes is set to one after the bootup time initialization * via mmu_init_mmu_page_sizes, to indicate that mmu_page_sizes has a * mmu_init_large_pages is called with the desired ism_pagesize parameter, * for Panther-only systems. It may be called from set_platform_defaults, * if some value other than 4M is desired, for Panther-only systems. * mmu_ism_pagesize is the tunable. If it has a bad value, then only warn, * since it would be bad form to panic due * The function re-initializes the disable_ism_large_pages and * pan_disable_large_pages variables, which are closely related. * Aka, if 32M is the desired [D]ISM page sizes, then 256M cannot be allowed * for non-ISM large page usage, or DTLB conflict will occur. Please see the * Panther PRM for additional DTLB technical info. * Re-initialize mmu_page_sizes and friends, for Panther mmu support. * Called during very early bootup from check_cpus_set(). * Can be called to verify that mmu_page_sizes are set up correctly. * Note that ncpus is not initialized at this point in the bootup sequence. /* Cheetah+ and later worst case DTLB parameters */ * The purpose of this code is to indirectly reorganize the sfmmu_pgsz array * in order to handle the Panther mmu DTLB requirements. Panther only supports * the 32M/256M pages in the T512_1 and not in the T16, so the Panther cpu * can only support one of the two largest page sizes at a time (efficiently). * Panther only supports 512K and 4M pages in the T512_0, and 32M/256M pages * in the T512_1. So check the sfmmu flags and ttecnt before enabling * the T512_1 for 32M or 256M page sizes, and make sure that 512K and 4M * requests go to the T512_0. * The tmp_pgsz array comes into this routine in sorted order, as it is * sorted from largest to smallest #pages per pagesize in use by the hat code, * and leaves with the Panther mmu DTLB requirements satisfied. Note that * when the array leaves this function it may not contain all of the page * size codes that it had coming into the function. * Note that for DISM the flag can be set but the ttecnt can be 0, if we * didn't fault any pages in. This allows the t512_1 to be reprogrammed, * because the T16 does not support the two giant page sizes. ouch. * Don't program 2nd dtlb for kernel and ism hat * This implements PAGESIZE programming of the T8s * if large TTE counts don't exceed the thresholds. * Function to set up the page size values used to reprogram the DTLBs, * when page sizes used by a process change significantly. * Don't program 2nd dtlb for kernel and ism hat * hat->sfmmu_pgsz[] is an array whose elements * contain a sorted order of page sizes. Element * 0 is the most commonly used page size, followed * by element 1, and so on. * ttecnt[] is an array of per-page-size page counts * mapped into the process. * If the HAT's choice for page sizes is unsuitable, * we can override it here. The new values written * to the array will be handed back to us later to * do the actual programming of the TLB hardware. * The policy we use for programming the dual T8s on * Cheetah+ and beyond is as follows: * We have two programmable TLBs, so we look at * the two most common page sizes in the array, which * have already been computed for us by the HAT. * If the TTE count of either of a preferred page size * exceeds the number of unlocked T16 entries, * we reprogram one of the T8s to that page size * to avoid thrashing in the T16. Else we program * that T8 to the base page size. Note that we do * not force either T8 to be the base page size if a * process is using more than two page sizes. Policy * decisions about which page sizes are best to use are * left to the upper layers. * Note that for Panther, 4M and 512K pages need to be * programmed into T512_0, and 32M and 256M into T512_1, * so we don't want to go through the MIN/MAX code. * For partial-Panther systems, we still want to make sure * that 4M and 512K page sizes NEVER get into the T512_1. * Since the DTLB flags are not set up on a per-cpu basis, * This implements PAGESIZE programming of the T8s * if large TTE counts don't exceed the thresholds. * The HAT calls this function when an MMU context is allocated so that we * can reprogram the large TLBs appropriately for the new process using * The caller must hold the HAT lock. * If supported, reprogram the TLBs to a larger pagesize. * assert cnum should be invalid, this is because pagesize * can only be changed after a proc's ctxs are invalidated. * sfmmu_setctx_sec() will take care of the * rest of the chores reprogramming the hat->sfmmu_cext * page size values into the DTLBs. * This function assumes that there are either four or six supported page * sizes and at most two programmable TLBs, so we need to decide which * page sizes are most important and then adjust the TLB page sizes * accordingly (if supported). * If these assumptions change, this function will need to be * updated to support whatever the new limits are. * We only consider reprogramming the TLBs if one or more of * the two most used page sizes changes and we're using * large pages in this process, except for Panther 32M/256M pages, * which the Panther T16 does not support. * Handle Panther page dtlb calcs separately. The check * for actual or potential 32M/256M pages must occur * every time due to lack of T16 support for them. * The sort works fine for Ch+/Jag, but Panther has * pagesize restrictions for both DTLBs. /* Check 2 largest values after the sort. */ #
endif /* CPU_IMP_DUAL_PAGESIZE */ /* do not reprogram dt512 tlb */ /* search for a valid segkmem_lpsize */ * no setting for segkmem_lpsize in /etc/system * use default from the table /* nothing found: disable large page kernel heap */