us3_cheetahplus_asm.s revision 750ba2244c23d03e3f43b4967911885b36bbac55
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer * CDDL HEADER START
bb5e3b2f129cc39517b925419c22f69a378ec023eh * The contents of this file are subject to the terms of the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Common Development and Distribution License, Version 1.0 only
bb5e3b2f129cc39517b925419c22f69a378ec023eh * (the "License"). You may not use this file except in compliance
bb5e3b2f129cc39517b925419c22f69a378ec023eh * with the License.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
bb5e3b2f129cc39517b925419c22f69a378ec023eh * See the License for the specific language governing permissions
bb5e3b2f129cc39517b925419c22f69a378ec023eh * and limitations under the License.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * When distributing Covered Code, include this CDDL HEADER in each
bb5e3b2f129cc39517b925419c22f69a378ec023eh * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * If applicable, add the following below this CDDL HEADER, with the
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bb5e3b2f129cc39517b925419c22f69a378ec023eh * CDDL HEADER END
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Use is subject to license terms.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Assembly code support for the Cheetah+ module
bb5e3b2f129cc39517b925419c22f69a378ec023eh#pragma ident "%Z%%M% %I% %E% SMI"
bb5e3b2f129cc39517b925419c22f69a378ec023eh#if !defined(lint)
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* TRAPTRACE */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#if !defined(lint)
bb5e3b2f129cc39517b925419c22f69a378ec023eh/* BEGIN CSTYLED */
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Cheetah+ version to reflush an Ecache line by index.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * By default we assume the Ecache is 2-way so we flush both
bb5e3b2f129cc39517b925419c22f69a378ec023eh * ways. Even if the cache is direct-mapped no harm will come
bb5e3b2f129cc39517b925419c22f69a378ec023eh * from performing the flush twice, apart from perhaps a performance
bb5e3b2f129cc39517b925419c22f69a378ec023eh * penalty.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * XXX - scr2 not used.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Cheetah+ version of ecache_flush_line. Uses Cheetah+ Ecache Displacement
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Flush feature.
bb5e3b2f129cc39517b925419c22f69a378ec023eh#define ECACHE_FLUSH_LINE(physaddr, ec_set_size, scr1, scr2) \
bb5e3b2f129cc39517b925419c22f69a378ec023eh/* END CSTYLED */
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Panther version to reflush a line from both the L2 cache and L3
bb5e3b2f129cc39517b925419c22f69a378ec023eh * cache by the respective indexes. Flushes all ways of the line from
bb5e3b2f129cc39517b925419c22f69a378ec023eh * each cache.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * l2_index Index into the L2$ of the line to be flushed. This
bb5e3b2f129cc39517b925419c22f69a378ec023eh * register will not be modified by this routine.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * l3_index Index into the L3$ of the line to be flushed. This
bb5e3b2f129cc39517b925419c22f69a378ec023eh * register will not be modified by this routine.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * scr2 scratch register.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * scr3 scratch register.
bb5e3b2f129cc39517b925419c22f69a378ec023eh#define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Panther version of ecache_flush_line. Flushes the line corresponding
bb5e3b2f129cc39517b925419c22f69a378ec023eh * to physaddr from both the L2 cache and the L3 cache.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * physaddr Input: Physical address to flush.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Output: Physical address to flush (preserved).
bb5e3b2f129cc39517b925419c22f69a378ec023eh * l2_idx_out Input: scratch register.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Output: Index into the L2$ of the line to be flushed.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * l3_idx_out Input: scratch register.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Output: Index into the L3$ of the line to be flushed.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * scr3 scratch register.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * scr4 scratch register.
bb5e3b2f129cc39517b925419c22f69a378ec023eh#define PN_ECACHE_FLUSH_LINE(physaddr, l2_idx_out, l3_idx_out, scr3, scr4) \
7efa17f5f4c3cc113e1b0a1e86f43d4bf2ede8fafei feng - Sun Microsystems - Beijing China and physaddr, l2_idx_out, l2_idx_out; \
7efa17f5f4c3cc113e1b0a1e86f43d4bf2ede8fafei feng - Sun Microsystems - Beijing China set PN_L2_IDX_DISP_FLUSH, scr3; \
7efa17f5f4c3cc113e1b0a1e86f43d4bf2ede8fafei feng - Sun Microsystems - Beijing China or l2_idx_out, scr3, l2_idx_out; \
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer#endif /* !lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Fast ECC error at TL>0 handler
bb5e3b2f129cc39517b925419c22f69a378ec023eh * We get here via trap 70 at TL>0->Software trap 0 at TL>0. We enter
bb5e3b2f129cc39517b925419c22f69a378ec023eh * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * For a complete description of the Fast ECC at TL>0 handling see the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
bb5e3b2f129cc39517b925419c22f69a378ec023eh#if defined(lint)
bb5e3b2f129cc39517b925419c22f69a378ec023eh#else /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh * This macro turns off the D$/I$ if they are on and saves their
bb5e3b2f129cc39517b925419c22f69a378ec023eh * original state in ch_err_tl1_tmp, saves all the %g registers in the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * ch_err_tl1_data structure, updates the ch_err_tl1_flags and saves
bb5e3b2f129cc39517b925419c22f69a378ec023eh * the %tpc in ch_err_tl1_tpc. At the end of this macro, %g1 will
bb5e3b2f129cc39517b925419c22f69a378ec023eh * point to the ch_err_tl1_data structure and the original D$/I$ state
bb5e3b2f129cc39517b925419c22f69a378ec023eh * will be saved in ch_err_tl1_tmp. All %g registers except for %g1
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * will be available.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * Get the diagnostic logout data. %g4 must be initialized to
bb5e3b2f129cc39517b925419c22f69a378ec023eh * current CEEN state, %g5 must point to logout structure in
bb5e3b2f129cc39517b925419c22f69a378ec023eh * ch_err_tl1_data_t. %g3 will contain the nesting count upon
bb5e3b2f129cc39517b925419c22f69a378ec023eh * If the logout nesting count is exceeded, we're probably
bb5e3b2f129cc39517b925419c22f69a378ec023eh * not making any progress, try to panic instead.
7efa17f5f4c3cc113e1b0a1e86f43d4bf2ede8fafei feng - Sun Microsystems - Beijing China cmp %g3, CLO_NESTING_MAX
7efa17f5f4c3cc113e1b0a1e86f43d4bf2ede8fafei feng - Sun Microsystems - Beijing China bge fecc_tl1_err
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer * Save the current CEEN and NCEEN state in %g7 and turn them off
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer * before flushing the Ecache.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Flush the Ecache, using the largest possible cache size with the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * smallest possible line size since we can't get the actual sizes
bb5e3b2f129cc39517b925419c22f69a378ec023eh * from the cpu_node due to DTLB misses.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Restore CEEN and NCEEN to the previous state.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * If we turned off the D$, then flush it and turn it back on.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Flush the D$.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Turn the D$ back on.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * If we turned off the I$, then flush it and turn it back on.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Flush the I$. Panther has different I$ parameters, and we
bb5e3b2f129cc39517b925419c22f69a378ec023eh * can't access the logout I$ params without possibly generating
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * a MMU miss.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Turn the I$ back on. Changing DCU_IC requires flush.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Get current trap trace entry physical pointer.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Create trap trace entry.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Advance trap trace pointer.
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* TRAPTRACE */
bb5e3b2f129cc39517b925419c22f69a378ec023eh * If nesting count is not zero, skip all the AFSR/AFAR
bb5e3b2f129cc39517b925419c22f69a378ec023eh * handling and just do the necessary cache-flushing.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * If a UCU or L3_UCU followed by a WDU has occurred go ahead
bb5e3b2f129cc39517b925419c22f69a378ec023eh * and panic since a UE will occur (on the retry) before the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * UCU and WDU messages are enqueued.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * We fall into this macro if we've successfully logged the error in
bb5e3b2f129cc39517b925419c22f69a378ec023eh * the ch_err_tl1_data structure and want the PIL15 softint to pick
bb5e3b2f129cc39517b925419c22f69a378ec023eh * it up and log it. %g1 must point to the ch_err_tl1_data structure.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Restores the %g registers and issues retry.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Establish panic exit label.
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#if defined(lint)
bb5e3b2f129cc39517b925419c22f69a378ec023eh * scrubphys - Pass in the aligned physical memory address
bb5e3b2f129cc39517b925419c22f69a378ec023eh * that you want to scrub, along with the ecache set size.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * 1) Displacement flush the E$ line corresponding to %addr.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * The first ldxa guarantees that the %addr is no longer in
bb5e3b2f129cc39517b925419c22f69a378ec023eh * M, O, or E (goes to I or S (if instruction fetch also happens).
bb5e3b2f129cc39517b925419c22f69a378ec023eh * 2) "Write" the data using a CAS %addr,%g0,%g0.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * The casxa guarantees a transition from I to M or S to M.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * 3) Displacement flush the E$ line corresponding to %addr.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * The second ldxa pushes the M line out of the ecache, into the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * writeback buffers, on the way to memory.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * 4) The "membar #Sync" pushes the cache line out of the writeback
bb5e3b2f129cc39517b925419c22f69a378ec023eh * buffers onto the bus, on the way to dram finally.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * This is a modified version of the algorithm suggested by Gary Lauterbach.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
bb5e3b2f129cc39517b925419c22f69a378ec023eh * as modified, but then we found out that for spitfire, if it misses in the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * E$ it will probably install as an M, but if it hits in the E$, then it
bb5e3b2f129cc39517b925419c22f69a378ec023eh * will stay E, if the store doesn't happen. So the first displacement flush
bb5e3b2f129cc39517b925419c22f69a378ec023eh * should ensure that the CAS will miss in the E$. Arrgh.
bb5e3b2f129cc39517b925419c22f69a378ec023eh/* ARGSUSED */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#else /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh GET_CPU_IMPL(%o5) ! Panther Ecache is flushed differently
bb5e3b2f129cc39517b925419c22f69a378ec023eh wrpr %g0, %o4, %pstate ! restore earlier pstate register value
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#if defined(lint)
bb5e3b2f129cc39517b925419c22f69a378ec023eh * clearphys - Pass in the physical memory address of the checkblock
bb5e3b2f129cc39517b925419c22f69a378ec023eh * that you want to push out, cleared with a recognizable pattern,
bb5e3b2f129cc39517b925419c22f69a378ec023eh * from the ecache.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * To ensure that the ecc gets recalculated after the bad data is cleared,
bb5e3b2f129cc39517b925419c22f69a378ec023eh * we must write out enough data to fill the w$ line (64 bytes). So we read
bb5e3b2f129cc39517b925419c22f69a378ec023eh * in an entire ecache subblock's worth of data, and write it back out.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Then we overwrite the 16 bytes of bad data with the pattern.
bb5e3b2f129cc39517b925419c22f69a378ec023eh/* ARGSUSED */
bb5e3b2f129cc39517b925419c22f69a378ec023ehclearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
bb5e3b2f129cc39517b925419c22f69a378ec023eh#else /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* turn off IE, AM bits */
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* turn off NCEEN */
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* align address passed with 64 bytes subblock size */
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* move the good data into the W$ */
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* now overwrite the bad data */
bb5e3b2f129cc39517b925419c22f69a378ec023eh GET_CPU_IMPL(%o3) ! Panther Ecache is flushed differently
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* clear the AFSR */
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* turn NCEEN back on */
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* return and re-enable IE and AM */
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg#endif /* lint */
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * Cheetah+ Ecache displacement flush the specified line from the E$
bb5e3b2f129cc39517b925419c22f69a378ec023eh * For Panther, this means flushing the specified line from both the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * L2 cache and L3 cache.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Register usage:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %o0 - 64 bit physical address for flushing
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %o1 - Ecache set size
bb5e3b2f129cc39517b925419c22f69a378ec023eh/*ARGSUSED*/
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg#else /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh GET_CPU_IMPL(%o3) ! Panther Ecache is flushed differently
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#if defined(lint)
bb5e3b2f129cc39517b925419c22f69a378ec023eh#else /* lint */
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg#endif /* lint */
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * The CPU jumps here from the MMU exception handler if an ITLB parity
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * error is detected and we are running on Panther.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * In this routine we collect diagnostic information and write it to our
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * logout structure (if possible) and clear all ITLB entries that may have
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * caused our parity trap.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * Then we call cpu_tlb_parity_error via systrap in order to drop down to TL0
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * and log any error messages. As for parameters to cpu_tlb_parity_error, we
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * %g2 - Contains the VA whose lookup in the ITLB caused the parity error
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * %g3 - Contains the tlo_info field of the pn_tlb_logout logout struct,
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * regardless of whether or not we actually used the logout struct.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * In the TL0 handler (cpu_tlb_parity_error) we will compare those two
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * parameters to the data contained in the logout structure in order to
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * determine whether the logout information is valid for this particular
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * error or not.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg#else /* lint */
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * Collect important information about the trap which will be
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * used as a parameter to the TL0 handler.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg ldxa [MMU_TAG_ACCESS_EXT]%asi, %g3 ! read the trap VA page size
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg or %g4, %g3, %g3 ! 'or' in the trap context and
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg or %g4, %g3, %g3 ! the tlo_info field for logout
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * at this point:
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * %g2 - contains the VA whose lookup caused the trap
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * %g3 - contains the tlo_info field
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * Next, we calculate the TLB index value for the failing VA.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg PN_GET_TLB_INDEX(%g4, %g5) ! %g4 has the index
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg sllx %g4, PN_TLB_ACC_IDX_SHIFT, %g4 ! shift the index into place
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * at this point:
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * %g2 - contains the VA whose lookup caused the trap
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * %g3 - contains the tlo_info field
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * %g4 - contains the TLB access index value for the
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * VA/PgSz in question
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * Check to see if the logout structure is available.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg GET_CPU_PRIVATE_PTR(%g6, %g1, %g5, itlb_parity_trap_1)
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg sllx %g6, 32, %g6 ! if our logout structure is
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg set LOGOUT_INVALID_L32, %g5 ! unavailable or if it is
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg or %g5, %g6, %g5 ! already being used, then we
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg ldx [%g1 + PN_TLO_ADDR], %g6 ! don't collect any diagnostic
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg cmp %g6, %g5 ! information before clearing
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg bne itlb_parity_trap_1 ! and logging the error.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * Record the logout information. %g4 contains our index + TLB ID
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * for use in ASI_ITLB_ACCESS and ASI_ITLB_TAGREAD. %g1 contains
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg * the pointer to our logout struct.
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg stx %g3, [%g1 + PN_TLO_INFO]
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg stx %g2, [%g1 + PN_TLO_ADDR]
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg stx %g2, [%g1 + PN_TLO_PC] ! %tpc == fault addr for IMMU
0f1b305ee9e700c825d9e9ad1ea1e4311d212eb2Seth Goldberg add %g1, PN_TLO_ITLB_TTE, %g1 ! move up the pointer
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev ldxa [%g4]ASI_ITLB_ACCESS, %g5 ! read the data
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev stx %g5, [%g1 + CH_TLO_TTE_DATA] ! store it away
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev ldxa [%g4]ASI_ITLB_TAGREAD, %g5 ! read the tag
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev stx %g5, [%g1 + CH_TLO_TTE_TAG] ! store it away
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev set PN_TLB_ACC_WAY_BIT, %g6 ! same thing again for way 1
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev or %g4, %g6, %g4
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev add %g1, CH_TLO_TTE_SIZE, %g1 ! move up the pointer
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev ldxa [%g4]ASI_ITLB_ACCESS, %g5 ! read the data
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev stx %g5, [%g1 + CH_TLO_TTE_DATA] ! store it away
e9f896cf06d03b269a2e209d54371788c513a7dbeh ldxa [%g4]ASI_ITLB_TAGREAD, %g5 ! read the tag
e9f896cf06d03b269a2e209d54371788c513a7dbeh stx %g5, [%g1 + CH_TLO_TTE_TAG] ! store it away
e9f896cf06d03b269a2e209d54371788c513a7dbeh andn %g4, %g6, %g4 ! back to way 0
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyevitlb_parity_trap_1:
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev * at this point:
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev * %g2 - contains the VA whose lookup caused the trap
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev * %g3 - contains the tlo_info field
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev * %g4 - contains the TLB access index value for the
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev * VA/PgSz in question
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev * Here we will clear the errors from the TLB.
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev set MMU_TAG_ACCESS, %g5 ! We write a TTE tag value of
799aa485da68fdaa1850eaf833ad108e5af82adbKonstantin Ananyev stxa %g0, [%g5]ASI_IMMU ! 0 as it will be invalid.
e9f896cf06d03b269a2e209d54371788c513a7dbeh stxa %g0, [%g4]ASI_ITLB_ACCESS ! Write the data and tag
e9f896cf06d03b269a2e209d54371788c513a7dbeh membar #Sync
bb5e3b2f129cc39517b925419c22f69a378ec023eh set PN_TLB_ACC_WAY_BIT, %g6 ! same thing again for way 1
bb5e3b2f129cc39517b925419c22f69a378ec023eh or %g4, %g6, %g4
bb5e3b2f129cc39517b925419c22f69a378ec023eh stxa %g0, [%g4]ASI_ITLB_ACCESS ! Write same data and tag
bb5e3b2f129cc39517b925419c22f69a378ec023eh membar #Sync
bb5e3b2f129cc39517b925419c22f69a378ec023eh sethi %hi(FLUSH_ADDR), %g6 ! PRM says we need to issue a
bb5e3b2f129cc39517b925419c22f69a378ec023eh flush %g6 ! flush after writing MMU regs
bb5e3b2f129cc39517b925419c22f69a378ec023eh * at this point:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g2 - contains the VA whose lookup caused the trap
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g3 - contains the tlo_info field
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Call cpu_tlb_parity_error via systrap at PIL 14 unless we're
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#if defined(lint)
bb5e3b2f129cc39517b925419c22f69a378ec023eh * The CPU jumps here from the MMU exception handler if a DTLB parity
bb5e3b2f129cc39517b925419c22f69a378ec023eh * error is detected and we are running on Panther.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * In this routine we collect diagnostic information and write it to our
bb5e3b2f129cc39517b925419c22f69a378ec023eh * logout structure (if possible) and clear all DTLB entries that may have
bb5e3b2f129cc39517b925419c22f69a378ec023eh * caused our parity trap.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Then we call cpu_tlb_parity_error via systrap in order to drop down to TL0
bb5e3b2f129cc39517b925419c22f69a378ec023eh * and log any error messages. As for parameters to cpu_tlb_parity_error, we
bb5e3b2f129cc39517b925419c22f69a378ec023eh * send two:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g2 - Contains the VA whose lookup in the DTLB caused the parity error
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g3 - Contains the tlo_info field of the pn_tlb_logout logout struct,
bb5e3b2f129cc39517b925419c22f69a378ec023eh * regardless of whether or not we actually used the logout struct.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * In the TL0 handler (cpu_tlb_parity_error) we will compare those two
bb5e3b2f129cc39517b925419c22f69a378ec023eh * parameters to the data contained in the logout structure in order to
bb5e3b2f129cc39517b925419c22f69a378ec023eh * determine whether the logout information is valid for this particular
bb5e3b2f129cc39517b925419c22f69a378ec023eh * error or not.
bb5e3b2f129cc39517b925419c22f69a378ec023eh#else /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Collect important information about the trap which will be
bb5e3b2f129cc39517b925419c22f69a378ec023eh * used as a parameter to the TL0 handler.
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldxa [MMU_TAG_ACCESS_EXT]%asi, %g3 ! read the trap VA page sizes
bb5e3b2f129cc39517b925419c22f69a378ec023eh * at this point:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g2 - contains the VA whose lookup caused the trap
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g3 - contains the tlo_info field
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Calculate the TLB index values for the failing VA. Since the T512
bb5e3b2f129cc39517b925419c22f69a378ec023eh * TLBs can be configured for different page sizes, we need to find
bb5e3b2f129cc39517b925419c22f69a378ec023eh * the index into each one separately.
bb5e3b2f129cc39517b925419c22f69a378ec023eh sllx %g4, PN_TLB_ACC_IDX_SHIFT, %g4 ! shift the index into place
bb5e3b2f129cc39517b925419c22f69a378ec023eh sllx %g7, PN_TLB_ACC_IDX_SHIFT, %g7 ! shift the index into place
bb5e3b2f129cc39517b925419c22f69a378ec023eh * at this point:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g2 - contains the VA whose lookup caused the trap
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g3 - contains the tlo_info field
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g4 - contains the T512_0 access index value for the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * VA/PgSz in question
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g7 - contains the T512_1 access index value for the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * VA/PgSz in question
bb5e3b2f129cc39517b925419c22f69a378ec023eh * If this trap happened at TL>0, then we don't want to mess
bb5e3b2f129cc39517b925419c22f69a378ec023eh * with the normal logout struct since that could caused a TLB
bb5e3b2f129cc39517b925419c22f69a378ec023eh * If we are here, then the trap happened at TL>1. Simply
bb5e3b2f129cc39517b925419c22f69a378ec023eh * update our tlo_info field and then skip to the TLB flush
bb5e3b2f129cc39517b925419c22f69a378ec023eh * at this point:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g2 - contains the VA whose lookup caused the trap
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g3 - contains the tlo_info field
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g4 - contains the T512_0 access index value for the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * VA/PgSz in question
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g7 - contains the T512_1 access index value for the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * VA/PgSz in question
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Check to see if the logout structure is available.
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldx [%g1 + PN_TLO_ADDR], %g6 ! don't collect any diagnostic
bb5e3b2f129cc39517b925419c22f69a378ec023eh cmp %g6, %g5 ! information before clearing
bb5e3b2f129cc39517b925419c22f69a378ec023eh bne dtlb_parity_trap_2 ! and logging the error.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Record the logout information. %g4 contains our DTLB_0
bb5e3b2f129cc39517b925419c22f69a378ec023eh * index + TLB ID and %g7 contains our DTLB_1 index + TLB ID
bb5e3b2f129cc39517b925419c22f69a378ec023eh * both of which will be used for ASI_DTLB_ACCESS and
bb5e3b2f129cc39517b925419c22f69a378ec023eh * ASI_DTLB_TAGREAD. %g1 contains the pointer to our logout
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g3, [%g1 + PN_TLO_INFO]
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g2, [%g1 + PN_TLO_ADDR]
bb5e3b2f129cc39517b925419c22f69a378ec023eh rdpr %tpc, %g5
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g5, [%g1 + PN_TLO_PC]
bb5e3b2f129cc39517b925419c22f69a378ec023eh add %g1, PN_TLO_DTLB_TTE, %g1 ! move up the pointer
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldxa [%g4]ASI_DTLB_ACCESS, %g5 ! read the data from DTLB_0
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g5, [%g1 + CH_TLO_TTE_DATA] ! way 0 and store it away
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldxa [%g4]ASI_DTLB_TAGREAD, %g5 ! read the tag from DTLB_0
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g5, [%g1 + CH_TLO_TTE_TAG] ! way 0 and store it away
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldxa [%g7]ASI_DTLB_ACCESS, %g5 ! now repeat for DTLB_1 way 0
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g5, [%g1 + (CH_TLO_TTE_DATA + (CH_TLO_TTE_SIZE * 2))]
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldxa [%g7]ASI_DTLB_TAGREAD, %g5
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g5, [%g1 + (CH_TLO_TTE_TAG + (CH_TLO_TTE_SIZE * 2))]
bb5e3b2f129cc39517b925419c22f69a378ec023eh set PN_TLB_ACC_WAY_BIT, %g6 ! same thing again for way 1
bb5e3b2f129cc39517b925419c22f69a378ec023eh or %g4, %g6, %g4 ! of each TLB.
bb5e3b2f129cc39517b925419c22f69a378ec023eh or %g7, %g6, %g7
bb5e3b2f129cc39517b925419c22f69a378ec023eh add %g1, CH_TLO_TTE_SIZE, %g1 ! move up the pointer
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldxa [%g4]ASI_DTLB_ACCESS, %g5 ! read the data from DTLB_0
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g5, [%g1 + CH_TLO_TTE_DATA] ! way 1 and store it away
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldxa [%g4]ASI_DTLB_TAGREAD, %g5 ! read the tag from DTLB_0
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g5, [%g1 + CH_TLO_TTE_TAG] ! way 1 and store it away
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldxa [%g7]ASI_DTLB_ACCESS, %g5 ! now repeat for DTLB_1 way 1
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g5, [%g1 + (CH_TLO_TTE_DATA + (CH_TLO_TTE_SIZE * 2))]
bb5e3b2f129cc39517b925419c22f69a378ec023eh ldxa [%g7]ASI_DTLB_TAGREAD, %g5
bb5e3b2f129cc39517b925419c22f69a378ec023eh stx %g5, [%g1 + (CH_TLO_TTE_TAG + (CH_TLO_TTE_SIZE * 2))]
bb5e3b2f129cc39517b925419c22f69a378ec023eh andn %g4, %g6, %g4 ! back to way 0
bb5e3b2f129cc39517b925419c22f69a378ec023eh andn %g7, %g6, %g7 ! back to way 0
bb5e3b2f129cc39517b925419c22f69a378ec023ehdtlb_parity_trap_2:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * at this point:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g2 - contains the VA whose lookup caused the trap
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g3 - contains the tlo_info field
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g4 - contains the T512_0 access index value for the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * VA/PgSz in question
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g7 - contains the T512_1 access index value for the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * VA/PgSz in question
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Here we will clear the errors from the DTLB.
bb5e3b2f129cc39517b925419c22f69a378ec023eh set MMU_TAG_ACCESS, %g5 ! We write a TTE tag value of
bb5e3b2f129cc39517b925419c22f69a378ec023eh stxa %g0, [%g5]ASI_DMMU ! 0 as it will be invalid.
bb5e3b2f129cc39517b925419c22f69a378ec023eh stxa %g0, [%g4]ASI_DTLB_ACCESS ! Write the data and tag.
bb5e3b2f129cc39517b925419c22f69a378ec023eh stxa %g0, [%g7]ASI_DTLB_ACCESS ! Now repeat for DTLB_1 way 0
bb5e3b2f129cc39517b925419c22f69a378ec023eh membar #Sync
bb5e3b2f129cc39517b925419c22f69a378ec023eh set PN_TLB_ACC_WAY_BIT, %g6 ! same thing again for way 1
bb5e3b2f129cc39517b925419c22f69a378ec023eh or %g4, %g6, %g4
bb5e3b2f129cc39517b925419c22f69a378ec023eh or %g7, %g6, %g7
bb5e3b2f129cc39517b925419c22f69a378ec023eh stxa %g0, [%g4]ASI_DTLB_ACCESS ! Write same data and tag.
bb5e3b2f129cc39517b925419c22f69a378ec023eh stxa %g0, [%g7]ASI_DTLB_ACCESS ! Now repeat for DTLB_1 way 0
bb5e3b2f129cc39517b925419c22f69a378ec023eh membar #Sync
bb5e3b2f129cc39517b925419c22f69a378ec023eh sethi %hi(FLUSH_ADDR), %g6 ! PRM says we need to issue a
bb5e3b2f129cc39517b925419c22f69a378ec023eh flush %g6 ! flush after writing MMU regs
bb5e3b2f129cc39517b925419c22f69a378ec023eh * at this point:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g2 - contains the VA whose lookup caused the trap
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %g3 - contains the tlo_info field
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Call cpu_tlb_parity_error via systrap at PIL 14 unless we're
bb5e3b2f129cc39517b925419c22f69a378ec023eh * already at PIL 15. We do this even for TL>1 traps since
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#if defined(lint)
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Calculates the Panther TLB index based on a virtual address and page size
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Register usage:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %o0 - virtual address whose index we want
bb5e3b2f129cc39517b925419c22f69a378ec023eh * %o1 - Page Size of the TLB in question as encoded in the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * ASI_[D|I]MMU_TAG_ACCESS_EXT register.
bb5e3b2f129cc39517b925419c22f69a378ec023eh#else /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#if defined(lint)
bb5e3b2f129cc39517b925419c22f69a378ec023eh * For Panther CPUs we need to flush the IPB after any I$ or D$
bb5e3b2f129cc39517b925419c22f69a378ec023eh * parity errors are detected.
bb5e3b2f129cc39517b925419c22f69a378ec023eh{ return; }
bb5e3b2f129cc39517b925419c22f69a378ec023eh#else /* lint */
bb5e3b2f129cc39517b925419c22f69a378ec023eh#endif /* lint */