us3_cheetah_asm.s revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*
* Assembly code support for the Cheetah module
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#if !defined(lint)
#include "assym.h"
#endif /* lint */
#include <sys/asm_linkage.h>
#include <vm/hat_sfmmu.h>
#include <sys/machparam.h>
#include <sys/machcpuvar.h>
#include <sys/machthread.h>
#include <sys/machtrap.h>
#include <sys/privregs.h>
#include <sys/asm_linkage.h>
#include <sys/cheetahregs.h>
#include <sys/us3_module.h>
#include <sys/cheetahasm.h>
#ifdef TRAPTRACE
#include <sys/traptrace.h>
#endif /* TRAPTRACE */
#if !defined(lint)
/* BEGIN CSTYLED */
/*
* Cheetah version to flush an Ecache line by index (aliased address)
*/
/* END CSTYLED */
#endif /* !lint */
/*
* Fast ECC error at TL>0 handler
* We get here via trap 70 at TL>0->Software trap 0 at TL>0. We enter
* this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
* For a complete description of the Fast ECC at TL>0 handling see the
*/
#if defined(lint)
void
fast_ecc_tl1_err(void)
{}
#else /* lint */
.section ".text"
.align 64
/*
* This macro turns off the D$/I$ if they are on and saves their
* original state in ch_err_tl1_tmp, saves all the %g registers in the
* ch_err_tl1_data structure, updates the ch_err_tl1_flags and saves
* the %tpc in ch_err_tl1_tpc. At the end of this macro, %g1 will
* point to the ch_err_tl1_data structure and the original D$/I$ state
* will be saved in ch_err_tl1_tmp. All %g registers except for %g1
* will be available.
*/
/*
* Get the diagnostic logout data. %g4 must be initialized to
* current CEEN state, %g5 must point to logout structure in
* ch_err_tl1_data_t. %g3 will contain the nesting count upon
* return.
*/
/*
* If the logout nesting count is exceeded, we're probably
* not making any progress, try to panic instead.
*/
/*
* Save the current CEEN and NCEEN state in %g7 and turn them off
* before flushing the Ecache.
*/
/*
* Flush the Ecache, using the largest possible cache size with the
* smallest possible line size since we can't get the actual sizes
* from the cpu_node due to DTLB misses.
*/
/*
* Use a different flush address to avoid recursion if the error
* exists in ecache_flushaddr.
*/
/*
* Restore CEEN and NCEEN to the previous state.
*/
/*
* If we turned off the D$, then flush it and turn it back on.
*/
/*
* Flush the D$.
*/
/*
* Turn the D$ back on.
*/
3:
/*
* If we turned off the I$, then flush it and turn it back on.
*/
/*
* Flush the I$.
*/
/*
* Turn the I$ back on. Changing DCU_IC requires flush.
*/
4:
#ifdef TRAPTRACE
/*
* Get current trap trace entry physical pointer.
*/
/*
* Create trap trace entry.
*/
/*
* Advance trap trace pointer.
*/
#endif /* TRAPTRACE */
/*
* handling and just do the necessary cache-flushing.
*/
/*
* If a UCU followed by a WDU has occurred go ahead and panic
* since a UE will occur (on the retry) before the UCU and WDU
* messages are enqueued.
*/
6:
/*
* We fall into this macro if we've successfully logged the error in
* the ch_err_tl1_data structure and want the PIL15 softint to pick
* it up and log it. %g1 must point to the ch_err_tl1_data structure.
* Restores the %g registers and issues retry.
*/
/*
* Establish panic exit label.
*/
#endif /* lint */
#if defined(lint)
/*
* scrubphys - Pass in the aligned physical memory address
* that you want to scrub, along with the ecache set size.
*
* 1) Displacement flush the E$ line corresponding to %addr.
* The first ldxa guarantees that the %addr is no longer in
* M, O, or E (goes to I or S (if instruction fetch also happens).
* 2) "Write" the data using a CAS %addr,%g0,%g0.
* The casxa guarantees a transition from I to M or S to M.
* 3) Displacement flush the E$ line corresponding to %addr.
* The second ldxa pushes the M line out of the ecache, into the
* writeback buffers, on the way to memory.
* 4) The "membar #Sync" pushes the cache line out of the writeback
* buffers onto the bus, on the way to dram finally.
*
* This is a modified version of the algorithm suggested by Gary Lauterbach.
* In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
* as modified, but then we found out that for spitfire, if it misses in the
* E$ it will probably install as an M, but if it hits in the E$, then it
* will stay E, if the store doesn't happen. So the first displacement flush
* should ensure that the CAS will miss in the E$. Arrgh.
*/
/* ARGSUSED */
void
{}
#else /* lint */
#endif /* lint */
#if defined(lint)
/*
* clearphys - Pass in the aligned physical memory address
* that you want to push out, as a ecache_linesize byte block of zeros,
* from the ecache zero-filled.
*/
/* ARGSUSED */
void
{
}
#else /* lint */
/* turn off IE, AM bits */
/* turn off NCEEN */
/* zero the E$ line */
1:
bge 1b
/* clear the AFSR */
/* turn NCEEN back on */
/* return and re-enable IE and AM */
#endif /* lint */
#if defined(lint)
/*
* Cheetah Ecache displacement flush the specified line from the E$
*
* Register usage:
* %o0 - 64 bit physical address for flushing
* %o1 - Ecache set size
*/
/*ARGSUSED*/
void
{
}
#else /* lint */
#endif /* lint */
#if defined(lint)
/*
* This routine will not be called in Cheetah systems.
*/
void
flush_ipb(void)
{ return; }
#else /* lint */
#endif /* lint */