us3_cheetah.c revision bb121940c2fe627557326e0143391ace6e6b7372
2N/A * The contents of this file are subject to the terms of the 2N/A * Common Development and Distribution License (the "License"). 2N/A * You may not use this file except in compliance with the License. 2N/A * See the License for the specific language governing permissions 2N/A * and limitations under the License. 2N/A * When distributing Covered Code, include this CDDL HEADER in each 2N/A * If applicable, add the following below this CDDL HEADER, with the 2N/A * fields enclosed by brackets "[]" replaced with your own identifying 2N/A * information: Portions Copyright [yyyy] [name of copyright owner] 2N/A * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2N/A * Use is subject to license terms. 2N/A#
pragma ident "%Z%%M% %I% %E% SMI" 2N/A#
endif /* CHEETAHPLUS_ERRATUM_25 */ 2N/A * Note that 'Cheetah PRM' refers to: 2N/A * SPARC V9 JPS1 Implementation Supplement: Sun UltraSPARC-III 2N/A * Setup trap handlers. 2N/A * Set the magic constants of the implementation. 2N/A * Cheetah's large page support has problems with large numbers of 2N/A * large pages, so just disable large pages out-of-the-box. 2N/A * Ship only to the first (IDSR_BN_SETS) CPUs. If we 2N/A * find we have shipped to more than (IDSR_BN_SETS) 2N/A * CPUs, set "index" to the highest numbered CPU in 2N/A * the set so we can ship to other CPUs a bit later on. 2N/A * If there is a big jump between the current tick 2N/A * count and lasttick, we have probably hit a break 2N/A * point. Adjust endtick accordingly to avoid panic. 2N/A * We claimed the whole memory or 2N/A * full scan is disabled. 2N/A#
endif /* CHEETAHPLUS_ERRATUM_25 */ 2N/A "[%d NACK %d BUSY]\nIDSR 0x%" 2N/A * Sequence through and ship to the 2N/A * remainder of the CPUs in the system 2N/A * (e.g. other than the first 2N/A * (IDSR_BN_SETS)) in reverse order. 2N/A * If we've processed all the CPUs, 2N/A * exit the loop now and save 2N/A * Clear recovered because we are sending to 2N/A * a new set of targets. 2N/A * Handles error logging for implementation specific error types. 2N/A /* There aren't any error types which are specific to cheetah only */ 2N/A * Figure out if Ecache is direct-mapped (Cheetah or Cheetah+ with Ecache 2N/A * control ECCR_ASSOC bit off or 2-way (Cheetah+ with ECCR_ASSOC on). 2N/A * We need to do this on the fly because we may have mixed Cheetah+'s with 2N/A * both direct and 2-way Ecaches. 2N/A * Note that these are entered into the table: Fatal Errors (PERR, IERR, 2N/A * ISAP, EMU) first, orphaned UCU/UCC, AFAR Overwrite policy, finally IVU, IVC. 2N/A * Afar overwrite policy is: 2N/A * UCU,UCC > UE,EDU,WDU,CPU > CE,EDC,EMC,WDC,CPC > TO,BERR 2N/A /* UE, EDU:ST, EDU:BLD, WDU, CPU */ 2N/A "Uncorrectable system bus (UE)",
2N/A /* CE, EDC, EMC, WDC, CPC */ 2N/A "Corrected system bus (CE)",
2N/A * Prioritized list of Error bits for AFAR overwrite. 2N/A * See Cheetah PRM P.6.1 2N/A * Class 3: UE, EDU, EMU, WDU, CPU 2N/A * Class 2: CE, EDC, EMC, WDC, CPC 2N/A * Prioritized list of Error bits for ESYND overwrite. 2N/A * See Cheetah PRM P.6.2 2N/A * Class 2: UE, IVU, EDU, WDU, UCU, CPU 2N/A * Class 1: CE, IVC, EDC, WDC, UCC, CPC 2N/A * Prioritized list of Error bits for MSYND overwrite. 2N/A * See Cheetah PRM P.6.3 2N/A * The Jalapeno memory controllers are required to drain outstanding 2N/A * memory transactions within 32 JBus clocks in order to be ready 2N/A * to enter Estar mode. In some corner cases however, that time 2N/A * A safe software solution is to force MCU to act like in Estar mode, 2N/A * then delay 1us (in ppm code) prior to assert J_CHNG_L signal. 2N/A * To reverse the effect, upon exiting Estar, software restores the 2N/A * MCU to its original state. 2N/A * We will reach here only if OBP and kernel don't agree on 2N/A * the speeds supported by the CPU. 2N/A * Cpu private initialization. This includes allocating the cpu_private 2N/A * data structure, initializing it, and initializing the scrubber for this 2N/A * cpu. This function calls cpu_init_ecache_scrub_dr to init the scrubber. 2N/A * We use kmem_cache_create for the cheetah private data structure because 2N/A * it needs to be allocated on a PAGESIZE (8192) byte boundary. 2N/A /* LINTED: E_TRUE_LOGICAL_EXPR */ 2N/A * Running with a Cheetah+, Jaguar, or Panther on a Cheetah CPU 2N/A * machine is not a supported configuration. Attempting to do so 2N/A * may result in unpredictable failures (e.g. running Cheetah+ 2N/A * CPUs with Cheetah E$ disp flush) so don't allow it. 2N/A * This is just defensive code since this configuration mismatch 2N/A * should have been caught prior to OS execution. 2N/A * If the ch_private_cache has not been created, create it. * Clear the error state registers for this CPU. * For Cheetah, just clear the AFSR * For Cheetah, the error recovery code uses an alternate flush area in the * TL>0 fast ECC handler. ecache_tl1_flushaddr is the physical address of * this exclusive displacement flush area. * Allocate and initialize the exclusive displacement flush area. * Called twice. The first time allocates virtual address. The second * call looks up the physical address. * Need to allocate an exclusive flush area that is twice the * largest supported E$ size, physically contiguous, and * aligned on twice the largest E$ size boundary. * Get the physical address of the exclusive flush area. * Update cpu_offline_set so the scrubber knows which cpus are offline