trapstat.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
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*
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*
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* If applicable, add the following below this CDDL HEADER, with the
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/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/cpu_module.h>
#include <vm/hat_sfmmu.h>
#include <vm/seg_kmem.h>
#include <sys/machsystm.h>
#include <sys/sysmacros.h>
#include <sys/archsystm.h>
#include <sys/trapstat.h>
#ifdef sun4v
#include <sys/hypervisor_api.h>
#endif
/* BEGIN CSTYLED */
/*
* trapstat: Trap Statistics through Dynamic Trap Table Interposition
* -------------------------------------------------------------------
*
* Motivation and Overview
*
* Despite being a fundamental indicator of system behavior, there has
* historically been very little insight provided into the frequency and cost
* of machine-specific traps. The lack of insight has been especially acute
* on UltraSPARC microprocessors: because these microprocessors handle TLB
* misses as software traps, the frequency and duration of traps play a
* decisive role in the performance of the memory system. As applications have
* increasingly outstripped TLB reach, this has become increasingly true.
*
* Part of the difficulty of observing trap behavior is that the trap handlers
* are so frequently called (e.g. millions of times per second) that any
* permanently enabled instrumentation would induce an unacceptable performance
* degradation. Thus, it is a constraint on any trap observability
* infrastructure that it have no probe effect when not explicitly enabled.
*
* The basic idea, then, is to create an interposing trap table in which each
* entry increments a per-trap, in-memory counter and then jumps to the actual,
* underlying trap table entry. To enable trapstat, we atomically write to the
* trap base address (%tba) register to point to our interposing trap table.
* (Note that per-CPU statistics fall out by creating a different trap table
* for each CPU.)
*
* Implementation Details
*
* While the idea is straight-forward, a nuance of SPARC V9 slightly
* complicates the implementation. Unlike its predecessors, SPARC V9 supports
* the notion of nested traps. The trap level is kept in the TL register:
* during normal operation it is 0; when a trap is taken, the TL register is
* incremented by 1. To aid system software, SPARC V9 breaks the trap table
* into two halves: the lower half contains the trap handlers for traps taken
* when TL is 0; the upper half contains the trap handlers for traps taken
* when TL is greater than 0. Each half is further subdivided into two
* subsequent halves: the lower half contains the trap handlers for traps
* other than those induced by the trap instruction (Tcc variants); the upper
* half contains the trap handlers for traps induced by the trap instruction.
* This gives a total of four ranges, with each range containing 256 traps:
*
* +--------------------------------+- 3ff
* | | .
* | Trap instruction, TL>0 | .
* | | .
* |- - - - - - - - - - - - - - - - +- 300
* |- - - - - - - - - - - - - - - - +- 2ff
* | | .
* | Non-trap instruction, TL>0 | .
* | | .
* |- - - - - - - - - - - - - - - - +- 200
* |- - - - - - - - - - - - - - - - +- 1ff
* | | .
* | Trap instruction, TL=0 | .
* | | .
* |- - - - - - - - - - - - - - - - +- 100
* |- - - - - - - - - - - - - - - - +- 0ff
* | | .
* | Non-trap instruction, TL=0 | .
* | | .
* +--------------------------------+- 000
*
*
* Solaris, however, doesn't have reason to support trap instructions when
* TL>0 (only privileged code may execute at TL>0; not supporting this only
* constrains our own implementation). The trap table actually looks like:
*
* +--------------------------------+- 2ff
* | | .
* | Non-trap instruction, TL>0 | .
* | | .
* |- - - - - - - - - - - - - - - - +- 200
* |- - - - - - - - - - - - - - - - +- 1ff
* | | .
* | Trap instruction, TL=0 | .
* | | .
* |- - - - - - - - - - - - - - - - +- 100
* |- - - - - - - - - - - - - - - - +- 0ff
* | | .
* | Non-trap instruction, TL=0 | .
* | | .
* +--------------------------------+- 000
*
* Putatively to aid system software, SPARC V9 has the notion of multiple
* sets of global registers. UltraSPARC defines four sets of global
* registers:
*
* Normal Globals
* Alternate Globals (AGs)
* MMU Globals (MGs)
* Interrupt Globals (IGs)
*
* The set of globals in use is controlled by bits in PSTATE; when TL is 0
* (and PSTATE has not been otherwise explicitly modified), the Normal Globals
* are in use. When a trap is issued, PSTATE is modified to point to a set of
* globals corresponding to the trap type. Most traps correspond to the
* Alternate Globals, with a minority corresponding to the MMU Globals, and
* only the interrupt-vector trap (vector 0x60) corresponding to the Interrupt
* Globals. (The complete mapping can be found in the UltraSPARC I&II User's
* Manual.)
*
* Note that the sets of globals are per trap _type_, not per trap _level_.
* Thus, when executing a TL>0 trap handler, one may not have registers
* available (for example, both trap-instruction traps and spill traps execute
* on the alternate globals; if a trap-instruction trap induces a window spill,
* the window spill handler has no available globals). For trapstat, this is
* problematic: a register is required to transfer control from one arbitrary
* location (in the interposing trap table) to another (in the actual trap
* table).
*
* We solve this problem by exploiting the trap table's location at the bottom
* of valid kernel memory (i.e. at KERNELBASE). We locate the interposing trap
* tables just below KERNELBASE -- thereby allowing us to use a branch-always
* instruction (ba) instead of a jump instruction (jmp) to transfer control
* from the TL>0 entries in the interposing trap table to the TL>0 entries in
* the actual trap table. (N.B. while this allows trap table interposition to
* work, it necessarily limits trapstat to only recording information about
* TL=0 traps -- there is no way to increment a counter without using a
* register.) Diagrammatically:
*
* Actual trap table:
*
* +--------------------------------+- 2ff
* | | .
* | Non-trap instruction, TL>0 | . <-----------------------+
* | | . <-----------------------|-+
* |- - - - - - - - - - - - - - - - +- 200 <-----------------------|-|-+
* |- - - - - - - - - - - - - - - - +- 1ff | | |
* | | . | | |
* | Trap instruction, TL=0 | . <-----------------+ | | |
* | | . <-----------------|-+ | | |
* |- - - - - - - - - - - - - - - - +- 100 <-----------------|-|-+ | | |
* |- - - - - - - - - - - - - - - - +- 0ff | | | | | |
* | | . | | | | | |
* | Non-trap instruction, TL=0 | . <-----------+ | | | | | |
* | | . <-----------|-+ | | | | | |
* +--------------------------------+- 000 <-----------|-|-+ | | | | | |
* KERNELBASE | | | | | | | | |
* | | | | | | | | |
* | | | | | | | | |
* Interposing trap table: | | | | | | | | |
* | | | | | | | | |
* +--------------------------------+- 2ff | | | | | | | | |
* | ... | . | | | | | | | | |
* | ... | . | | | | | | | | |
* | ... | . | | | | | | | | |
* |- - - - - - - - - - - - - - - - +- 203 | | | | | | | | |
* | ba,a | -------------|-|-|-|-|-|-+ | |
* |- - - - - - - - - - - - - - - - +- 202 | | | | | | | |
* | ba,a | -------------|-|-|-|-|-|---+ |
* |- - - - - - - - - - - - - - - - +- 201 | | | | | | |
* | ba,a | -------------|-|-|-|-|-|-----+
* |- - - - - - - - - - - - - - - - +- 200 | | | | | |
* | ... | . | | | | | |
* | ... | . | | | | | |
* | ... | . | | | | | |
* |- - - - - - - - - - - - - - - - +- 103 | | | | | |
* | (Increment counter) | | | | | | |
* | ba,a | -------------------+ | |
* |- - - - - - - - - - - - - - - - +- 102 | | | | |
* | (Increment counter) | | | | | |
* | ba,a | ---------------------+ |
* |- - - - - - - - - - - - - - - - +- 101 | | | |
* | (Increment counter) | | | | |
* | ba,a | -----------------------+
* |- - - - - - - - - - - - - - - - +- 100 | | |
* | ... | . | | |
* | ... | . | | |
* | ... | . | | |
* |- - - - - - - - - - - - - - - - +- 003 | | |
* | (Increment counter) | | | |
* | ba,a | -------------+ | |
* |- - - - - - - - - - - - - - - - +- 002 | |
* | (Increment counter) | | |
* | ba,a | ---------------+ |
* |- - - - - - - - - - - - - - - - +- 001 |
* | (Increment counter) | |
* | ba,a | -----------------+
* +--------------------------------+- 000
* KERNELBASE - tstat_total_size
*
* tstat_total_size is the number of pages required for each trap table. It
* must be true that KERNELBASE - tstat_total_size is less than the maximum
* branch displacement; if each CPU were to consume a disjoint virtual range
* below KERNELBASE for its trap table, we could support at most
* (maximum_branch_displacement / tstat_total_size) CPUs. The maximum branch
* displacement for Bicc variants is just under eight megabytes, and (because
* the %tba must be 32K aligned), tstat_total_size must be at least 32K; if
* each CPU were to consume a disjoint virtual range, we would have an
* unacceptably low upper bound of 256 CPUs.
*
* While there are tricks that one could use to address this constraint (e.g.,
* creating trampolines every maximum_branch_displacement bytes), we instead
* solve this by not permitting each CPU to consume a disjoint virtual range.
* Rather, we have each CPU's interposing trap table use the _same_ virtual
* range, but we back the trap tables with disjoint physical memory. Normally,
* such one-to-many virtual-to-physical mappings are illegal; this is
* permissible here only because the pages for the interposing trap table are
* necessarily locked in the TLB. (The CPUs thus never have the opportunity to
* discover that they have conflicting translations.)
*
* On CMT architectures in which CPUs can share MMUs, the above trick will not
* work: two CPUs that share an MMU cannot have the same virtual address map
* to disjoint physical pages. On these architectures, any CPUs sharing the
* same MMU must consume a disjoint 32K virtual address range -- limiting the
* number of CPUs sharing an MMU on these architectures to 256 due to the
* branch displacement limitation described above. On the sun4v architecture,
* there is a further limitation: a guest may not have more than eight locked
* TLB entries per MMU. To allow operation under this restriction, the
* interposing trap table and the trap statistics are each accessed through
* a single 4M TLB entry. This limits the footprint to two locked entries
* (one for the I-TLB and one for the D-TLB), but further restricts the number
* of CPUs to 128 per MMU. However, support for more than 128 CPUs can easily
* be added via a hybrid scheme, where the same 4M virtual address is used
* on different MMUs.
*
*
* TLB Statistics
*
* Because TLB misses are an important component of system performance, we wish
* to know much more about these traps than simply the number received.
* Specifically, we wish to know:
*
* (a) The amount of time spent executing the TLB miss handler
* (b) TLB misses versus TSB misses
* (c) Kernel-level misses versus user-level misses
* (d) Misses per pagesize
*
* TLB Statistics: Time Spent Executing
*
* To accurately determine the amount of time spent executing the TLB miss
* handler, one must get a timestamp on trap entry and trap exit, subtract the
* latter from the former, and add the result to an accumulating count.
* Consider flow of control during normal TLB miss processing (where "ldx
* [%g2], %g2" is an arbitrary TLB-missing instruction):
*
* + - - - - - - - -+
* : :
* : ldx [%g2], %g2 :<-------------------------------------------------------+
* : : Return from trap: |
* + - - - - - - - -+ TL <- TL - 1 (0) |
* | %pc <- TSTATE[TL].TPC (address of load) |
* | TLB miss: |
* | TL <- TL + 1 (1) |
* | %pc <- TLB-miss-trap-handler |
* | |
* v |
* + - - - - - - - - - - - - - - - + |
* : : |
* : Lookup VA in TSB : |
* : If (hit) : |
* : Fill TLB : |
* : Else : |
* : Lookup VA (hme hash table : |
* : or segkpm) : |
* : Fill TLB : |
* : Endif : |
* : Issue "retry" ---------------------------------------------------------+
* : :
* + - - - - - - - - - - - - - - - +
* TLB-miss-trap-handler
*
*
* As the above diagram indicates, interposing on the trap table allows one
* only to determine a timestamp on trap _entry_: when the TLB miss handler
* has completed filling the TLB, a "retry" will be issued, and control will
* transfer immediately back to the missing %pc.
*
* To obtain a timestamp on trap exit, we must then somehow interpose between
* the "retry" and the subsequent control transfer to the TLB-missing
* instruction. To do this, we _push_ a trap level. The basic idea is to
* spoof a TLB miss by raising TL, setting the %tpc to be within text
* controlled by trapstat (the "TLB return entry") and branching to the
* underlying TLB miss handler. When the TLB miss handler issues its "retry",
* control will transfer not to the TLB-missing instruction, but rather to the
* TLB return entry. This code can then obtain a timestamp, and issue its own
* "retry" -- thereby correctly returning to the TLB-missing instruction.
* Here is the above TLB miss flow control diagram modified to reflect
* trapstat's operation:
*
* + - - - - - - - -+
* : :
* : ldx [%g2], %g2 :<-------------------------------------------------------+
* : : Return from trap: |
* + - - - - - - - -+ TL <- TL - 1 (0) |
* | %pc <- TSTATE[TL].TPC (address of load) |
* | TLB miss: |
* | TL <- TL + 1 (1) |
* | %pc <- TLB-miss-trap-handler (trapstat) |
* | |
* v TLB-return-entry (trapstat) |
* + - - - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - + |
* : : : : |
* : Record timestamp : : Record timestamp : |
* : TL <- 2 : : Take timestamp difference : |
* : TSTATE[1].TPC <- TLB-return-entry : : Add to running total : |
* : ba,a TLB-miss-trap-handler -----------+ : Issue "retry" --------------+
* : : | : :
* + - - - - - - - - - - - - - - - - - - + | + - - - - - - - - - - - - - +
* TLB-miss-trap-handler | ^
* (trapstat) | |
* | |
* | |
* +-----------------------+ |
* | |
* | |
* v |
* + - - - - - - - - - - - - - - - + |
* : : |
* : Lookup VA in TSB : |
* : If (hit) : |
* : Fill TLB : |
* : Else : |
* : Lookup VA (hme hash table : |
* : or segkpm) : |
* : Fill TLB : |
* : Endif : |
* : Issue "retry" ------------------------------------------+
* : : Return from trap:
* + - - - - - - - - - - - - - - - + TL <- TL - 1 (1)
* TLB-miss-trap-handler %pc <- TSTATE[TL].TPC (TLB-return-entry)
*
*
* A final subterfuge is required to complete our artifice: if we miss in
* the TLB, the TSB _and_ the subsequent hash or segkpm lookup (that is, if
* there is no valid translation for the TLB-missing address), common system
* software will need to accurately determine the %tpc as part of its page
* fault handling. We therefore modify the kernel to check the %tpc in this
* case: if the %tpc falls within the VA range controlled by trapstat and
* the TL is 2, TL is simply lowered back to 1 (this check is implemented
* by the TSTAT_CHECK_TL1 macro). Lowering TL to 1 has the effect of
* discarding the state pushed by trapstat.
*
* TLB Statistics: TLB Misses versus TSB Misses
*
* Distinguishing TLB misses from TSB misses requires further interposition
* on the TLB miss handler: we cannot know a priori or a posteriori if a
* given VA will or has hit in the TSB.
*
* We achieve this distinction by adding a second TLB return entry almost
* identical to the first -- differing only in the address to which it
* stores its results. We then modify the TLB miss handlers of the kernel
* such that they check the %tpc when they determine that a TLB miss has
* subsequently missed in the TSB: if the %tpc lies within trapstat's VA
* range and TL is 2 (that is, if trapstat is running), the TLB miss handler
* _increments_ the %tpc by the size of the TLB return entry. The ensuing
* "retry" will thus transfer control to the second TLB return entry, and
* the time spent in the handler will be accumulated in a memory location
* specific to TSB misses.
*
* N.B.: To minimize the amount of knowledge the kernel must have of trapstat,
* we do not allow the kernel to hard-code the size of the TLB return entry.
* Rather, the actual tsbmiss handler executes a known instruction at the
* corresponding tsbmiss patch points (see the tstat_tsbmiss_patch_table) with
* the %tpc in %g7: when trapstat is not running, these points contain the
* harmless TSTAT_TSBMISS_INSTR instruction ("add %g7, 0, %g7"). Before
* running, trapstat modifies the instructions at these patch points such
* that the simm13 equals the size of the TLB return entry.
*
* TLB Statistics: Kernel-level Misses versus User-level Misses
*
* Differentiating user-level misses from kernel-level misses employs a
* similar technique, but is simplified by the ability to distinguish a
* user-level miss from a kernel-level miss a priori by reading the context
* register: we implement kernel-/user-level differentiation by again doubling
* the number of TLB return entries, and setting the %tpc to the appropriate
* TLB return entry in trapstat's TLB miss handler. Together with the doubling
* total of four TLB return entries:
*
* Level TSB hit? Structure member
* ------------------------------------------------------------
* Kernel Yes tstat_tlbret_t.ttlbr_ktlb
* Kernel No tstat_tlbret_t.ttlbr_ktsb
* User Yes tstat_tlbret_t.ttlbr_utlb
* User No tstat_tlbret_t.ttlbr_utsb
*
* TLB Statistics: Misses per Pagesize
*
* pagesize a priori. This is therefore implemented by mandating a new rule:
* whenever the kernel fills the TLB in its TLB miss handler, the TTE
* corresponding to the TLB-missing VA must be in %g5 when the handler
* executes its "retry". This allows the TLB return entry to determine
* pagesize by simply looking at the pagesize field in the TTE stored in
* %g5.
*
* TLB Statistics: Probe Effect
*
* As one might imagine, gathering TLB statistics by pushing a trap level
* induces significant probe effect. To account for this probe effect,
* trapstat attempts to observe it by executing a code sequence with a known
* number of TLB misses both before and after interposing on the trap table.
* This allows trapstat to determine a per-trap probe effect which can then be
* factored into the "%tim" fields of the trapstat command.
*
* Note that on sun4v platforms, TLB misses are normally handled by the
* hypervisor or the hardware TSB walker. Thus no fast MMU miss information
* is reported for normal operation. However, when trapstat is invoked with
* -t or -T option to collect detailed TLB statistics, kernel takes
* over TLB miss handling. This results in significantly more overhead
* and TLB statistics may not be as accurate as on sun4u platforms.
*
* Locking
*
* The implementation uses two locks: tstat_lock (a local lock) and the global
* cpu_lock. tstat_lock is used to assure trapstat's consistency in the
* necessary to correctly support multithreaded access). cpu_lock is held
* whenever CPUs are being manipulated directly, to prevent them from
* disappearing in the process. Because trapstat's DR callback
* (trapstat_cpu_setup()) must grab tstat_lock and is called with cpu_lock
* held, the lock ordering is necessarily cpu_lock before tstat_lock.
*
*/
/* END CSTYLED */
static int tstat_open; /* set if driver is open */
static int tstat_running; /* set if trapstat is running */
static int tstat_options; /* bit-wise indication of options */
static int *tstat_enabled; /* map of enabled trap entries */
static int tstat_tsbmiss_patched; /* tsbmiss patch flag */
static char *tstat_probe_area; /* VA range used for probe effect */
/*
* sizeof tstat_data_t + pgsz data for the kernel. For simplicity's sake, when
* we collect data, we do it based upon szc, but when we report data back to
* userland, we have to do it based upon the userszc which may not match.
* So, these two variables are for internal use and exported use respectively.
*/
static size_t tstat_data_t_size;
static size_t tstat_data_t_exported_size;
#ifdef sun4v
#endif
/*
* In the above block comment, see "TLB Statistics: TLB Misses versus
* TSB Misses" for an explanation of the tsbmiss patch points.
*/
extern uint32_t tsbmiss_trapstat_patch_point;
/*
* Trapstat tsbmiss patch table
*/
{(uint32_t *)&tsbmiss_trapstat_patch_point, 0},
{(uint32_t *)&tsbmiss_trapstat_patch_point_kpm, 0},
};
/*
* We define some general SPARC-specific constants to allow more readable
* relocations.
*/
#define NOP 0x01000000
/*
* The interposing trap table must be locked in the I-TLB, and any data
* referred to in the interposing trap handler must be locked in the D-TLB.
* This function locks these pages in the appropriate TLBs by creating TTEs
* from whole cloth, and manually loading them into the TLB. This function is
* called from cross call context.
*
* On sun4v platforms, we use 4M page size mappings to minimize the number
* of locked down entries (i.e. permanent mappings). Each CPU uses a
* reserved portion of that 4M page for its TBA and data.
*/
static void
trapstat_load_tlb(void)
{
#ifndef sun4v
int i;
#else
#endif
#ifndef sun4v
if (i < TSTAT_INSTR_PAGES) {
} else {
}
}
#else /* sun4v */
#endif /* sun4v */
}
/*
* As mentioned in the "TLB Statistics: TLB Misses versus TSB Misses" section
* of the block comment, TLB misses are differentiated from TSB misses in
* part by hot-patching the instructions at the tsbmiss patch points (see
* tstat_tsbmiss_patch_table). This routine is used both to initially patch
* the instructions, and to patch them back to their original values upon
* restoring the original trap table.
*/
static void
{
if (!(tstat_options & TSTAT_OPT_TLBDATA))
return;
if (!tstat_tsbmiss_patched) {
/*
* We haven't patched the TSB paths; do so now.
*/
/*CONSTCOND*/
/*
* Assert that the instruction we're about to patch is
* "add %g7, 0, %g7" (0x8e01e000).
*/
}
} else {
/*
* Remove patches from the TSB paths.
*/
}
}
}
/*
* This is the routine executed to clock the performance of the trap table,
* executed both before and after interposing on the trap table to attempt to
* determine probe effect. The probe effect is used to adjust the "%tim"
* fields of trapstat's -t and -T output; we only use TLB misses to clock the
* trap table. We execute the inner loop (which is designed to exceed the
* TLB's reach) nlaps times, taking the best time as our time (thereby
* factoring out the effects of interrupts, cache misses or other perturbing
* events.
*/
static hrtime_t
{
int i, j = 0;
while (nlaps--) {
for (i = 0; i < TSTAT_PROBE_SIZE; i += MMU_PAGESIZE)
*((volatile char *)&tstat_probe_area[i]);
}
return (best);
}
/*
* This routine determines the probe effect by calling trapstat_probe_laps()
* both without and with the interposing trap table. Note that this is
* called from a cross call on the desired CPU, and that it is called on
* every CPU (this is necessary because the probe effect may differ from
* one CPU to another).
*/
static void
{
return;
return;
/*
* We very much expect the %tba to be KERNELBASE; this is a
* precautionary measure to assure that trapstat doesn't melt the
* machine should the %tba point unexpectedly elsewhere.
*/
return;
/*
* Preserve this CPU's data before destroying it by enabling the
* interposing trap table. We can safely use tstat_buffer because
* the caller of the trapstat_probe() cross call is holding tstat_lock.
*/
}
static void
{
int i;
if (!(tstat_options & TSTAT_OPT_TLBDATA))
return;
/*
* Grab some virtual from the heap arena.
*/
/*
* Grab a single physical page.
*/
/*
* Now set the translation for every page in our virtual range
* to be our allocated physical page.
*/
for (i = 0; i < TSTAT_PROBE_NPAGES; i++) {
va += MMU_PAGESIZE;
}
}
static void
{
int i;
return;
for (i = 0; i < TSTAT_PROBE_NPAGES; i++) {
va += MMU_PAGESIZE;
}
}
/*
* This routine actually enables a CPU by setting its %tba to be the
* CPU's interposing trap table. It is called out of cross call context.
*/
static void
{
return;
return;
if (!(tstat_options & TSTAT_OPT_NOGO))
#ifdef sun4v
/*
* On sun4v platforms, TLB misses are normally handled by the
* hypervisor or the hardware -- provided one or more TSBs
* have been setup and communicated via hv_set_ctx0 and
* hv_set_nonctx0 API. However, as part of collecting TLB
* statistics, we disabled this miss processing by telling the
* hypervisor that there was not a TSB; we now need to
* resume efficient operation.
*
* While we restore kernel TSB information immediately, to
* avoid any locking dependency, we don't restore user TSB
* information right away. Rather, we simply clear the
* TSTAT_TLB_STATS flag so that the user TSB information is
* automatically restored on the next context switch.
*
* Note that the call to restore kernel TSB information is not
* expected to fail. Even in the event of failure, the system
* will still continue to function properly, if in a state of
* reduced performance due to the guest kernel handling all
* TLB misses.
*/
}
#endif
}
/*
* This routine disables a CPU (vis a vis trapstat) by setting its %tba to be
* the actual, underlying trap table. It is called out of cross call context.
*/
static void
{
return;
if (!(tstat_options & TSTAT_OPT_NOGO))
#ifdef sun4v
/*
* On sun4v platforms, TlB misses are normally handled by
* the hypervisor or the hardware provided one or more TSBs
* have been setup and communicated via hv_set_ctx0 and
* hv_set_nonctx0 API. However, as part of collecting TLB
* statistics, we disabled that by faking NO TSB and we
* so that TLB misses can be handled by the hypervisor or
* the hardware more efficiently.
*
* We restore kernel TSB information right away. However,
* to minimize any locking dependency, we don't restore
* user TSB information right away. Instead, we simply
* clear the TSTAT_TLB_STATS flag so that the user TSB
* information is automatically restored on next context
* switch.
*
* Note that the call to restore kernel TSB information
* will normally not fail, unless wrong information is
* passed here. In that scenario, system will still
* continue to function properly with the exception of
* kernel handling all the TLB misses.
*/
}
#endif
}
/*
* We use %tick as the time base when recording the time spent executing
* the trap handler. %tick, however, is not necessarily kept in sync
* across CPUs (indeed, different CPUs may have different %tick frequencies).
* We therefore cross call onto a CPU to get a snapshot of its data to
* copy out; this is the routine executed out of that cross call.
*/
static void
{
}
/*
* The TSTAT_RETENT_* constants define offsets in the TLB return entry.
* They are used only in trapstat_tlbretent() (below) and #undef'd
* immediately afterwards. Any change to "retent" in trapstat_tlbretent()
* will likely require changes to these constants.
*/
#ifndef sun4v
#define TSTAT_RETENT_STATHI 1
#define TSTAT_RETENT_STATLO 2
#define TSTAT_RETENT_SHIFT 8
#define TSTAT_RETENT_COUNT_LD 10
#define TSTAT_RETENT_COUNT_ST 12
#define TSTAT_RETENT_TMPTSHI 13
#define TSTAT_RETENT_TMPTSLO 14
#define TSTAT_RETENT_TIME_LD 16
#define TSTAT_RETENT_TIME_ST 18
#else /* sun4v */
#define TSTAT_RETENT_STATHI 1
#define TSTAT_RETENT_STATLO 2
#define TSTAT_RETENT_SHIFT 5
#define TSTAT_RETENT_COUNT_LD 7
#define TSTAT_RETENT_COUNT_ST 9
#define TSTAT_RETENT_TMPTSHI 10
#define TSTAT_RETENT_TMPTSLO 11
#define TSTAT_RETENT_TIME_LD 13
#define TSTAT_RETENT_TIME_ST 15
#endif /* sun4v */
static void
{
/*
* handler (i.e. the code interpositioned between the "retry" and
* the actual return to the TLB-missing instruction). Detail on its
* theory of operation can be found in the "TLB Statistics" section
* of the block comment. Note that we expect the TTE just loaded
* into the TLB to be in %g5; all other globals are available as
* scratch. Finally, note that the page size information in sun4v is
* located in the lower bits of the TTE -- requiring us to have a
* different return entry on sun4v.
*/
#ifndef sun4v
0x87410000, /* rd %tick, %g3 */
0x03000000, /* sethi %hi(stat), %g1 */
0x82106000, /* or %g1, %lo(stat), %g1 */
0x89297001, /* sllx %g5, 1, %g4 */
0x8931303e, /* srlx %g4, 62, %g4 */
0x8531702e, /* srlx %g5, 46, %g2 */
0x8408a004, /* and %g2, 4, %g2 */
0x88110002, /* or %g4, %g2, %g4 */
0x89292000, /* sll %g4, shift, %g4 */
0x82004004, /* add %g1, %g4, %g1 */
0xc4586000, /* ldx [%g1 + tmiss_count], %g2 */
0x8400a001, /* add %g2, 1, %g2 */
0xc4706000, /* stx %g2, [%g1 + tmiss_count] */
0x0d000000, /* sethi %hi(tdata_tmptick), %g6 */
0xc459a000, /* ldx [%g6 + %lo(tdata_tmptick)], %g2 */
0x8620c002, /* sub %g3, %g2, %g3 */
0xc4586000, /* ldx [%g1 + tmiss_time], %g2 */
0x84008003, /* add %g2, %g3, %g2 */
0xc4706000, /* stx %g2, [%g1 + tmiss_time] */
0x83f00000 /* retry */
#else /* sun4v */
0x87410000, /* rd %tick, %g3 */
0x03000000, /* sethi %hi(stat), %g1 */
0x82106000, /* or %g1, %lo(stat), %g1 */
0x8929703d, /* sllx %g5, 61, %g4 */
0x8931303d, /* srlx %g4, 61, %g4 */
0x89292000, /* sll %g4, shift, %g4 */
0x82004004, /* add %g1, %g4, %g1 */
0xc4586000, /* ldx [%g1 + tmiss_count], %g2 */
0x8400a001, /* add %g2, 1, %g2 */
0xc4706000, /* stx %g2, [%g1 + tmiss_count] */
0x0d000000, /* sethi %hi(tdata_tmptick), %g6 */
0xc459a000, /* ldx [%g6 + %lo(tdata_tmptick)], %g2 */
0x8620c002, /* sub %g3, %g2, %g3 */
0xc4586000, /* ldx [%g1 + tmiss_time], %g2 */
0x84008003, /* add %g2, %g3, %g2 */
0xc4706000, /* stx %g2, [%g1 + tmiss_time] */
0x83f00000 /* retry */
#endif /* sun4v */
};
/*CONSTCOND*/
/*CONSTCOND*/
/*CONSTCOND*/
continue;
/* LINTED E_EXPR_NULL_EFFECT */
/* LINTED E_EXPR_NULL_EFFECT */
}
/*
* The TSTAT_TLBENT_* constants define offsets in the TLB entry. They are
* used only in trapstat_tlbent() (below) and #undef'd immediately afterwards.
* Any change to "tlbent" in trapstat_tlbent() will likely require changes
* to these constants.
*/
#ifndef sun4v
#define TSTAT_TLBENT_STATHI 0
#define TSTAT_TLBENT_STATLO_LD 1
#define TSTAT_TLBENT_STATLO_ST 3
#define TSTAT_TLBENT_MMUASI 15
#define TSTAT_TLBENT_TPCHI 18
#define TSTAT_TLBENT_TPCLO_USER 19
#define TSTAT_TLBENT_TPCLO_KERN 21
#define TSTAT_TLBENT_TSHI 25
#define TSTAT_TLBENT_TSLO 27
#define TSTAT_TLBENT_BA 28
#else /* sun4v */
#define TSTAT_TLBENT_STATHI 0
#define TSTAT_TLBENT_STATLO_LD 1
#define TSTAT_TLBENT_STATLO_ST 3
#define TSTAT_TLBENT_TAGTARGET 19
#define TSTAT_TLBENT_TPCHI 21
#define TSTAT_TLBENT_TPCLO_USER 22
#define TSTAT_TLBENT_TPCLO_KERN 24
#define TSTAT_TLBENT_TSHI 28
#define TSTAT_TLBENT_TSLO 30
#define TSTAT_TLBENT_BA 31
#endif /* sun4v */
static void
{
#ifndef sun4v
#else
#endif
/*
* When trapstat is run with TLB statistics, this is the entry for
* both I- and D-TLB misses; this code performs trap level pushing,
* as described in the "TLB Statistics" section of the block comment.
* This code is executing at TL 1; %tstate[0] contains the saved
* state at the time of the TLB miss. Pushing trap level 1 (and thus
* raising TL to 2) requires us to fill in %tstate[1] with our %pstate,
* %cwp and %asi. We leave %tt unchanged, and we set %tpc and %tnpc to
* the appropriate TLB return entry (based on the context of the miss).
* Finally, we sample %tick, and stash it in the tdata_tmptick member
* the per-CPU tstat_data structure. tdata_tmptick will be used in
* the TLB return entry to determine the amount of time spent in the
* TLB miss handler.
*
* Note that on sun4v platforms, we must also force the %gl value to 1
* in %tstate and we must obtain the context information from the MMU
* fault status area. (The base address of this MMU fault status area
* is kept in the scratchpad register 0.)
*/
#ifndef sun4v
0x03000000, /* sethi %hi(stat), %g1 */
0xc4586000, /* ldx [%g1 + %lo(stat)], %g2 */
0x8400a001, /* add %g2, 1, %g2 */
0xc4706000, /* stx %g2, [%g1 + %lo(stat)] */
0x85524000, /* rdpr %cwp, %g2 */
0x87518000, /* rdpr %pstate, %g3 */
0x8728f008, /* sllx %g3, 8, %g3 */
0x84108003, /* or %g2, %g3, %g2 */
0x8740c000, /* rd %asi, %g3 */
0x8728f018, /* sllx %g3, 24, %g3 */
0x84108003, /* or %g2, %g3, %g2 */
0x8350c000, /* rdpr %tt, %g1 */
0x8f902002, /* wrpr %g0, 2, %tl */
0x85908000, /* wrpr %g2, %g0, %tstate */
0x87904000, /* wrpr %g1, %g0, %tt */
0xc2d80000, /* ldxa [%g0]ASI_MMU, %g1 */
0x83307030, /* srlx %g1, CTXSHIFT, %g1 */
0x02c04004, /* brz,pn %g1, .+0x10 */
0x03000000, /* sethi %hi(new_tpc), %g1 */
0x82106000, /* or %g1, %lo(new_tpc), %g1 */
0x30800002, /* ba,a .+0x8 */
0x82106000, /* or %g1, %lo(new_tpc), %g1 */
0x81904000, /* wrpr %g1, %g0, %tpc */
0x82006004, /* add %g1, 4, %g1 */
0x83904000, /* wrpr %g1, %g0, %tnpc */
0x03000000, /* sethi %hi(tmptick), %g1 */
0x85410000, /* rd %tick, %g2 */
0xc4706000, /* stx %g2, [%g1 + %lo(tmptick)] */
0x30800000, /* ba,a addr */
#else /* sun4v */
0x03000000, /* sethi %hi(stat), %g1 */
0xc4586000, /* ldx [%g1 + %lo(stat)], %g2 */
0x8400a001, /* add %g2, 1, %g2 */
0xc4706000, /* stx %g2, [%g1 + %lo(stat)] */
0x85524000, /* rdpr %cwp, %g2 */
0x87518000, /* rdpr %pstate, %g3 */
0x8728f008, /* sllx %g3, 8, %g3 */
0x84108003, /* or %g2, %g3, %g2 */
0x8740c000, /* rd %asi, %g3 */
0x03000040, /* sethi %hi(0x10000), %g1 */
0x86104003, /* or %g1, %g3, %g3 */
0x8728f018, /* sllx %g3, 24, %g3 */
0x84108003, /* or %g2, %g3, %g2 */
0x8350c000, /* rdpr %tt, %g1 */
0x8f902002, /* wrpr %g0, 2, %tl */
0x85908000, /* wrpr %g2, %g0, %tstate */
0x87904000, /* wrpr %g1, %g0, %tt */
0xa1902001, /* wrpr %g0, 1, %gl */
0xc2d80400, /* ldxa [%g0]ASI_SCRATCHPAD, %g1 */
0xc2586000, /* ldx [%g1 + MMFSA_?_CTX], %g1 */
0x02c04004, /* brz,pn %g1, .+0x10 */
0x03000000, /* sethi %hi(new_tpc), %g1 */
0x82106000, /* or %g1, %lo(new_tpc), %g1 */
0x30800002, /* ba,a .+0x8 */
0x82106000, /* or %g1, %lo(new_tpc), %g1 */
0x81904000, /* wrpr %g1, %g0, %tpc */
0x82006004, /* add %g1, 4, %g1 */
0x83904000, /* wrpr %g1, %g0, %tnpc */
0x03000000, /* sethi %hi(tmptick), %g1 */
0x85410000, /* rd %tick, %g2 */
0xc4706000, /* stx %g2, [%g1 + %lo(tmptick)] */
0x30800000 /* ba,a addr */
#endif /* sun4v */
};
if (itlb) {
} else {
}
#ifndef sun4v
#else
#endif
/*
* And now set up the TLB return entries.
*/
}
#ifndef sun4v
#else
#endif
/*
* The TSTAT_ENABLED_* constants define offsets in the enabled entry; the
* TSTAT_DISABLED_BA constant defines an offset in the disabled entry. Both
* sets of constants are used only in trapstat_make_traptab() (below) and
* #undef'd immediately afterwards. Any change to "enabled" or "disabled"
* in trapstat_make_traptab() will likely require changes to these constants.
*/
#define TSTAT_ENABLED_STATHI 0
#define TSTAT_ENABLED_STATLO_LD 1
#define TSTAT_ENABLED_STATLO_ST 3
#define TSTAT_ENABLED_BA 4
#define TSTAT_DISABLED_BA 0
static void
{
int nent;
/*
* This is the entry in the interposing trap table for enabled trap
* table entries. It loads a counter, increments it and stores it
* back before branching to the actual trap table entry.
*/
0x03000000, /* sethi %hi(stat), %g1 */
0xc4586000, /* ldx [%g1 + %lo(stat)], %g2 */
0x8400a001, /* add %g2, 1, %g2 */
0xc4706000, /* stx %g2, [%g1 + %lo(stat)] */
0x30800000, /* ba,a addr */
};
/*
* This is the entry in the interposing trap table for disabled trap
* table entries. It simply branches to the actual, underlying trap
* table entry. As explained in the "Implementation Details" section
* of the block comment, all TL>0 traps _must_ use the disabled entry;
* additional entries may be explicitly disabled through the use
*/
0x30800000, /* ba,a addr */
};
orig = KERNELBASE;
if (tstat_enabled[nent]) {
} else {
}
stat++;
}
}
static void
{
#ifndef sun4v
int i;
#endif
/*
* The lower fifteen bits of the %tba are always read as zero; we must
* align our instruction base address appropriately.
*/
#ifndef sun4v
& TSTAT_TBA_MASK);
/*
* We must be sure that the pages that we will use to examine the data
* have the same virtual color as the pages to which the data is being
* recorded, hence the alignment and phase constraints on the
* allocation.
*/
#else /* sun4v */
(1 + ~TSTAT_TBA_MASK)));
#endif /* sun4v */
/*
* Now that we have all of the instruction and data pages allocated,
* make the trap table from scratch.
*/
if (tstat_options & TSTAT_OPT_TLBDATA) {
/*
* TLB Statistics have been specified; set up the I- and D-TLB
* entries and corresponding TLB return entries.
*/
}
/*
* Finally, get the target CPU to load the locked pages into its TLBs.
*/
}
static void
{
#ifndef sun4v
int i;
#endif
#ifndef sun4v
}
#else
#endif
}
static int
{
if (tstat_running) {
return (EBUSY);
}
#ifdef sun4v
/*
* Allocate large page to hold interposing tables
*/
if (tstat_pfn == PFN_INVALID) {
return (EAGAIN);
}
#endif
/*
* First, perform any necessary hot patching.
*/
/*
* Allocate the resources we'll need to measure probe effect.
*/
do {
continue;
/*
* Note that due to trapstat_probe()'s use of global data,
* we determine the probe effect on each CPU serially instead
* of in parallel with an xc_all().
*/
tstat_running = 1;
return (0);
}
static int
{
int i;
if (!tstat_running) {
return (ENXIO);
}
for (i = 0; i <= max_cpuid; i++) {
}
#ifdef sun4v
#endif
tstat_running = 0;
return (0);
}
/*
* This is trapstat's DR CPU configuration callback. It's called (with
* cpu_lock held) to unconfigure a newly powered-off CPU, or to configure a
* powered-off CPU that is to be brought into the system. We need only take
* action in the unconfigure case: because a powered-off CPU will have its
* trap table restored to KERNELBASE if it is ever powered back on, we must
* update the flags to reflect that trapstat is no longer enabled on the
* powered-off CPU. Note that this means that a TSTAT_CPU_ENABLED CPU that
* is unconfigured/powered off and later powered back on/reconfigured will
* _not_ be re-TSTAT_CPU_ENABLED.
*/
static int
{
if (!tstat_running) {
return (0);
}
switch (what) {
case CPU_CONFIG:
break;
case CPU_UNCONFIG:
break;
default:
break;
}
return (0);
}
/*
* This is called before a CPR suspend and after a CPR resume. We don't have
* anything to do before a suspend, but after a restart we must restore the
* trap table to be our interposing trap table. However, we don't actually
* know whether or not the CPUs have been powered off -- this routine may be
* called while restoring from a failed CPR suspend. We thus run through each
* TSTAT_CPU_ENABLED CPU, and explicitly destroy and reestablish its
* interposing trap table. This assures that our state is correct regardless
* of whether or not the CPU has been newly powered on.
*/
/*ARGSUSED*/
static boolean_t
{
if (code == CB_CODE_CPR_CHKPT)
return (B_TRUE);
if (!tstat_running) {
return (B_TRUE);
}
do {
continue;
/*
* Preserve this CPU's data in tstat_buffer and rip down its
* interposing trap table.
*/
/*
* Reestablish the interposing trap table and restore the old
* data.
*/
return (B_TRUE);
}
/*ARGSUSED*/
static int
{
int i;
if (tstat_open != 0) {
return (EBUSY);
}
/*
* Register this in open() rather than in attach() to prevent deadlock
* with DR code. During attach, I/O device tree locks are grabbed
* before trapstat_attach() is invoked - registering in attach
* will result in the lock order: device tree lock, cpu_lock.
* DR code however requires that cpu_lock be acquired before
* device tree locks.
*/
/*
* Clear all options. And until specific CPUs are specified, we'll
* mark all CPUs as selected.
*/
tstat_options = 0;
for (i = 0; i <= max_cpuid; i++)
/*
* By default, all traps at TL=0 are enabled. Traps at TL>0 must
* be disabled.
*/
for (i = 0; i < TSTAT_TOTAL_NENT; i++)
tstat_open = 1;
return (0);
}
/*ARGSUSED*/
static int
{
(void) trapstat_stop();
tstat_open = 0;
return (DDI_SUCCESS);
}
static int
trapstat_option(int option)
{
if (tstat_running) {
return (EBUSY);
}
tstat_options |= option;
return (0);
}
/*ARGSUSED*/
static int
{
int i, j, out;
switch (cmd) {
case TSTATIOC_GO:
return (trapstat_go());
case TSTATIOC_NOGO:
return (trapstat_option(TSTAT_OPT_NOGO));
case TSTATIOC_STOP:
return (trapstat_stop());
case TSTATIOC_CPU:
return (EINVAL);
/*FALLTHROUGH*/
case TSTATIOC_NOCPU:
if (tstat_running) {
return (EBUSY);
}
/*
* If this is the first CPU to be specified (or if we are
* being asked to explicitly de-select CPUs), disable all CPUs.
*/
for (i = 0; i <= max_cpuid; i++) {
}
}
if (cmd == TSTATIOC_CPU)
return (0);
case TSTATIOC_ENTRY:
if (tstat_running) {
return (EBUSY);
}
return (EINVAL);
}
if (!(tstat_options & TSTAT_OPT_ENTRY)) {
/*
* If this is the first entry that we are explicitly
* enabling, explicitly disable every TL=0 entry.
*/
for (i = 0; i < TSTAT_NENT; i++)
tstat_enabled[i] = 0;
}
return (0);
case TSTATIOC_NOENTRY:
if (tstat_running) {
return (EBUSY);
}
for (i = 0; i < TSTAT_NENT; i++)
tstat_enabled[i] = 0;
return (0);
case TSTATIOC_READ:
if (tstat_options & TSTAT_OPT_TLBDATA) {
} else {
dsize = sizeof (tstat_data_t);
}
continue;
/*
* This CPU is not currently responding to
* cross calls; we have caught it while it is
* being unconfigured. We'll drop tstat_lock
* and pick up and drop cpu_lock. By the
* time we acquire cpu_lock, the DR operation
* will appear consistent and we can assert
* that trapstat_cpu_setup() has cleared
* TSTAT_CPU_ENABLED.
*/
continue;
}
/*
* Need to compensate for the difference between page
* sizes exported to users and page sizes available
* within the kernel.
*/
if ((tstat_options & TSTAT_OPT_TLBDATA) &&
(tstat_pgszs != tstat_user_pgszs)) {
for (j = 0; j < tstat_user_pgszs; j++) {
if ((szc = USERSZC_2_SZC(j)) != j) {
sizeof (tstat_pgszdata_t));
}
}
}
return (EFAULT);
}
out++;
}
return (EFAULT);
}
}
return (0);
case TSTATIOC_TLBDATA:
return (trapstat_option(TSTAT_OPT_TLBDATA));
default:
break;
}
return (ENOTTY);
}
/*ARGSUSED*/
static int
{
int error;
switch (infocmd) {
case DDI_INFO_DEVT2DEVINFO:
*result = (void *)tstat_devi;
error = DDI_SUCCESS;
break;
case DDI_INFO_DEVT2INSTANCE:
*result = (void *)0;
error = DDI_SUCCESS;
break;
default:
error = DDI_FAILURE;
}
return (error);
}
static int
{
switch (cmd) {
case DDI_ATTACH:
break;
case DDI_RESUME:
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
}
0, DDI_PSEUDO, 0) == DDI_FAILURE) {
return (DDI_FAILURE);
}
tstat_devi = devi;
tstat_data_t_size = sizeof (tstat_data_t) +
tstat_data_t_exported_size = sizeof (tstat_data_t) +
#ifndef sun4v
#else
tstat_data_pages = 0;
MMU_PAGESHIFT) + 1;
#endif
sizeof (tstat_percpu_t), KM_SLEEP);
/*
* Create our own arena backed by segkmem to assure a source of
* MMU_PAGESIZE-aligned allocations. We allocate out of the
* heap32_arena to assure that we can address the allocated memory with
*/
/*
* CB_CL_CPR_POST_USER is the class that executes from cpr_resume()
* after user threads can be restarted. By executing in this class,
* we are assured of the availability of system services needed to
* resume trapstat (specifically, we are assured that all CPUs are
* restarted and responding to cross calls).
*/
return (DDI_SUCCESS);
}
static int
{
int rval;
switch (cmd) {
case DDI_DETACH:
break;
case DDI_SUSPEND:
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*
* Configuration data structures
*/
static struct cb_ops trapstat_cb_ops = {
trapstat_open, /* open */
trapstat_close, /* close */
nulldev, /* strategy */
nulldev, /* print */
nodev, /* dump */
nodev, /* read */
nodev, /* write */
trapstat_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
ddi_prop_op, /* cb_prop_op */
0, /* streamtab */
};
static struct dev_ops trapstat_ops = {
DEVO_REV, /* devo_rev, */
0, /* refcnt */
trapstat_info, /* getinfo */
nulldev, /* identify */
nulldev, /* probe */
trapstat_attach, /* attach */
trapstat_detach, /* detach */
nulldev, /* reset */
&trapstat_cb_ops, /* cb_ops */
(struct bus_ops *)0, /* bus_ops */
};
&mod_driverops, /* Type of module. This one is a driver */
"Trap Statistics", /* name of module */
&trapstat_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
};
int
_init(void)
{
return (mod_install(&modlinkage));
}
int
_fini(void)
{
return (mod_remove(&modlinkage));
}
int
{
}