px_space.c revision f8d2de6bd2421da1926f3daa456d161670decdf7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* PCI Express nexus driver tunables
*/
#include "px_space.h"
/*LINTLIBRARY*/
/*
* The following variable enables a workaround for the following obp bug:
*
* 1234181 - obp should set latency timer registers in pci
* configuration header
*
* Until this bug gets fixed in the obp, the following workaround should
* be enabled.
*/
/*
* The following driver parameters are defined as variables to allow
* patching for debugging and tuning. Flags that can be set on a per
* PBM basis are bit fields where the PBM device instance number maps
* to the bit position.
*/
uint_t px_rerun_disable = 0;
uint_t px_dwsync_disable = 0;
uint_t px_intsync_disable = 0;
/*
* The following flag controls behavior of the ino handler routine
* when multiple interrupts are attached to a single ino. Typically
* this case would occur for the ino's assigned to the PCI bus slots
* with multi-function devices or bus bridges.
*
* Setting the flag to zero causes the ino handler routine to return
* after finding the first interrupt handler to claim the interrupt.
*
* Setting the flag to non-zero causes the ino handler routine to
* return after making one complete pass through the interrupt
* handlers.
*/
/*
* The following value is the number of consecutive unclaimed interrupts that
* will be tolerated for a particular ino_p before the interrupt is deemed to
* be jabbering and is blocked.
*/
/*
* The following value will cause the nexus driver to block an ino after
* px_unclaimed_intr_max unclaimed interrupts have been seen. Setting this
* value to 0 will cause interrupts to never be blocked, no matter how many
* unclaimed interrupts are seen on a particular ino.
*/
uint_t px_lock_tlb = 0;
uint64_t px_dvma_debug_on = 0;
/*
* dvma address space allocation cache variables
*/
#ifdef PX_DMA_PROF
#endif
uint_t px_disable_fdvma = 0;
/*
* This flag preserves prom MMU settings by copying prom TSB entries
* to corresponding kernel TSB entry locations. It should be removed
* after the interface properties from obp have become default.
*/
/*
* memory callback list id callback list for kmem_alloc failure clients
*/
uintptr_t px_kmem_clid = 0;
uint_t px_err_log_all = 0;
/*
* Do not enable Link Interrupts
*/
/*
* (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_S) |
* (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_P);
*/
/*
* LPU Intr Registers are reverse encoding from the registers above.
* 1 = disable
* 0 = enable
*
* Log and Count are however still the same.
*/
/* timeout in micro seconds for receiving PME_To_ACK */
/* PIL at which PME_To_ACK message interrupt is handled */