px_pec.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* PCI Express PEC implementation:
* initialization
* Bus error interrupt handler
*/
#include <sys/sysmacros.h>
#include <sys/ddi_impldefs.h>
#include "px_obj.h"
/*LINTLIBRARY*/
extern uint_t px_ranges_phi_mask;
static void
{
/*
* Register ilu error interrupt. This will
* also program the correct values into the
* log enable and interrupt enable registers.
*/
}
int
{
if (stat)
}
static void
{
}
static void
{
}
int
{
if (stat)
stat);
}
int
{
if (stat)
stat);
}
int
{
if (stat)
stat);
}
int
{
if (stat)
}
int
{
int i, len;
int ret;
/*
* Allocate a state structure for the PEC and cross-link it
* to its per px node state structure.
*/
sizeof (pec_p->pec_nameinst_str),
/*
* Add interrupt handlers to process correctable/fatal/non fatal
* PCIE messages.
*/
return (ret);
}
/*
* Get this pec's mem32 and mem64 segments to determine whether
* a dma object originates from ths pec. i.e. dev to dev dma
*/
switch (rng_type) {
case PCI_ADDR_MEM32:
break;
case PCI_ADDR_MEM64:
break;
case PCI_ADDR_CONFIG:
case PCI_ADDR_IO:
default:
continue;
}
px_ranges_phi_mask) << 32;
}
/*
* configure ILU.
*/
/*
* configure TLU.
*/
/*
* configure LPU
*/
/*
* Register a function to disable pec error interrupts during a panic.
* do in px_attach. bus_func_register(BF_TYPE_ERRDIS,
* (busfunc_t)pec_disable_pci_errors, pec_p);
*/
return (DDI_SUCCESS);
}
{
/*
* Disable error interrupts via the interrupt mapping register.
*/
return (BF_NONE);
}
void
{
/*
* Free the pokefault mutex.
*/
/*
* Remove the pci error interrupt handler.
*/
/*
* Remove the error disable function.
*/
/*
* Remove interrupt handlers to process correctable/fatal/non fatal
* PCIE messages.
*/
/*
* Free the pec state structure.
*/
}
/*
* pec_msg_add_intr:
*
* Add interrupt handlers to process correctable/fatal/non fatal
* PCIE messages.
*/
static int
{
int ret = DDI_SUCCESS;
/* Initilize handle */
/* Add correctable error message handler */
"PCIE_CORR_MSG registration failed\n");
return (DDI_FAILURE);
}
/* Add non-fatal error message handler */
"PCIE_NONFATAL_MSG registration failed\n");
return (DDI_FAILURE);
}
/* Add fatal error message handler */
"PCIE_FATAL_MSG registration failed\n");
return (DDI_FAILURE);
}
return (ret);
}
/*
* px_pec_msg_rem_intr:
*
* Remove interrupt handlers to process correctable/fatal/non fatal
* PCIE messages. For now, all these PCIe messages are mapped to
* same MSIQ.
*/
static void
{
/* Initilize handle */
if (pec_p->pec_corr_msg_msiq_id >= 0) {
}
if (pec_p->pec_non_fatal_msg_msiq_id >= 0) {
}
if (pec_p->pec_fatal_msg_msiq_id >= 0) {
}
}
/*ARGSUSED*/
{
"px_pec_corr_msg_intr: requester id 0x%x\n", rid);
return (DDI_INTR_CLAIMED);
}
/*ARGSUSED*/
{
"px_pec_non_fatal_msg_intr: requester id 0x%x\n", rid);
return (DDI_INTR_CLAIMED);
}
/*ARGSUSED*/
{
"px_pec_fatal_msg_intr: requester id 0x%x\n", rid);
return (DDI_INTR_CLAIMED);
}