px_pci.c revision 00d0963faf2e861a4aef6b1bf28f99a5b2b20755
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Sun4 PCI Express to PCI bus bridge nexus driver
*/
#include <sys/sysmacros.h>
#include <sys/autoconf.h>
#include <sys/ddi_impldefs.h>
#include <sys/ddi_subrdefs.h>
#include <sys/pcie_impl.h>
#include "pcie_pwr.h"
#include "px_pci.h"
#include "px_debug.h"
/* Tunables. Beware: Some are for debug purpose only. */
/*
* PXB MSI tunable:
*
* By default MSI is enabled on all supported platforms.
*/
void *, void *);
/*
* FMA functions
*/
const void *impl_data);
#ifdef PRINT_PLX_SEEPROM_CRC
#endif
struct bus_ops pxb_bus_ops = {
0,
0,
0,
ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */
ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */
ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */
ndi_post_event, /* (*bus_post_event)(); */
NULL, /* (*bus_intr_ctl)(); */
NULL, /* (*bus_config)(); */
NULL, /* (*bus_unconfig)(); */
pxb_fm_init_child, /* (*bus_fm_init)(); */
NULL, /* (*bus_fm_fini)(); */
i_ndi_busop_access_enter, /* (*bus_fm_access_enter)(); */
i_ndi_busop_access_exit, /* (*bus_fm_access_fini)(); */
pcie_bus_power, /* (*bus_power)(); */
pxb_intr_ops /* (*bus_intr_op)(); */
};
static struct cb_ops pxb_cb_ops = {
pxb_open, /* open */
pxb_close, /* close */
nulldev, /* strategy */
nulldev, /* print */
nulldev, /* dump */
nulldev, /* read */
nulldev, /* write */
pxb_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
pxb_prop_op, /* cb_prop_op */
NULL, /* streamtab */
CB_REV, /* rev */
nodev, /* int (*cb_aread)() */
nodev /* int (*cb_awrite)() */
};
static int pxb_probe(dev_info_t *);
/* Hotplug related functions */
DEVO_REV, /* devo_rev */
0, /* refcnt */
pxb_info, /* info */
nulldev, /* identify */
pxb_probe, /* probe */
pxb_attach, /* attach */
pxb_detach, /* detach */
nulldev, /* reset */
&pxb_cb_ops, /* driver operations */
&pxb_bus_ops, /* bus operations */
pcie_power /* power entry */
};
/*
* Module linkage information for the kernel.
*/
&mod_driverops, /* Type of module */
&pxb_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
(void *)&modldrv,
};
/*
* soft state pointer and structure template:
*/
void *pxb_state;
/*
* SW workaround for PLX HW bug Flag
*/
int pxb_tlp_count = 64;
/*
* forward function declarations:
*/
static void pxb_removechild(dev_info_t *);
int
_init(void)
{
int e;
return (e);
}
int
_fini(void)
{
int e;
if ((e = mod_remove(&modlinkage)) == 0)
return (e);
}
int
{
}
/*ARGSUSED*/
static int
{
instance);
switch (infocmd) {
default:
return (DDI_FAILURE);
case DDI_INFO_DEVT2INSTANCE:
return (DDI_SUCCESS);
case DDI_INFO_DEVT2DEVINFO:
return (DDI_FAILURE);
return (DDI_SUCCESS);
}
}
/*ARGSUSED*/
static int
{
return (DDI_PROBE_SUCCESS);
}
/*ARGSUSED*/
static int
{
int instance;
char device_type[8];
switch (cmd) {
case DDI_RESUME:
/*
* Get the soft state structure for the bridge.
*/
pxb = (pxb_devstate_t *)
(void) pcie_pwr_resume(devi);
return (DDI_SUCCESS);
case DDI_ATTACH:
/* Follow through to below the switch statement */
break;
default:
return (DDI_FAILURE);
}
/*
* Allocate and get soft state structure.
*/
return (DDI_FAILURE);
}
/* Create Mutex */
/* Setup and save the config space pointer */
goto fail;
}
/* Save the vnedor id and device id */
/*
* This is a software workaround to fix the Broadcom PCIe-PCI bridge
* prefetch bug. Create a boolean property and its existence means
* the px nexus driver has to allocate an extra page & make it valid
* one, for any DVMA request that comes from any of the Broadcom child
* device.
*/
if (PXB_IS_BCM5714(pxb)) {
"cross-page-prefetch") != DDI_PROP_SUCCESS) {
"ndi_prop_create_boolean() failed\n");
goto fail;
}
}
/*
* is at D0 during attach.
*/
goto fail;
goto fail;
}
goto fail;
}
/*
* Make sure the "device_type" property exists.
*/
else
"device_type", device_type);
/*
* Check whether the "ranges" property is present.
* Otherwise create the ranges property by reading
* the configuration registers
*/
"ranges") == 0) {
}
/*
* Initialize hotplug support on this bus. At minimum
* (for non hotplug bus) this would create ":devctl" minor
* node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
* to this bus. This all takes place if this nexus has hot-plug
* slots and successfully initializes Hot Plug Framework.
*/
}
/* attach interrupt only if hotplug functionality is required */
goto fail;
}
#ifdef PRINT_PLX_SEEPROM_CRC
/* check seeprom CRC to ensure the platform config is right */
(void) pxb_print_plx_seeprom_crc_data(pxb);
#endif
/*
* create minor node for devctl interfaces
*/
DDI_NT_NEXUS, 0) != DDI_SUCCESS)
goto fail;
}
"pxb_attach(): this nexus %s hotplug slots\n",
goto fail;
}
return (DDI_SUCCESS);
fail:
return (DDI_FAILURE);
}
/*ARGSUSED*/
static int
{
int error = DDI_SUCCESS;
switch (cmd) {
case DDI_DETACH:
/*
* And finally free the per-pci soft state after
* uninitializing hotplug support for this bus in
* opposite order of attach.
*/
pxb = (pxb_devstate_t *)
error = DDI_FAILURE;
(void) pciehpc_uninit(devi);
(void) pcishpc_uninit(devi);
}
else
"cross-page-prefetch");
return (error);
case DDI_SUSPEND:
pxb = (pxb_devstate_t *)
return (error);
}
return (DDI_FAILURE);
}
/*ARGSUSED*/
static int
{
register dev_info_t *pdip;
}
/*ARGSUSED*/
static int
{
int reglen;
int rn;
int totreg;
struct detachspec *ds;
struct attachspec *as;
switch (ctlop) {
case DDI_CTLOPS_REPORTDEV:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_INITCHILD:
case DDI_CTLOPS_UNINITCHILD:
return (DDI_SUCCESS);
case DDI_CTLOPS_SIDDEV:
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE:
case DDI_CTLOPS_NREGS:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
break;
case DDI_CTLOPS_ATTACH:
case DDI_PRE:
return (pcie_pm_hold(dip));
}
DDI_SUCCESS) {
}
}
return (DDI_SUCCESS);
case DDI_POST:
return (DDI_SUCCESS);
default:
break;
}
break;
case DDI_CTLOPS_DETACH:
case DDI_POST:
}
return (DDI_SUCCESS);
default:
break;
}
break;
default:
}
*(int *)result = 0;
return (DDI_FAILURE);
if (ctlop == DDI_CTLOPS_NREGS)
else if (ctlop == DDI_CTLOPS_REGSIZE) {
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
}
static dev_info_t *
{
;
return (cdip);
}
static int
{
goto done;
/*
* If the interrupt-map property is defined at this
* node, it will have performed the interrupt
* translation as part of the property, so no
* rotation needs to be done.
*/
goto done;
/*
* Use the devices reg property to determine its
* PCI bus number and device number.
*/
return (DDI_FAILURE);
/* spin the interrupt */
else
done:
/* Pass up the request to our parent. */
}
/*
* name_child
*
* This function is called from init_child to name a node. It is
* also passed as a callback for node merging functions.
*
* return value: DDI_SUCCESS, DDI_FAILURE
*/
static int
{
char **unit_addr;
uint_t n;
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
return (DDI_FAILURE);
}
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*
* Get the address portion of the node name based on
* the function and device number.
*/
return (DDI_FAILURE);
}
if (func != 0)
else
return (DDI_SUCCESS);
}
static int
{
char name[MAXNAMELEN];
int result = DDI_FAILURE;
int i;
/*
* Name the child
*/
goto done;
}
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
extern int pci_allow_pseudo_children;
/*
* Try to merge the properties from this prototype
* node into real h/w nodes.
*/
/*
* Merged ok - return failure to remove the node.
*/
goto done;
}
/* workaround for ddivs to run under PCI */
if (pci_allow_pseudo_children) {
goto done;
}
/*
* The child was not merged into a h/w node,
* but there's not much we can do with it other
* than return failure to cause the node to be removed.
*/
goto done;
}
"INITCHILD: px_pm_hold failed\n");
goto done;
}
/* Any return from here must call pcie_pm_release */
/*
* If configuration registers were previously saved by
* child (before it entered D3), then let the child do the
* restore to set up the config regs as it'll first need to
* power the device out of D3.
*/
"config-regs-saved-by-child") == 1) {
"INITCHILD: config regs to be restored by child"
goto cleanup;
}
"INITCHILD: config regs setup for %s@%s\n",
goto cleanup;
}
/*
* Due to a PLX HW bug, a SW workaround to prevent the chip from
* wedging is needed. SW just needs to tranfer 64 TLPs from
* the downstream port to the child device.
* The most benign way of doing this is to read the ID register
* 64 times. This SW workaround should have minimum performance
* impact and shouldn't cause a problem for all other bridges
* and switches.
*
* The code needs to be written in a way to make sure it isn't
* optimized out.
*/
if ((!pxb_tlp_count) ||
/* Workaround not needed return success */
goto cleanup;
}
goto cleanup;
}
for (i = 0; i < pxb_tlp_count; i += 1)
done:
return (result);
}
static int
{
int intr_types;
uint8_t bad_msi_dev = 0;
/*
* Initialize interrupt handlers.
* If both MSI and FIXED are supported, try to attach MSI first.
* If MSI fails for any reason, then try FIXED, but only allow one
* type to be attached.
*/
return (DDI_FAILURE);
}
bad_msi_dev = 1;
!bad_msi_dev) {
else
}
if (intr_types & DDI_INTR_TYPE_FIXED) {
"Unable to attach INTx handler\n");
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
}
/*
* This function initializes internally generated interrupts only.
* It does not affect any interrupts generated by downstream devices
* or the forwarding of them.
*
* Enable Device Specific Interrupts or Hotplug features here.
* Enabling features may change how many interrupts are requested
* by the device. If features are not enabled first, the
* device might not ask for any interrupts.
*/
static int
{
int ret;
int intr_cap = 0;
"Attaching %s handler\n",
/*
* Get number of requested interrupts. If none requested or DDI_FAILURE
* just return DDI_SUCCESS.
*
* in a FAILURE, if the device is not configured in a way that
* interrupts are needed. (eg. hotplugging)
*/
return (DDI_SUCCESS);
}
/* Find out how many MSI's are available. */
if (intr_type == DDI_INTR_TYPE_MSI) {
"ddi_intr_get_navail() ret: %d available: %d\n",
goto fail;
}
"Requested Intr: %d Available: %d\n",
}
}
/* Allocate an array of interrupt handlers */
"ddi_intr_alloc() ret: %d ask: %d actual: %d\n",
goto fail;
}
/* Save the actually number of interrupts allocated */
"Requested Intr: %d Received: %d\n",
}
/* Get interrupt priority */
if (ret != DDI_SUCCESS) {
goto fail;
}
if (ret != DDI_SUCCESS) {
ret);
goto fail;
}
}
if (ret != DDI_SUCCESS) {
"ddi_intr_add_handler() ret: %d\n",
ret);
break;
}
}
/* If unsucessful remove the added handlers */
if (ret != DDI_SUCCESS) {
for (x = 0; x < count; x++) {
}
goto fail;
}
if (intr_cap & DDI_INTR_FLAG_BLOCK) {
} else {
}
}
/* Save the interrupt type */
return (DDI_SUCCESS);
fail:
return (DDI_FAILURE);
}
static void
{
int x;
}
for (x = 0; x < count; x++) {
if (flags & PXB_INIT_ENABLE)
if (flags & PXB_INIT_HANDLER)
if (flags & PXB_INIT_ALLOC)
}
if (flags & PXB_INIT_HTABLE)
flags &= ~PXB_INIT_HTABLE;
}
/*
* This only handles internal errors, not bus errors.
* Currently the only known interrupt would be from hotplugging.
*/
/*ARGSUSED*/
static uint_t
{
int rval = DDI_INTR_UNCLAIMED;
else
}
return (rval);
}
static int
{
/*
* Check if capabilities list is supported. If not then it is a PCI
* device. If so, check to see if it contains PCI Express Capability
* Register. Eventually move this code to PCI-EX Framework.
*/
& PCI_STAT_CAP)
PCI_CONF_CAP_PTR), 4);
else
while (caps_ptr != PCI_CAP_NEXT_PTR_NULL) {
if (caps_ptr < 0x40) {
"Capability pointer 0x%x out of range.\n",
caps_ptr);
break;
}
if (cap == PCI_CAP_ID_PCI_E) {
break;
}
}
return (port_type);
}
static void
{
/*
* Strip the node to properly convert it back to prototype form
*/
}
/*
* Initialize hotplug framework if we are hotpluggable.
* Sets flag in the soft state if Hot Plug is supported and initialized
* properly.
*/
/*ARGSUSED*/
static void
{
int rv;
if (rv == DDI_SUCCESS)
if (rv == DDI_SUCCESS)
}
"%s%d: Failed setting hotplug framework",
}
}
}
static void
{
int i = 0, rangelen = sizeof (pxb_ranges_t)/sizeof (int);
/*
* Create ranges for IO space
*/
ranges[i].parent_high = 0;
(PCI_REG_REL_M | PCI_ADDR_IO);
}
}
}
/*
* Create ranges for 32bit memory space
*/
ranges[i].parent_high = 0;
i++;
}
if (i) {
}
}
/*ARGSUSED*/
static int
{
/*
* Make sure the open is for the right file type.
*/
return (EINVAL);
/*
* Get the soft state structure for the device.
*/
instance);
return (ENXIO);
/*
* Handle the open by tracking the device state.
*/
return (EBUSY);
}
} else {
return (EBUSY);
}
}
return (0);
}
/*ARGSUSED*/
static int
{
return (EINVAL);
instance);
return (ENXIO);
return (0);
}
/*
* pxb_ioctl: devctl hotplug controls
*/
/*ARGSUSED*/
static int
int *rvalp)
{
struct devctl_iocdata *dcp;
int rv = 0;
instance);
return (ENXIO);
/*
* We can use the generic implementation for these ioctls
*/
switch (cmd) {
case DEVCTL_DEVICE_GETSTATE:
case DEVCTL_DEVICE_ONLINE:
case DEVCTL_DEVICE_OFFLINE:
case DEVCTL_BUS_GETSTATE:
}
/*
* read devctl ioctl data
*/
return (EFAULT);
switch (cmd) {
case DEVCTL_DEVICE_RESET:
break;
case DEVCTL_BUS_QUIESCE:
if (bus_state == BUS_QUIESCED)
break;
break;
case DEVCTL_BUS_UNQUIESCE:
if (bus_state == BUS_ACTIVE)
break;
break;
case DEVCTL_BUS_RESET:
break;
case DEVCTL_BUS_RESETALL:
break;
default:
}
return (rv);
}
{
instance);
return (ENXIO);
}
/*
* Power management related initialization specific to px_pci.
* Called by pxb_attach()
*/
static int
{
char *comp_array[5];
int i, instance;
/*
* Disable PM for PLX 8532 switch. Transitioning one port on
* this switch to low power causes links on other ports on the
* same station to die.
* Due to PLX erratum #34, we can't allow the downstream device
* go to non-D0 state.
*/
"disabling PM\n");
return (DDI_SUCCESS);
}
/* Code taken from pci_pci driver */
return (DDI_FAILURE);
}
/*
* Walk the capabilities searching for a PM entry.
*/
while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
cap_ptr + PCI_CAP_ID);
if (cap_id == PCI_CAP_ID_PM) {
break;
}
}
if (cap_ptr == 0) {
" PM data structure not found in config header\n");
return (DDI_SUCCESS);
}
/*
* Save offset to pmcsr for future references.
*/
if (pmcap & PCI_PMCAP_D1) {
}
if (pmcap & PCI_PMCAP_D2) {
}
i = 0;
comp_array[i++] = "NAME=PCIe switch/bridge PM";
comp_array[i++] = "0=Power Off (D3)";
comp_array[i++] = "1=D2";
comp_array[i++] = "2=D1";
comp_array[i++] = "3=Full Power D0";
/*
* Create pm-components property, if it does not exist already.
*/
return (DDI_FAILURE);
}
}
/*
* Initializes the power level and raise the power to D0, if it is
* not at D0.
*/
static int
{
int ret = DDI_SUCCESS;
/*
* Intialize our power level from PMCSR. The common code initializes
* this to UNKNOWN. There is no guarantee that we will be at full
* power at attach. If we are not at D0, raise the power.
*/
switch (pmcsr) {
case PCI_PMCSR_D0:
break;
case PCI_PMCSR_D1:
break;
case PCI_PMCSR_D2:
break;
case PCI_PMCSR_D3HOT:
break;
default:
break;
}
/* Raise the power to D0. */
/*
* Read PMCSR again. If it is at D0, ignore the return
* value from pm_raise_power.
*/
ret = DDI_SUCCESS;
else {
"power to D0 \n");
}
}
if (ret == DDI_SUCCESS)
return (ret);
}
static int
{
/*
* Request our capability level and get our parents capability
* and ibc.
*/
/*
* Register error callback with our parent.
*/
(void *)&pxb_p->pxb_config_handle);
return (DDI_SUCCESS);
}
/*
* Breakdown our FMA resources
*/
static void
{
/*
* Clean up allocated fm structures
*/
}
/*
* Function used to initialize FMA for our children nodes. Called
* through pci busops when child node calls ddi_fm_init.
*/
/*ARGSUSED*/
int
{
}
/*
* FMA Error callback handler.
* Need to revisit when pcie fm is supported.
*/
/*ARGSUSED*/
static int
const void *impl_data)
{
return (derr->fme_status);
}
/*
* undo whatever is done in pxb_pwr_setup. called by pxb_detach()
*/
static void
{
return;
if (pwr_p->pwr_conf_hdl)
}
/*ARGSUSED*/
{
if (!(status & PCI_STAT_CAP))
else {
cap_ptr &= 0xFC;
}
while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
if (cap_id == PCI_CAP_ID_PCI_E) {
if (slotimpl)
PCIE_SLOTCAP) &
break;
}
cap_ptr &= 0xFC;
}
}
/*ARGSUSED*/
{
if (!(status & PCI_STAT_CAP))
else {
cap_ptr &= 0xFC;
}
while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
if (cap_id == PCI_CAP_ID_PCI_HOTPLUG)
break;
cap_ptr &= 0xFC;
}
}
/* check if this device has PCIe link underneath. */
static int
{
/* No PCIe CAP regs, we are not PCIe device_type */
if (port_type < 0)
return (DDI_FAILURE);
/* check for all PCIe device_types */
if ((port_type == PCIE_PCIECAP_DEV_TYPE_UP) ||
(port_type == PCIE_PCIECAP_DEV_TYPE_DOWN) ||
return (DDI_SUCCESS);
return (DDI_FAILURE);
}
#ifdef PRINT_PLX_SEEPROM_CRC
static void
{
int nregs;
};
return;
return;
return;
return;
&mattr, &h) != DDI_SUCCESS)
return;
printf("%s#%d: EEPROM StatusReg = %x, CRC = %x\n",
#ifdef PLX_HOT_RESET_DISABLE
/* prevent hot reset from propogating downstream. */
printf("%s#%d: EEPROM 0x1DC prewrite=%x postwrite=%x\n",
#endif
ddi_regs_map_free(&h);
}
#endif
/*
* given a cap_id, return its cap_id location in config space
*/
static int
{
int location = -1;
/*
* Need to check the Status register for ECP support first.
* Also please note that for type 1 devices, the
* offset could change. Should support type 1 next.
*/
if (!(status & PCI_STAT_CAP)) {
return (-1);
}
/* Walk the list of capabilities */
while (cap_id_loc) {
break;
}
cap_id_loc + 1);
}
return (location);
}
static uint16_t
{
while ((hdr_next_ptr != PCIE_EXT_CAP_NEXT_PTR_NULL) &&
(hdr_cap_id != cap_id)) {
}
if (hdr_cap_id == cap_id)
return (PCIE_EXT_CAP_NEXT_PTR_NULL);
}
/* check for known bad functionality in devices */
static int
{
switch (func) {
/* some devices do not render MSI well. */
case PXB_MSI:
if (pxb->pxb_rev_id <=
}
break;
case PXB_LINK_INIT:
/*
* some devices require certain initialization sequence so
* as to not get wedged.
*/
case PXB_HOTPLUG_MSGS:
/*
* disable UR for 1.0a implementations where
* hotplug messages sent downstream cause URs to be
* detected causing error messages to be sent to the fabric.
*/
}
if (func == PXB_HOTPLUG_MSGS)
break;
default:
break;
}
return (ret);
}
/* check for known bad devices from a vendor */
static int
{
switch (vend) {
case PXB_VENDOR_SUN:
((pxb->pxb_device_id ==
(pxb->pxb_device_id ==
PXB_DEVICE_PLX_PCIE))) {
}
break;
case PXB_VENDOR_PLX:
((pxb->pxb_device_id ==
(pxb->pxb_device_id ==
PXB_DEVICE_PLX_8516))) {
}
break;
default:
break;
}
return (ret);
}