px_ib.c revision 25cf1a301a396c38e8adf52c15f537b80d2483f7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* PX Interrupt Block implementation
*/
#include <sys/ddi_impldefs.h>
#include "px_obj.h"
/*LINTLIBRARY*/
extern uint64_t xc_tick_jump_limit;
int
{
return (DDI_FAILURE);
/*
* Allocate interrupt block state structure and link it to
* the px state structure.
*/
/*
* Initialize PEC fault data structure
*/
return (DDI_SUCCESS);
}
void
{
}
void
{
/*
* Determine the cpu for the interrupt
*/
&sysino) != DDI_SUCCESS) {
"px_ib_intr_enable: px_intr_devino_to_sysino() failed\n");
return;
}
}
/*ARGSUSED*/
void
{
/* Disable the interrupt */
&sysino) != DDI_SUCCESS) {
"px_ib_intr_disable: px_intr_devino_to_sysino() failed\n");
return;
}
}
void
{
int e = DDI_SUCCESS;
"px_intr_devino_to_sysino() failed, ino 0x%x\n", ino);
return;
}
/* Skip enabling disabled interrupts */
"failed, sysino 0x%x\n", sysino);
return;
}
if (!enabled)
return;
/* Done if redistributed onto the same cpuid */
"px_intr_gettarget() failed\n");
return;
}
if (cpu_id == old_cpu_id)
return;
if (!wait_flag)
goto done;
/* Busy wait on pending interrupts */
DDI_SUCCESS) &&
/*
* If we have a really large jump in hrtime, it is most
* probably because we entered the debugger (or OBP,
* in general). So, we adjust the timeout accordingly
* to prevent declaring an interrupt timeout. The
* master-interrupt mechanism in OBP should deliver
* the interrupts properly.
*/
intr_timeout += interval;
"%s%d: px_ib_intr_dist_en: sysino 0x%lx(ino 0x%x) "
"from cpu id 0x%x to 0x%x timeout",
e = DDI_FAILURE;
break;
}
}
if (e != DDI_SUCCESS)
done:
}
static void
{
extern kmutex_t pxintr_ks_template_lock;
/*
* Because we are updating two fields in ih_t we must lock
* pxintr_ks_template_lock to prevent someone from reading the
* kstats after we set ih_ticks to 0 and before we increment
* ih_nsec to compensate.
*
* We must also protect against the interrupt arriving and incrementing
* ih_ticks between the time we read it and when we reset it to 0.
* To do this we use atomic_swap.
*/
}
/*
* Redistribute interrupts of the specified weight. The first call has a weight
* of weight_max, which can be used to trigger initialization for
* redistribution. The inos with weight [weight_max, inf.) should be processed
* on the "weight == weight_max" call. This first call is followed by calls
* of decreasing weights, inos of that weight should be processed. The final
* call specifies a weight of zero, this can be used to trigger processing of
* stragglers.
*/
static void
{
int i;
/* Redistribute internal interrupts */
if (weight == 0) {
}
/* Redistribute device interrupts */
/*
* Recomputes the sum of interrupt weights of devices that
* share the same ino upon first call marked by
* (weight == weight_max).
*/
if (weight == weight_max) {
ino_p->ino_intr_weight = 0;
i < ino_p->ino_ih_size;
if (dweight > 0)
}
}
/*
* As part of redistributing weighted interrupts over cpus,
* nexus redistributes device interrupts and updates
* cpu weight. The purpose is for the most light weighted
* cpu to take the next interrupt and gain weight, therefore
* attention demanding device gains more cpu attention by
* making itself heavy.
*/
((weight >= weight_max) &&
/* select cpuid to target and mark ino established */
/* Add device weight to targeted cpu. */
i < ino_p->ino_ih_size;
/*
* Different cpus may have different clock
* speeds. to account for this, whenever an
* interrupt is moved to a new CPU, we
* convert the accumulated ticks into nsec,
* based upon the clock rate of the prior
* CPU.
*
* It is possible that the prior CPU no longer
* exists. In this case, fall back to using
* this CPU's clock rate.
*
* Note that the value in ih_ticks has already
* been corrected for any power savings mode
* which might have been in effect.
*/
}
/* enable interrupt on new targeted cpu */
}
}
}
/*
* Reset interrupts to IDLE. This function is called during
* panic handling after redistributing interrupts; it's needed to
* support dumping to network devices after 'sync' from OBP.
*
* N.B. This routine runs in a context where all other threads
* are permanently suspended.
*/
static uint_t
px_ib_intr_reset(void *arg)
{
return (BF_FATAL);
return (BF_NONE);
}
/*
* Locate ino_info structure on ib_p->ib_ino_lst according to ino#
* returns NULL if not found.
*/
{
return (ino_p);
}
{
KM_SLEEP);
ino_p->ino_unclaimed = 0;
&sysino) != DDI_SUCCESS)
return (NULL);
/*
* Cannot disable interrupt since we might share slot
*/
return (ino_p);
}
/*
* The ino_p is retrieved by previous call to px_ib_locate_ino().
*/
void
{
else {
}
}
/*
* Free all ino when we are detaching.
*/
void
{
while (tmp) {
}
}
int
{
int ret = DDI_SUCCESS;
/* Disable the interrupt */
&curr_cpu)) != DDI_SUCCESS) {
"px_ib_ino_add_intr px_intr_gettarget() failed\n");
return (ret);
}
/* Busy wait on pending interrupt */
"sysino 0x%lx(ino 0x%x) timeout",
ret = DDI_FAILURE;
break;
}
}
if (ret != DDI_SUCCESS) {
return (ret);
}
/* Link up px_ispec_t portion of the ppd */
ino_p->ino_ih_size++;
/*
* If the interrupt was previously blocked (left in pending state)
* because of jabber we need to clear the pending state in case the
* jabber has gone away.
*/
"%s%d: px_ib_ino_add_intr: ino 0x%x has been unblocked",
ino_p->ino_unclaimed = 0;
INTR_IDLE_STATE)) != DDI_SUCCESS) {
"px_ib_ino_add_intr px_intr_setstate failed\n");
return (ret);
}
}
/* Re-enable interrupt */
return (ret);
}
/*
* Removes px_ispec_t from the ino's link list.
* uses hardware mutex to lock out interrupt threads.
* Side effects: interrupt belongs to that ino is turned off on return.
* if we are sharing PX slot with other inos, the caller needs
* to turn it back on.
*/
int
{
int i, ret = DDI_SUCCESS;
/* Disable the interrupt */
goto not_found;
goto reset;
}
/* Busy wait on pending interrupt */
"sysino 0x%lx(ino 0x%x) timeout",
ret = DDI_FAILURE;
break;
}
}
if (ret != DDI_SUCCESS) {
return (ret);
}
/*
* If the interrupt was previously blocked (left in pending state)
* because of jabber we need to clear the pending state in case the
* jabber has gone away.
*/
"ino 0x%x has been unblocked",
ino_p->ino_unclaimed = 0;
INTR_IDLE_STATE)) != DDI_SUCCESS) {
"px_ib_ino_rem_intr px_intr_setstate failed\n");
return (ret);
}
}
/* Search the link list for ih_p */
for (i = 0; (i < ino_p->ino_ih_size) &&
goto not_found;
if (ih_p->ih_config_handle)
ino_p->ino_ih_size--;
return (ret);
return (DDI_FAILURE);
}
px_ih_t *
{
int i;
return (ih_lst);
}
}
px_ih_t *
{
return (ih_p);
}
int
{
int ret = DDI_FAILURE;
msg_code)) {
ret = DDI_SUCCESS;
}
}
return (ret);
}
static void
{
}
/*
* Return the dips or number of dips associated with a given interrupt block.
* Size of dips array arg is passed in as dips_ret arg.
* Number of dips returned is returned in dips_ret arg.
* Array of dips gets returned in the dips argument.
* Function returns number of dips existing for the given interrupt block.
*
* the px node and (Internal) when it finds no other devices (and *devs_ret > 0)
*/
{
char pathname[MAXPATHLEN];
int i;
px_fill_in_intr_devs(&devs[i],
}
*devs_ret = i;
} else if (*devs_ret > 0) {
px_fill_in_intr_devs(&devs[0],
}
return (num_devs);
}
void
{
/* Log in OS data structures the new CPU. */
/* Log in OS data structures the new CPU. */
/* Account for any residual time to be logged for old cpu. */
}
}