px.c revision c2cc6e0756df4cf338a68021e19d09219abba393
0N/A/*
880N/A * CDDL HEADER START
0N/A *
0N/A * The contents of this file are subject to the terms of the
0N/A * Common Development and Distribution License (the "License").
0N/A * You may not use this file except in compliance with the License.
0N/A *
0N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
0N/A * or http://www.opensolaris.org/os/licensing.
0N/A * See the License for the specific language governing permissions
0N/A * and limitations under the License.
0N/A *
0N/A * When distributing Covered Code, include this CDDL HEADER in each
0N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
0N/A * If applicable, add the following below this CDDL HEADER, with the
0N/A * fields enclosed by brackets "[]" replaced with your own identifying
0N/A * information: Portions Copyright [yyyy] [name of copyright owner]
0N/A *
0N/A * CDDL HEADER END
0N/A */
0N/A/*
0N/A * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
0N/A * Use is subject to license terms.
0N/A */
0N/A
0N/A/*
0N/A * PCI Express nexus driver interface
0N/A */
0N/A
0N/A#include <sys/types.h>
0N/A#include <sys/conf.h> /* nulldev */
0N/A#include <sys/stat.h> /* devctl */
0N/A#include <sys/kmem.h>
0N/A#include <sys/sunddi.h>
0N/A#include <sys/sunndi.h>
0N/A#include <sys/ddi_impldefs.h>
0N/A#include <sys/ddi_subrdefs.h>
0N/A#include <sys/spl.h>
0N/A#include <sys/epm.h>
0N/A#include <sys/iommutsb.h>
0N/A#include <sys/hotplug/pci/pcihp.h>
0N/A#include <sys/hotplug/pci/pciehpc.h>
0N/A#include "px_obj.h"
0N/A#include <sys/pci_tools.h>
0N/A#include "px_tools_ext.h"
0N/A#include <sys/pcie_pwr.h>
0N/A
0N/A/*LINTLIBRARY*/
0N/A
1064N/A/*
0N/A * function prototypes for dev ops routines:
0N/A */
0N/Astatic int px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
0N/Astatic int px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
0N/Astatic int px_info(dev_info_t *dip, ddi_info_cmd_t infocmd,
0N/A void *arg, void **result);
0N/Astatic int px_cb_attach(px_t *);
0N/Astatic void px_cb_detach(px_t *);
0N/Astatic int px_pwr_setup(dev_info_t *dip);
0N/Astatic void px_pwr_teardown(dev_info_t *dip);
1064N/A
0N/Astatic void px_set_mps(px_t *px_p);
0N/A
0N/Aextern int pcie_max_mps;
0N/A
0N/A/*
0N/A * function prototypes for hotplug routines:
0N/A */
0N/Astatic int px_init_hotplug(px_t *px_p);
0N/Astatic int px_uninit_hotplug(dev_info_t *dip);
0N/A
0N/A/*
0N/A * bus ops and dev ops structures:
0N/A */
0N/Astatic struct bus_ops px_bus_ops = {
0N/A BUSO_REV,
0N/A px_map,
0N/A 0,
0N/A 0,
0N/A 0,
0N/A i_ddi_map_fault,
0N/A px_dma_setup,
0N/A px_dma_allochdl,
0N/A px_dma_freehdl,
0N/A px_dma_bindhdl,
0N/A px_dma_unbindhdl,
0N/A px_lib_dma_sync,
0N/A px_dma_win,
0N/A px_dma_ctlops,
0N/A px_ctlops,
0N/A ddi_bus_prop_op,
0N/A ndi_busop_get_eventcookie,
0N/A ndi_busop_add_eventcall,
0N/A ndi_busop_remove_eventcall,
0N/A ndi_post_event,
0N/A NULL,
0N/A NULL, /* (*bus_config)(); */
0N/A NULL, /* (*bus_unconfig)(); */
0N/A px_fm_init_child, /* (*bus_fm_init)(); */
0N/A NULL, /* (*bus_fm_fini)(); */
0N/A px_bus_enter, /* (*bus_fm_access_enter)(); */
0N/A px_bus_exit, /* (*bus_fm_access_fini)(); */
0N/A pcie_bus_power, /* (*bus_power)(); */
0N/A px_intr_ops /* (*bus_intr_op)(); */
0N/A};
0N/A
0N/Aextern struct cb_ops px_cb_ops;
0N/A
0N/Astatic struct dev_ops px_ops = {
0N/A DEVO_REV,
0N/A 0,
0N/A px_info,
0N/A nulldev,
0N/A 0,
0N/A px_attach,
1064N/A px_detach,
1064N/A nodev,
1064N/A &px_cb_ops,
1064N/A &px_bus_ops,
0N/A nulldev,
0N/A ddi_quiesce_not_needed, /* quiesce */
0N/A};
0N/A
0N/A/*
0N/A * module definitions:
0N/A */
0N/A#include <sys/modctl.h>
0N/Aextern struct mod_ops mod_driverops;
0N/A
0N/Astatic struct modldrv modldrv = {
0N/A &mod_driverops, /* Type of module - driver */
0N/A "PCI Express nexus driver", /* Name of module. */
0N/A &px_ops, /* driver ops */
0N/A};
0N/A
0N/Astatic struct modlinkage modlinkage = {
0N/A MODREV_1, (void *)&modldrv, NULL
0N/A};
0N/A
0N/A/* driver soft state */
0N/Avoid *px_state_p;
0N/A
0N/Aint
0N/A_init(void)
0N/A{
0N/A int e;
0N/A
0N/A /*
0N/A * Initialize per-px bus soft state pointer.
0N/A */
0N/A e = ddi_soft_state_init(&px_state_p, sizeof (px_t), 1);
0N/A if (e != DDI_SUCCESS)
0N/A return (e);
0N/A
0N/A /*
0N/A * Install the module.
0N/A */
0N/A e = mod_install(&modlinkage);
0N/A if (e != DDI_SUCCESS)
0N/A ddi_soft_state_fini(&px_state_p);
0N/A return (e);
0N/A}
0N/A
0N/Aint
0N/A_fini(void)
0N/A{
0N/A int e;
0N/A
0N/A /*
0N/A * Remove the module.
0N/A */
0N/A e = mod_remove(&modlinkage);
0N/A if (e != DDI_SUCCESS)
0N/A return (e);
0N/A
0N/A /* Free px soft state */
0N/A ddi_soft_state_fini(&px_state_p);
0N/A
0N/A return (e);
0N/A}
0N/A
0N/Aint
0N/A_info(struct modinfo *modinfop)
0N/A{
0N/A return (mod_info(&modlinkage, modinfop));
0N/A}
0N/A
0N/A/* ARGSUSED */
0N/Astatic int
0N/Apx_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
0N/A{
0N/A int instance = getminor((dev_t)arg);
0N/A px_t *px_p = INST_TO_STATE(instance);
0N/A
1064N/A /*
1064N/A * Allow hotplug to deal with ones it manages
1064N/A * Hot Plug will be done later.
1064N/A */
1064N/A if (px_p && (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE))
0N/A return (pcihp_info(dip, infocmd, arg, result));
0N/A
0N/A /* non-hotplug or not attached */
0N/A switch (infocmd) {
0N/A case DDI_INFO_DEVT2INSTANCE:
0N/A *result = (void *)(intptr_t)instance;
0N/A return (DDI_SUCCESS);
0N/A
0N/A case DDI_INFO_DEVT2DEVINFO:
0N/A if (px_p == NULL)
0N/A return (DDI_FAILURE);
0N/A *result = (void *)px_p->px_dip;
0N/A return (DDI_SUCCESS);
0N/A
1150N/A default:
0N/A return (DDI_FAILURE);
0N/A }
0N/A}
0N/A
0N/A/* device driver entry points */
0N/A/*
0N/A * attach entry point:
0N/A */
0N/A/*ARGSUSED*/
0N/Astatic int
0N/Apx_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
0N/A{
0N/A px_t *px_p; /* per bus state pointer */
0N/A int instance = DIP_TO_INST(dip);
0N/A int ret = DDI_SUCCESS;
0N/A devhandle_t dev_hdl = NULL;
0N/A
0N/A switch (cmd) {
0N/A case DDI_ATTACH:
0N/A DBG(DBG_ATTACH, dip, "DDI_ATTACH\n");
0N/A
0N/A /*
0N/A * Allocate and get the per-px soft state structure.
0N/A */
0N/A if (ddi_soft_state_zalloc(px_state_p, instance)
0N/A != DDI_SUCCESS) {
0N/A cmn_err(CE_WARN, "%s%d: can't allocate px state",
0N/A ddi_driver_name(dip), instance);
0N/A goto err_bad_px_softstate;
0N/A }
0N/A px_p = INST_TO_STATE(instance);
0N/A px_p->px_dip = dip;
0N/A mutex_init(&px_p->px_mutex, NULL, MUTEX_DRIVER, NULL);
0N/A px_p->px_soft_state = PX_SOFT_STATE_CLOSED;
0N/A px_p->px_open_count = 0;
0N/A
0N/A (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip,
0N/A "device_type", "pciex");
0N/A
0N/A /* Initialize px_dbg for high pil printing */
0N/A px_dbg_attach(dip, &px_p->px_dbg_hdl);
0N/A
0N/A /*
0N/A * Get key properties of the pci bridge node and
0N/A * determine it's type (psycho, schizo, etc ...).
0N/A */
0N/A if (px_get_props(px_p, dip) == DDI_FAILURE)
0N/A goto err_bad_px_prop;
0N/A
0N/A if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS)
0N/A goto err_bad_dev_init;
0N/A
350N/A /* Initialize device handle */
350N/A px_p->px_dev_hdl = dev_hdl;
350N/A
350N/A /* Cache the BDF of the root port nexus */
350N/A px_p->px_bdf = px_lib_get_bdf(px_p);
350N/A
350N/A /*
350N/A * Initialize interrupt block. Note that this
350N/A * initialize error handling for the PEC as well.
350N/A */
350N/A if ((ret = px_ib_attach(px_p)) != DDI_SUCCESS)
350N/A goto err_bad_ib;
350N/A
0N/A if (px_cb_attach(px_p) != DDI_SUCCESS)
0N/A goto err_bad_cb;
0N/A
0N/A /*
0N/A * Start creating the modules.
0N/A * Note that attach() routines should
0N/A * register and enable their own interrupts.
0N/A */
0N/A
0N/A if ((px_mmu_attach(px_p)) != DDI_SUCCESS)
0N/A goto err_bad_mmu;
0N/A
0N/A if ((px_msiq_attach(px_p)) != DDI_SUCCESS)
0N/A goto err_bad_msiq;
0N/A
0N/A if ((px_msi_attach(px_p)) != DDI_SUCCESS)
0N/A goto err_bad_msi;
0N/A
0N/A if ((px_pec_attach(px_p)) != DDI_SUCCESS)
0N/A goto err_bad_pec;
0N/A
0N/A if ((px_dma_attach(px_p)) != DDI_SUCCESS)
0N/A goto err_bad_dma; /* nothing to uninitialize on DMA */
0N/A
0N/A if ((px_fm_attach(px_p)) != DDI_SUCCESS)
0N/A goto err_bad_dma;
0N/A
0N/A /*
0N/A * All of the error handlers have been registered
350N/A * by now so it's time to activate the interrupt.
113N/A */
113N/A if ((ret = px_err_add_intr(&px_p->px_fault)) != DDI_SUCCESS)
113N/A goto err_bad_intr;
113N/A
0N/A (void) px_init_hotplug(px_p);
642N/A
642N/A (void) px_set_mps(px_p);
642N/A
642N/A /*
642N/A * Create the "devctl" node for hotplug and pcitool support.
642N/A * For non-hotplug bus, we still need ":devctl" to
642N/A * support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls.
642N/A */
325N/A if (ddi_create_minor_node(dip, "devctl", S_IFCHR,
0N/A PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR),
0N/A DDI_NT_NEXUS, 0) != DDI_SUCCESS) {
0N/A goto err_bad_devctl_node;
0N/A }
0N/A
0N/A if (pxtool_init(dip) != DDI_SUCCESS)
0N/A goto err_bad_pcitool_node;
350N/A
350N/A /*
350N/A * power management setup. Even if it fails, attach will
350N/A * succeed as this is a optional feature. Since we are
0N/A * always at full power, this is not critical.
0N/A */
0N/A if (pwr_common_setup(dip) != DDI_SUCCESS) {
0N/A DBG(DBG_PWR, dip, "pwr_common_setup failed\n");
0N/A } else if (px_pwr_setup(dip) != DDI_SUCCESS) {
0N/A DBG(DBG_PWR, dip, "px_pwr_setup failed \n");
0N/A pwr_common_teardown(dip);
389N/A }
389N/A
389N/A /*
389N/A * add cpr callback
389N/A */
389N/A px_cpr_add_callb(px_p);
0N/A
0N/A ddi_report_dev(dip);
0N/A
0N/A px_p->px_state = PX_ATTACHED;
0N/A DBG(DBG_ATTACH, dip, "attach success\n");
0N/A break;
462N/A
462N/Aerr_bad_pcitool_node:
462N/A ddi_remove_minor_node(dip, "devctl");
0N/Aerr_bad_devctl_node:
0N/A px_err_rem_intr(&px_p->px_fault);
0N/Aerr_bad_intr:
0N/A px_fm_detach(px_p);
0N/Aerr_bad_dma:
0N/A px_pec_detach(px_p);
0N/Aerr_bad_pec:
0N/A px_msi_detach(px_p);
0N/Aerr_bad_msi:
0N/A px_msiq_detach(px_p);
0N/Aerr_bad_msiq:
0N/A px_mmu_detach(px_p);
0N/Aerr_bad_mmu:
0N/A px_cb_detach(px_p);
0N/Aerr_bad_cb:
0N/A px_ib_detach(px_p);
0N/Aerr_bad_ib:
0N/A if (px_lib_dev_fini(dip) != DDI_SUCCESS) {
0N/A DBG(DBG_ATTACH, dip, "px_lib_dev_fini failed\n");
0N/A }
0N/Aerr_bad_dev_init:
0N/A px_free_props(px_p);
0N/Aerr_bad_px_prop:
0N/A px_dbg_detach(dip, &px_p->px_dbg_hdl);
0N/A mutex_destroy(&px_p->px_mutex);
0N/A ddi_soft_state_free(px_state_p, instance);
0N/Aerr_bad_px_softstate:
0N/A ret = DDI_FAILURE;
0N/A break;
0N/A
0N/A case DDI_RESUME:
0N/A DBG(DBG_ATTACH, dip, "DDI_RESUME\n");
0N/A
0N/A px_p = INST_TO_STATE(instance);
0N/A
0N/A mutex_enter(&px_p->px_mutex);
0N/A
0N/A /* suspend might have not succeeded */
0N/A if (px_p->px_state != PX_SUSPENDED) {
0N/A DBG(DBG_ATTACH, px_p->px_dip,
0N/A "instance NOT suspended\n");
0N/A ret = DDI_FAILURE;
0N/A break;
0N/A }
0N/A
0N/A px_msiq_resume(px_p);
0N/A px_lib_resume(dip);
0N/A (void) pcie_pwr_resume(dip);
0N/A px_p->px_state = PX_ATTACHED;
0N/A
0N/A mutex_exit(&px_p->px_mutex);
0N/A
0N/A break;
0N/A default:
0N/A DBG(DBG_ATTACH, dip, "unsupported attach op\n");
0N/A ret = DDI_FAILURE;
0N/A break;
0N/A }
0N/A
0N/A return (ret);
0N/A}
0N/A
0N/A/*
0N/A * detach entry point:
0N/A */
0N/A/*ARGSUSED*/
0N/Astatic int
0N/Apx_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
0N/A{
0N/A int instance = ddi_get_instance(dip);
0N/A px_t *px_p = INST_TO_STATE(instance);
0N/A int ret;
0N/A
0N/A /*
0N/A * Make sure we are currently attached
0N/A */
0N/A if (px_p->px_state != PX_ATTACHED) {
0N/A DBG(DBG_DETACH, dip, "Instance not attached\n");
0N/A return (DDI_FAILURE);
0N/A }
0N/A
0N/A mutex_enter(&px_p->px_mutex);
0N/A
0N/A switch (cmd) {
0N/A case DDI_DETACH:
0N/A DBG(DBG_DETACH, dip, "DDI_DETACH\n");
0N/A
0N/A /*
0N/A * remove cpr callback
0N/A */
0N/A px_cpr_rem_callb(px_p);
0N/A
0N/A if (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)
0N/A if (px_uninit_hotplug(dip) != DDI_SUCCESS) {
0N/A mutex_exit(&px_p->px_mutex);
0N/A return (DDI_FAILURE);
0N/A }
0N/A
0N/A /*
0N/A * things which used to be done in obj_destroy
0N/A * are now in-lined here.
0N/A */
0N/A
0N/A px_p->px_state = PX_DETACHED;
0N/A
0N/A pxtool_uninit(dip);
0N/A
0N/A ddi_remove_minor_node(dip, "devctl");
0N/A px_err_rem_intr(&px_p->px_fault);
0N/A px_fm_detach(px_p);
0N/A px_pec_detach(px_p);
0N/A px_pwr_teardown(dip);
0N/A pwr_common_teardown(dip);
0N/A px_msi_detach(px_p);
0N/A px_msiq_detach(px_p);
0N/A px_mmu_detach(px_p);
0N/A px_cb_detach(px_p);
0N/A px_ib_detach(px_p);
0N/A if (px_lib_dev_fini(dip) != DDI_SUCCESS) {
0N/A DBG(DBG_DETACH, dip, "px_lib_dev_fini failed\n");
0N/A }
0N/A
0N/A /*
0N/A * Free the px soft state structure and the rest of the
0N/A * resources it's using.
0N/A */
0N/A px_free_props(px_p);
0N/A px_dbg_detach(dip, &px_p->px_dbg_hdl);
0N/A mutex_exit(&px_p->px_mutex);
0N/A mutex_destroy(&px_p->px_mutex);
0N/A
0N/A /* Free the interrupt-priorities prop if we created it. */
0N/A {
0N/A int len;
0N/A
0N/A if (ddi_getproplen(DDI_DEV_T_ANY, dip,
0N/A DDI_PROP_NOTPROM | DDI_PROP_DONTPASS,
0N/A "interrupt-priorities", &len) == DDI_PROP_SUCCESS)
0N/A (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
0N/A "interrupt-priorities");
0N/A }
0N/A
681N/A px_p->px_dev_hdl = NULL;
681N/A ddi_soft_state_free(px_state_p, instance);
681N/A
681N/A return (DDI_SUCCESS);
169N/A
169N/A case DDI_SUSPEND:
681N/A if (pcie_pwr_suspend(dip) != DDI_SUCCESS) {
681N/A mutex_exit(&px_p->px_mutex);
681N/A return (DDI_FAILURE);
0N/A }
0N/A if ((ret = px_lib_suspend(dip)) == DDI_SUCCESS)
0N/A px_p->px_state = PX_SUSPENDED;
0N/A mutex_exit(&px_p->px_mutex);
0N/A
0N/A return (ret);
434N/A
0N/A default:
0N/A DBG(DBG_DETACH, dip, "unsupported detach op\n");
0N/A mutex_exit(&px_p->px_mutex);
0N/A return (DDI_FAILURE);
0N/A }
0N/A}
0N/A
0N/Aint
0N/Apx_cb_attach(px_t *px_p)
0N/A{
0N/A px_fault_t *fault_p = &px_p->px_cb_fault;
0N/A dev_info_t *dip = px_p->px_dip;
0N/A sysino_t sysino;
0N/A
0N/A if (px_lib_intr_devino_to_sysino(dip,
0N/A px_p->px_inos[PX_INTR_XBC], &sysino) != DDI_SUCCESS)
0N/A return (DDI_FAILURE);
0N/A
0N/A fault_p->px_fh_dip = dip;
0N/A fault_p->px_fh_sysino = sysino;
0N/A fault_p->px_err_func = px_err_cb_intr;
0N/A fault_p->px_intr_ino = px_p->px_inos[PX_INTR_XBC];
0N/A
0N/A return (px_cb_add_intr(fault_p));
0N/A}
0N/A
0N/Avoid
0N/Apx_cb_detach(px_t *px_p)
0N/A{
0N/A px_cb_rem_intr(&px_p->px_cb_fault);
0N/A}
0N/A
0N/A/*
0N/A * power management related initialization specific to px
0N/A * called by px_attach()
0N/A */
0N/Astatic int
0N/Apx_pwr_setup(dev_info_t *dip)
0N/A{
0N/A pcie_pwr_t *pwr_p;
0N/A int instance = ddi_get_instance(dip);
0N/A px_t *px_p = INST_TO_STATE(instance);
0N/A ddi_intr_handle_impl_t hdl;
0N/A
0N/A ASSERT(PCIE_PMINFO(dip));
0N/A pwr_p = PCIE_NEXUS_PMINFO(dip);
0N/A ASSERT(pwr_p);
0N/A
0N/A /*
0N/A * indicate support LDI (Layered Driver Interface)
0N/A * Create the property, if it is not already there
0N/A */
0N/A if (!ddi_prop_exists(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS,
0N/A DDI_KERNEL_IOCTL)) {
0N/A if (ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP,
0N/A DDI_KERNEL_IOCTL, NULL, 0) != DDI_PROP_SUCCESS) {
0N/A DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n");
0N/A return (DDI_FAILURE);
0N/A }
0N/A }
0N/A /* No support for device PM. We are always at full power */
0N/A pwr_p->pwr_func_lvl = PM_LEVEL_D0;
0N/A
0N/A mutex_init(&px_p->px_l23ready_lock, NULL, MUTEX_DRIVER,
0N/A DDI_INTR_PRI(px_pwr_pil));
0N/A cv_init(&px_p->px_l23ready_cv, NULL, CV_DRIVER, NULL);
0N/A
0N/A /* Initialize handle */
0N/A bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
0N/A hdl.ih_cb_arg1 = px_p;
0N/A hdl.ih_ver = DDI_INTR_VERSION;
0N/A hdl.ih_state = DDI_IHDL_STATE_ALLOC;
0N/A hdl.ih_dip = dip;
0N/A hdl.ih_pri = px_pwr_pil;
0N/A
0N/A /* Add PME_TO_ACK message handler */
0N/A hdl.ih_cb_func = (ddi_intr_handler_t *)px_pmeq_intr;
0N/A if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC,
0N/A (msgcode_t)PCIE_PME_ACK_MSG, -1,
0N/A &px_p->px_pm_msiq_id) != DDI_SUCCESS) {
0N/A DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add "
0N/A " PME_TO_ACK intr\n");
0N/A goto pwr_setup_err1;
0N/A }
0N/A px_lib_msg_setmsiq(dip, PCIE_PME_ACK_MSG, px_p->px_pm_msiq_id);
0N/A px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_VALID);
0N/A
0N/A if (px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
0N/A px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), px_pwr_pil,
0N/A PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) {
0N/A DBG(DBG_PWR, dip, "px_pwr_setup: PME_TO_ACK update interrupt"
0N/A " state failed\n");
0N/A goto px_pwrsetup_err_state;
0N/A }
0N/A
0N/A return (DDI_SUCCESS);
0N/A
0N/Apx_pwrsetup_err_state:
0N/A px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID);
0N/A (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,
0N/A px_p->px_pm_msiq_id);
0N/Apwr_setup_err1:
0N/A mutex_destroy(&px_p->px_l23ready_lock);
0N/A cv_destroy(&px_p->px_l23ready_cv);
0N/A
0N/A return (DDI_FAILURE);
0N/A}
0N/A
0N/A/*
0N/A * undo whatever is done in px_pwr_setup. called by px_detach()
0N/A */
0N/Astatic void
0N/Apx_pwr_teardown(dev_info_t *dip)
0N/A{
0N/A int instance = ddi_get_instance(dip);
0N/A px_t *px_p = INST_TO_STATE(instance);
0N/A ddi_intr_handle_impl_t hdl;
0N/A
0N/A if (!PCIE_PMINFO(dip) || !PCIE_NEXUS_PMINFO(dip))
263N/A return;
0N/A
0N/A /* Initialize handle */
263N/A bzero(&hdl, sizeof (ddi_intr_handle_impl_t));
263N/A hdl.ih_ver = DDI_INTR_VERSION;
263N/A hdl.ih_state = DDI_IHDL_STATE_ALLOC;
263N/A hdl.ih_dip = dip;
263N/A hdl.ih_pri = px_pwr_pil;
263N/A
481N/A px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID);
481N/A (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,
481N/A px_p->px_pm_msiq_id);
0N/A
0N/A (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum,
0N/A px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), px_pwr_pil,
0N/A PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG);
0N/A
0N/A px_p->px_pm_msiq_id = (msiqid_t)-1;
0N/A
0N/A cv_destroy(&px_p->px_l23ready_cv);
0N/A mutex_destroy(&px_p->px_l23ready_lock);
0N/A}
0N/A
0N/A/* bus driver entry points */
0N/A
0N/A/*
0N/A * bus map entry point:
0N/A *
0N/A * if map request is for an rnumber
0N/A * get the corresponding regspec from device node
0N/A * build a new regspec in our parent's format
0N/A * build a new map_req with the new regspec
0N/A * call up the tree to complete the mapping
0N/A */
0N/Aint
0N/Apx_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
0N/A off_t off, off_t len, caddr_t *addrp)
0N/A{
0N/A px_t *px_p = DIP_TO_STATE(dip);
0N/A struct regspec p_regspec;
0N/A ddi_map_req_t p_mapreq;
0N/A int reglen, rval, r_no;
0N/A pci_regspec_t reloc_reg, *rp = &reloc_reg;
0N/A
0N/A DBG(DBG_MAP, dip, "rdip=%s%d:",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip));
615N/A
615N/A if (mp->map_flags & DDI_MF_USER_MAPPING)
615N/A return (DDI_ME_UNIMPLEMENTED);
615N/A
615N/A switch (mp->map_type) {
615N/A case DDI_MT_REGSPEC:
0N/A reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */
0N/A break;
0N/A
0N/A case DDI_MT_RNUMBER:
0N/A r_no = mp->map_obj.rnumber;
0N/A DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no);
0N/A
0N/A if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS,
0N/A "reg", (caddr_t)&rp, &reglen) != DDI_SUCCESS)
0N/A return (DDI_ME_RNUMBER_RANGE);
0N/A
0N/A if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) {
0N/A kmem_free(rp, reglen);
0N/A return (DDI_ME_RNUMBER_RANGE);
0N/A }
0N/A rp += r_no;
0N/A break;
0N/A
0N/A default:
0N/A return (DDI_ME_INVAL);
0N/A }
0N/A DBG(DBG_MAP | DBG_CONT, dip, "\n");
0N/A
0N/A if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) {
0N/A /*
0N/A * There may be a need to differentiate between PCI
0N/A * and PCI-Ex devices so the following range check is
0N/A * done correctly, depending on the implementation of
0N/A * pcieb bridge nexus driver.
0N/A */
0N/A if ((off >= PCIE_CONF_HDR_SIZE) ||
0N/A (len > PCIE_CONF_HDR_SIZE) ||
0N/A (off + len > PCIE_CONF_HDR_SIZE))
0N/A return (DDI_ME_INVAL);
0N/A /*
0N/A * the following function returning a DDI_FAILURE assumes
989N/A * that there are no virtual config space access services
989N/A * defined in this layer. Otherwise it is availed right
989N/A * here and we return.
989N/A */
989N/A rval = px_lib_map_vconfig(dip, mp, off, rp, addrp);
0N/A if (rval == DDI_SUCCESS)
0N/A goto done;
0N/A }
0N/A
0N/A /*
0N/A * No virtual config space services or we are mapping
0N/A * a region of memory mapped config/IO/memory space, so proceed
0N/A * to the parent.
0N/A */
0N/A
0N/A /* relocate within 64-bit pci space through "assigned-addresses" */
0N/A if (rval = px_reloc_reg(dip, rdip, px_p, rp))
0N/A goto done;
0N/A
0N/A if (len) /* adjust regspec according to mapping request */
100N/A rp->pci_size_low = len; /* MIN ? */
0N/A rp->pci_phys_low += off;
0N/A
100N/A /* translate relocated pci regspec into parent space through "ranges" */
100N/A if (rval = px_xlate_reg(px_p, rp, &p_regspec))
100N/A goto done;
370N/A
100N/A p_mapreq = *mp; /* dup the whole structure */
100N/A p_mapreq.map_type = DDI_MT_REGSPEC;
100N/A p_mapreq.map_obj.rp = &p_regspec;
0N/A px_lib_map_attr_check(&p_mapreq);
0N/A rval = ddi_map(dip, &p_mapreq, 0, 0, addrp);
100N/A
0N/A if (rval == DDI_SUCCESS) {
0N/A /*
0N/A * Set-up access functions for FM access error capable drivers.
0N/A */
0N/A if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip)))
0N/A px_fm_acc_setup(mp, rdip, rp);
0N/A }
0N/A
0N/Adone:
0N/A if (mp->map_type == DDI_MT_RNUMBER)
0N/A kmem_free(rp - r_no, reglen);
0N/A
0N/A return (rval);
0N/A}
0N/A
0N/A/*
0N/A * bus dma map entry point
0N/A * return value:
0N/A * DDI_DMA_PARTIAL_MAP 1
0N/A * DDI_DMA_MAPOK 0
0N/A * DDI_DMA_MAPPED 0
0N/A * DDI_DMA_NORESOURCES -1
0N/A * DDI_DMA_NOMAPPING -2
0N/A * DDI_DMA_TOOBIG -3
100N/A */
0N/Aint
0N/Apx_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq,
0N/A ddi_dma_handle_t *handlep)
0N/A{
0N/A px_t *px_p = DIP_TO_STATE(dip);
0N/A px_mmu_t *mmu_p = px_p->px_mmu_p;
0N/A ddi_dma_impl_t *mp;
0N/A int ret;
0N/A
0N/A DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip),
0N/A handlep ? "alloc" : "advisory");
0N/A
0N/A if (!(mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq)))
1064N/A return (DDI_DMA_NORESOURCES);
0N/A if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING)
0N/A return (DDI_DMA_NOMAPPING);
0N/A if (ret = px_dma_type(px_p, dmareq, mp))
0N/A goto freehandle;
0N/A if (ret = px_dma_pfn(px_p, dmareq, mp))
0N/A goto freehandle;
0N/A
0N/A switch (PX_DMA_TYPE(mp)) {
0N/A case PX_DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */
0N/A if ((ret = px_dvma_win(px_p, dmareq, mp)) || !handlep)
0N/A goto freehandle;
0N/A if (!PX_DMA_CANCACHE(mp)) { /* try fast track */
0N/A if (PX_DMA_CANFAST(mp)) {
0N/A if (!px_dvma_map_fast(mmu_p, mp))
0N/A break;
0N/A /* LINTED E_NOP_ELSE_STMT */
0N/A } else {
0N/A PX_DVMA_FASTTRAK_PROF(mp);
0N/A }
0N/A }
0N/A if (ret = px_dvma_map(mp, dmareq, mmu_p))
0N/A goto freehandle;
0N/A break;
0N/A case PX_DMAI_FLAGS_PTP: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */
0N/A if ((ret = px_dma_physwin(px_p, dmareq, mp)) || !handlep)
0N/A goto freehandle;
0N/A break;
0N/A case PX_DMAI_FLAGS_BYPASS:
0N/A default:
1064N/A cmn_err(CE_PANIC, "%s%d: px_dma_setup: bad dma type 0x%x",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip),
0N/A PX_DMA_TYPE(mp));
0N/A /*NOTREACHED*/
0N/A }
0N/A *handlep = (ddi_dma_handle_t)mp;
0N/A mp->dmai_flags |= PX_DMAI_FLAGS_INUSE;
0N/A px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
0N/A
0N/A return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
0N/Afreehandle:
0N/A if (ret == DDI_DMA_NORESOURCES)
0N/A px_dma_freemp(mp); /* don't run_callback() */
0N/A else
0N/A (void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
0N/A return (ret);
0N/A}
0N/A
0N/A
0N/A/*
0N/A * bus dma alloc handle entry point:
0N/A */
0N/Aint
0N/Apx_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp,
0N/A int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep)
0N/A{
474N/A px_t *px_p = DIP_TO_STATE(dip);
132N/A ddi_dma_impl_t *mp;
132N/A int rval;
0N/A
0N/A DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip));
0N/A
0N/A if (attrp->dma_attr_version != DMA_ATTR_V0)
0N/A return (DDI_DMA_BADATTR);
0N/A
0N/A if (!(mp = px_dma_allocmp(dip, rdip, waitfp, arg)))
0N/A return (DDI_DMA_NORESOURCES);
0N/A
0N/A /*
514N/A * Save requestor's information
514N/A */
514N/A mp->dmai_attr = *attrp; /* whole object - augmented later */
514N/A *PX_DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */
514N/A DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp);
514N/A
514N/A /* check and convert dma attributes to handle parameters */
1064N/A if (rval = px_dma_attr2hdl(px_p, mp)) {
514N/A px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
514N/A *handlep = NULL;
514N/A return (rval);
1064N/A }
514N/A *handlep = (ddi_dma_handle_t)mp;
514N/A return (DDI_SUCCESS);
1064N/A}
0N/A
0N/A
0N/A/*
0N/A * bus dma free handle entry point:
0N/A */
0N/A/*ARGSUSED*/
0N/Aint
0N/Apx_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
0N/A{
0N/A DBG(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip), handle);
0N/A px_dma_freemp((ddi_dma_impl_t *)handle);
0N/A
0N/A if (px_kmem_clid) {
0N/A DBG(DBG_DMA_FREEH, dip, "run handle callback\n");
0N/A ddi_run_callback(&px_kmem_clid);
0N/A }
0N/A return (DDI_SUCCESS);
0N/A}
0N/A
0N/A
0N/A/*
0N/A * bus dma bind handle entry point:
370N/A */
0N/Aint
0N/Apx_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
0N/A ddi_dma_handle_t handle, ddi_dma_req_t *dmareq,
0N/A ddi_dma_cookie_t *cookiep, uint_t *ccountp)
0N/A{
0N/A px_t *px_p = DIP_TO_STATE(dip);
0N/A px_mmu_t *mmu_p = px_p->px_mmu_p;
0N/A ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
0N/A int ret;
0N/A
0N/A DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq);
0N/A
0N/A if (mp->dmai_flags & PX_DMAI_FLAGS_INUSE)
0N/A return (DDI_DMA_INUSE);
0N/A
0N/A ASSERT((mp->dmai_flags & ~PX_DMAI_FLAGS_PRESERVE) == 0);
0N/A mp->dmai_flags |= PX_DMAI_FLAGS_INUSE;
0N/A
0N/A if (ret = px_dma_type(px_p, dmareq, mp))
0N/A goto err;
0N/A if (ret = px_dma_pfn(px_p, dmareq, mp))
0N/A goto err;
0N/A
0N/A switch (PX_DMA_TYPE(mp)) {
0N/A case PX_DMAI_FLAGS_DVMA:
0N/A if (ret = px_dvma_win(px_p, dmareq, mp))
1064N/A goto map_err;
1064N/A if (!PX_DMA_CANCACHE(mp)) { /* try fast track */
1064N/A if (PX_DMA_CANFAST(mp)) {
0N/A if (!px_dvma_map_fast(mmu_p, mp))
0N/A goto mapped; /*LINTED E_NOP_ELSE_STMT*/
0N/A } else {
0N/A PX_DVMA_FASTTRAK_PROF(mp);
0N/A }
0N/A }
0N/A if (ret = px_dvma_map(mp, dmareq, mmu_p))
0N/A goto map_err;
0N/Amapped:
0N/A *ccountp = 1;
0N/A MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size);
0N/A break;
0N/A case PX_DMAI_FLAGS_BYPASS:
0N/A case PX_DMAI_FLAGS_PTP:
0N/A if (ret = px_dma_physwin(px_p, dmareq, mp))
0N/A goto map_err;
0N/A *ccountp = PX_WINLST(mp)->win_ncookies;
0N/A *cookiep =
0N/A *(ddi_dma_cookie_t *)(PX_WINLST(mp) + 1); /* wholeobj */
0N/A break;
0N/A default:
0N/A cmn_err(CE_PANIC, "%s%d: px_dma_bindhdl(%p): bad dma type",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
0N/A /*NOTREACHED*/
0N/A }
0N/A DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x\n",
0N/A cookiep->dmac_address, cookiep->dmac_size);
0N/A px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
0N/A
0N/A /* insert dma handle into FMA cache */
0N/A if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) {
0N/A (void) ndi_fmc_insert(rdip, DMA_HANDLE, mp, NULL);
0N/A mp->dmai_error.err_cf = px_err_dma_hdl_check;
0N/A }
0N/A
0N/A return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
0N/Amap_err:
0N/A px_dma_freepfn(mp);
0N/Aerr:
0N/A mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE;
0N/A return (ret);
0N/A}
0N/A
0N/A
0N/A/*
0N/A * bus dma unbind handle entry point:
0N/A */
0N/A/*ARGSUSED*/
0N/Aint
1064N/Apx_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
0N/A{
0N/A ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
0N/A px_t *px_p = DIP_TO_STATE(dip);
0N/A px_mmu_t *mmu_p = px_p->px_mmu_p;
0N/A
0N/A DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip), handle);
0N/A if ((mp->dmai_flags & PX_DMAI_FLAGS_INUSE) == 0) {
0N/A DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n");
0N/A return (DDI_FAILURE);
0N/A }
0N/A
0N/A /* remove dma handle from FMA cache */
0N/A if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) {
0N/A if (DEVI(rdip)->devi_fmhdl != NULL &&
0N/A DDI_FM_DMA_ERR_CAP(DEVI(rdip)->devi_fmhdl->fh_cap)) {
0N/A (void) ndi_fmc_remove(rdip, DMA_HANDLE, mp);
0N/A }
0N/A }
0N/A
0N/A /*
0N/A * Here if the handle is using the iommu. Unload all the iommu
0N/A * translations.
0N/A */
0N/A switch (PX_DMA_TYPE(mp)) {
0N/A case PX_DMAI_FLAGS_DVMA:
0N/A px_mmu_unmap_window(mmu_p, mp);
0N/A px_dvma_unmap(mmu_p, mp);
0N/A px_dma_freepfn(mp);
0N/A break;
0N/A case PX_DMAI_FLAGS_BYPASS:
0N/A case PX_DMAI_FLAGS_PTP:
0N/A px_dma_freewin(mp);
0N/A break;
0N/A default:
0N/A cmn_err(CE_PANIC, "%s%d: px_dma_unbindhdl:bad dma type %p",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
0N/A /*NOTREACHED*/
0N/A }
0N/A if (mmu_p->mmu_dvma_clid != 0) {
0N/A DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n");
219N/A ddi_run_callback(&mmu_p->mmu_dvma_clid);
219N/A }
219N/A if (px_kmem_clid) {
0N/A DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n");
0N/A ddi_run_callback(&px_kmem_clid);
0N/A }
0N/A mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE;
0N/A
0N/A return (DDI_SUCCESS);
0N/A}
0N/A
0N/A/*
0N/A * bus dma win entry point:
0N/A */
0N/Aint
71N/Apx_dma_win(dev_info_t *dip, dev_info_t *rdip,
71N/A ddi_dma_handle_t handle, uint_t win, off_t *offp,
71N/A size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp)
71N/A{
71N/A ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
71N/A int ret;
405N/A
405N/A DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n",
405N/A ddi_driver_name(rdip), ddi_get_instance(rdip));
405N/A
405N/A px_dump_dma_handle(DBG_DMA_WIN, dip, mp);
405N/A if (win >= mp->dmai_nwin) {
0N/A DBG(DBG_DMA_WIN, dip, "%x out of range\n", win);
0N/A return (DDI_FAILURE);
0N/A }
0N/A
0N/A switch (PX_DMA_TYPE(mp)) {
0N/A case PX_DMAI_FLAGS_DVMA:
0N/A if (win != PX_DMA_CURWIN(mp)) {
0N/A px_t *px_p = DIP_TO_STATE(dip);
0N/A px_mmu_t *mmu_p = px_p->px_mmu_p;
0N/A px_mmu_unmap_window(mmu_p, mp);
0N/A
0N/A /* map_window sets dmai_mapping/size/offset */
0N/A px_mmu_map_window(mmu_p, mp, win);
0N/A if ((ret = px_mmu_map_window(mmu_p,
0N/A mp, win)) != DDI_SUCCESS)
0N/A return (ret);
0N/A }
0N/A if (cookiep)
0N/A MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping,
0N/A mp->dmai_size);
0N/A if (ccountp)
0N/A *ccountp = 1;
0N/A break;
0N/A case PX_DMAI_FLAGS_PTP:
0N/A case PX_DMAI_FLAGS_BYPASS: {
0N/A int i;
0N/A ddi_dma_cookie_t *ck_p;
0N/A px_dma_win_t *win_p = mp->dmai_winlst;
0N/A
0N/A for (i = 0; i < win; win_p = win_p->win_next, i++) {};
0N/A ck_p = (ddi_dma_cookie_t *)(win_p + 1);
0N/A *cookiep = *ck_p;
0N/A mp->dmai_offset = win_p->win_offset;
0N/A mp->dmai_size = win_p->win_size;
0N/A mp->dmai_mapping = ck_p->dmac_laddress;
0N/A mp->dmai_cookie = ck_p + 1;
0N/A win_p->win_curseg = 0;
0N/A if (ccountp)
0N/A *ccountp = win_p->win_ncookies;
0N/A }
0N/A break;
370N/A default:
0N/A cmn_err(CE_WARN, "%s%d: px_dma_win:bad dma type 0x%x",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip),
880N/A PX_DMA_TYPE(mp));
880N/A return (DDI_FAILURE);
880N/A }
0N/A if (cookiep)
0N/A DBG(DBG_DMA_WIN, dip,
0N/A "cookie - dmac_address=%x dmac_size=%x\n",
0N/A cookiep->dmac_address, cookiep->dmac_size);
0N/A if (offp)
0N/A *offp = (off_t)mp->dmai_offset;
0N/A if (lenp)
0N/A *lenp = mp->dmai_size;
0N/A return (DDI_SUCCESS);
0N/A}
0N/A
0N/A#ifdef DEBUG
0N/Astatic char *px_dmactl_str[] = {
0N/A "DDI_DMA_FREE",
0N/A "DDI_DMA_SYNC",
0N/A "DDI_DMA_HTOC",
0N/A "DDI_DMA_KVADDR",
0N/A "DDI_DMA_MOVWIN",
0N/A "DDI_DMA_REPWIN",
0N/A "DDI_DMA_GETERR",
0N/A "DDI_DMA_COFF",
0N/A "DDI_DMA_NEXTWIN",
0N/A "DDI_DMA_NEXTSEG",
0N/A "DDI_DMA_SEGTOC",
0N/A "DDI_DMA_RESERVE",
0N/A "DDI_DMA_RELEASE",
0N/A "DDI_DMA_RESETH",
0N/A "DDI_DMA_CKSYNC",
0N/A "DDI_DMA_IOPB_ALLOC",
0N/A "DDI_DMA_IOPB_FREE",
0N/A "DDI_DMA_SMEM_ALLOC",
0N/A "DDI_DMA_SMEM_FREE",
0N/A "DDI_DMA_SET_SBUS64"
0N/A};
0N/A#endif /* DEBUG */
0N/A
0N/A/*
0N/A * bus dma control entry point:
0N/A */
0N/A/*ARGSUSED*/
0N/Aint
0N/Apx_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
0N/A enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
0N/A uint_t cache_flags)
0N/A{
0N/A ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
0N/A
0N/A#ifdef DEBUG
0N/A DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd],
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip));
0N/A#endif /* DEBUG */
0N/A
0N/A switch (cmd) {
0N/A case DDI_DMA_FREE:
0N/A (void) px_dma_unbindhdl(dip, rdip, handle);
0N/A (void) px_dma_freehdl(dip, rdip, handle);
0N/A return (DDI_SUCCESS);
0N/A case DDI_DMA_RESERVE: {
0N/A px_t *px_p = DIP_TO_STATE(dip);
0N/A return (px_fdvma_reserve(dip, rdip, px_p,
0N/A (ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp));
0N/A }
0N/A case DDI_DMA_RELEASE: {
0N/A px_t *px_p = DIP_TO_STATE(dip);
0N/A return (px_fdvma_release(dip, px_p, mp));
0N/A }
0N/A default:
0N/A break;
0N/A }
0N/A
0N/A switch (PX_DMA_TYPE(mp)) {
0N/A case PX_DMAI_FLAGS_DVMA:
0N/A return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
0N/A cache_flags));
0N/A case PX_DMAI_FLAGS_PTP:
0N/A case PX_DMAI_FLAGS_BYPASS:
0N/A return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
0N/A cache_flags));
0N/A default:
0N/A cmn_err(CE_PANIC, "%s%d: px_dma_ctlops(%x):bad dma type %x",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip), cmd,
0N/A mp->dmai_flags);
0N/A /*NOTREACHED*/
0N/A }
0N/A return (0);
0N/A}
0N/A
0N/A/*
0N/A * control ops entry point:
0N/A *
0N/A * Requests handled completely:
0N/A * DDI_CTLOPS_INITCHILD see init_child() for details
0N/A * DDI_CTLOPS_UNINITCHILD
0N/A * DDI_CTLOPS_REPORTDEV see report_dev() for details
0N/A * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1
0N/A * DDI_CTLOPS_REGSIZE
0N/A * DDI_CTLOPS_NREGS
0N/A * DDI_CTLOPS_DVMAPAGESIZE
0N/A * DDI_CTLOPS_POKE
0N/A * DDI_CTLOPS_PEEK
0N/A *
0N/A * All others passed to parent.
0N/A */
0N/Aint
342N/Apx_ctlops(dev_info_t *dip, dev_info_t *rdip,
342N/A ddi_ctl_enum_t op, void *arg, void *result)
350N/A{
342N/A px_t *px_p = DIP_TO_STATE(dip);
0N/A struct detachspec *ds;
0N/A struct attachspec *as;
0N/A
0N/A switch (op) {
0N/A case DDI_CTLOPS_INITCHILD:
0N/A return (px_init_child(px_p, (dev_info_t *)arg));
0N/A
0N/A case DDI_CTLOPS_UNINITCHILD:
0N/A return (px_uninit_child(px_p, (dev_info_t *)arg));
0N/A
0N/A case DDI_CTLOPS_ATTACH:
0N/A if (!pcie_is_child(dip, rdip))
0N/A return (DDI_SUCCESS);
0N/A
0N/A as = (struct attachspec *)arg;
0N/A switch (as->when) {
0N/A case DDI_PRE:
0N/A if (as->cmd == DDI_ATTACH) {
0N/A DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n",
0N/A ddi_driver_name(rdip),
0N/A ddi_get_instance(rdip));
0N/A return (pcie_pm_hold(dip));
0N/A }
0N/A if (as->cmd == DDI_RESUME) {
0N/A DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n",
0N/A ddi_driver_name(rdip),
0N/A ddi_get_instance(rdip));
0N/A
0N/A pcie_clear_errors(rdip);
0N/A }
0N/A return (DDI_SUCCESS);
0N/A
0N/A case DDI_POST:
0N/A DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip));
0N/A if (as->cmd == DDI_ATTACH &&
0N/A as->result != DDI_SUCCESS) {
0N/A /*
0N/A * Attach failed for the child device. The child
0N/A * driver may have made PM calls before the
0N/A * attach failed. pcie_pm_remove_child() should
0N/A * cleanup PM state and holds (if any)
483N/A * associated with the child device.
483N/A */
483N/A return (pcie_pm_remove_child(dip, rdip));
483N/A }
483N/A
483N/A if (as->result == DDI_SUCCESS)
0N/A pf_init(rdip, (void *)px_p->px_fm_ibc, as->cmd);
375N/A
375N/A (void) pcie_postattach_child(rdip);
0N/A
342N/A return (DDI_SUCCESS);
342N/A default:
342N/A break;
0N/A }
0N/A break;
0N/A
0N/A case DDI_CTLOPS_DETACH:
0N/A if (!pcie_is_child(dip, rdip))
0N/A return (DDI_SUCCESS);
0N/A
0N/A ds = (struct detachspec *)arg;
0N/A switch (ds->when) {
0N/A case DDI_POST:
0N/A if (ds->cmd == DDI_DETACH &&
0N/A ds->result == DDI_SUCCESS) {
0N/A DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n",
1064N/A ddi_driver_name(rdip),
1064N/A ddi_get_instance(rdip));
0N/A return (pcie_pm_remove_child(dip, rdip));
0N/A }
1064N/A return (DDI_SUCCESS);
1064N/A case DDI_PRE:
0N/A pf_fini(rdip, ds->cmd);
0N/A return (DDI_SUCCESS);
0N/A default:
0N/A break;
0N/A }
0N/A break;
0N/A
0N/A case DDI_CTLOPS_REPORTDEV:
0N/A return (px_report_dev(rdip));
0N/A
0N/A case DDI_CTLOPS_IOMIN:
0N/A return (DDI_SUCCESS);
1064N/A
1064N/A case DDI_CTLOPS_REGSIZE:
1064N/A *((off_t *)result) = px_get_reg_set_size(rdip, *((int *)arg));
0N/A return (*((off_t *)result) == 0 ? DDI_FAILURE : DDI_SUCCESS);
0N/A
0N/A case DDI_CTLOPS_NREGS:
0N/A *((uint_t *)result) = px_get_nreg_set(rdip);
0N/A return (DDI_SUCCESS);
0N/A
0N/A case DDI_CTLOPS_DVMAPAGESIZE:
0N/A *((ulong_t *)result) = MMU_PAGE_SIZE;
0N/A return (DDI_SUCCESS);
0N/A
0N/A case DDI_CTLOPS_POKE: /* platform dependent implementation. */
0N/A return (px_lib_ctlops_poke(dip, rdip,
0N/A (peekpoke_ctlops_t *)arg));
0N/A
0N/A case DDI_CTLOPS_PEEK: /* platform dependent implementation. */
0N/A return (px_lib_ctlops_peek(dip, rdip,
0N/A (peekpoke_ctlops_t *)arg, result));
0N/A
0N/A case DDI_CTLOPS_POWER:
0N/A default:
0N/A break;
0N/A }
0N/A
0N/A /*
0N/A * Now pass the request up to our parent.
0N/A */
0N/A DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip));
0N/A return (ddi_ctlops(dip, rdip, op, arg, result));
0N/A}
0N/A
0N/A/* ARGSUSED */
0N/Aint
0N/Apx_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
0N/A ddi_intr_handle_impl_t *hdlp, void *result)
0N/A{
0N/A int intr_types, ret = DDI_SUCCESS;
0N/A
0N/A DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n",
0N/A ddi_driver_name(rdip), ddi_get_instance(rdip));
0N/A
0N/A /* Process DDI_INTROP_SUPPORTED_TYPES request here */
0N/A if (intr_op == DDI_INTROP_SUPPORTED_TYPES) {
0N/A *(int *)result = i_ddi_get_intx_nintrs(rdip) ?
695N/A DDI_INTR_TYPE_FIXED : 0;
695N/A
695N/A if ((pci_msi_get_supported_type(rdip,
679N/A &intr_types)) == DDI_SUCCESS) {
695N/A /*
679N/A * Double check supported interrupt types vs.
534N/A * what the host bridge supports.
534N/A */
534N/A *(int *)result |= intr_types;
534N/A }
1064N/A
1064N/A return (ret);
534N/A }
534N/A
0N/A /*
0N/A * PCI-E nexus driver supports fixed, MSI and MSI-X interrupts.
1145N/A * Return failure if interrupt type is not supported.
0N/A */
0N/A switch (hdlp->ih_type) {
0N/A case DDI_INTR_TYPE_FIXED:
1145N/A ret = px_intx_ops(dip, rdip, intr_op, hdlp, result);
1145N/A break;
1145N/A case DDI_INTR_TYPE_MSI:
1145N/A case DDI_INTR_TYPE_MSIX:
1145N/A ret = px_msix_ops(dip, rdip, intr_op, hdlp, result);
1145N/A break;
1145N/A default:
1145N/A ret = DDI_ENOTSUP;
1145N/A break;
1145N/A }
1145N/A
1145N/A return (ret);
1145N/A}
1145N/A
1145N/Astatic int
1145N/Apx_init_hotplug(px_t *px_p)
1145N/A{
1145N/A px_bus_range_t bus_range;
1145N/A dev_info_t *dip;
1145N/A pciehpc_regops_t regops;
1145N/A
1145N/A dip = px_p->px_dip;
1145N/A
1145N/A if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1145N/A "hotplug-capable") == 0)
1145N/A return (DDI_FAILURE);
1145N/A
1145N/A /*
1145N/A * Before initializing hotplug - open up bus range. The busra
1145N/A * module will initialize its pool of bus numbers from this.
1145N/A * "busra" will be the agent that keeps track of them during
1145N/A * hotplug. Also, note, that busra will remove any bus numbers
1145N/A * already in use from boot time.
1145N/A */
1145N/A if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1145N/A "bus-range") == 0) {
0N/A cmn_err(CE_WARN, "%s%d: bus-range not found\n",
0N/A ddi_driver_name(dip), ddi_get_instance(dip));
0N/A#ifdef DEBUG
0N/A bus_range.lo = 0x0;
1064N/A bus_range.hi = 0xff;
1064N/A
0N/A if (ndi_prop_update_int_array(DDI_DEV_T_NONE,
0N/A dip, "bus-range", (int *)&bus_range, 2)
0N/A != DDI_PROP_SUCCESS) {
1064N/A return (DDI_FAILURE);
0N/A }
342N/A#else
342N/A return (DDI_FAILURE);
342N/A#endif
342N/A }
342N/A
342N/A if (px_lib_hotplug_init(dip, (void *)&regops) != DDI_SUCCESS)
0N/A return (DDI_FAILURE);
0N/A
0N/A if (pciehpc_init(dip, &regops) != DDI_SUCCESS) {
0N/A px_lib_hotplug_uninit(dip);
0N/A return (DDI_FAILURE);
0N/A }
0N/A
0N/A if (pcihp_init(dip) != DDI_SUCCESS) {
0N/A (void) pciehpc_uninit(dip);
0N/A px_lib_hotplug_uninit(dip);
0N/A return (DDI_FAILURE);
0N/A }
0N/A
1064N/A if (pcihp_get_cb_ops() != NULL) {
1064N/A DBG(DBG_ATTACH, dip, "%s%d hotplug enabled",
0N/A ddi_driver_name(dip), ddi_get_instance(dip));
0N/A px_p->px_dev_caps |= PX_HOTPLUG_CAPABLE;
1064N/A }
1064N/A
0N/A return (DDI_SUCCESS);
0N/A}
0N/A
1064N/Astatic int
0N/Apx_uninit_hotplug(dev_info_t *dip)
1145N/A{
1145N/A if (pcihp_uninit(dip) != DDI_SUCCESS)
1145N/A return (DDI_FAILURE);
1145N/A
1145N/A if (pciehpc_uninit(dip) != DDI_SUCCESS)
1145N/A return (DDI_FAILURE);
1145N/A
1145N/A px_lib_hotplug_uninit(dip);
1145N/A
1145N/A return (DDI_SUCCESS);
0N/A}
0N/A
0N/Astatic void
0N/Apx_set_mps(px_t *px_p)
0N/A{
1145N/A dev_info_t *dip;
1145N/A pcie_bus_t *bus_p;
1145N/A int max_supported;
1145N/A
1145N/A dip = px_p->px_dip;
1145N/A bus_p = PCIE_DIP2BUS(dip);
1145N/A
1145N/A bus_p->bus_mps = -1;
1145N/A
1145N/A if (pcie_root_port(dip) == DDI_FAILURE) {
1145N/A if (px_lib_get_root_complex_mps(px_p, dip,
1145N/A &max_supported) < 0) {
1145N/A
1145N/A DBG(DBG_MPS, dip, "MPS: Can not get RC MPS\n");
1145N/A return;
1145N/A }
1145N/A
1145N/A DBG(DBG_MPS, dip, "MPS: Root Complex MPS Cap of = %x\n",
1145N/A max_supported);
1145N/A
1145N/A if (pcie_max_mps < max_supported)
1145N/A max_supported = pcie_max_mps;
1145N/A
1145N/A (void) pcie_get_fabric_mps(dip, ddi_get_child(dip),
1145N/A &max_supported);
1145N/A
1145N/A bus_p->bus_mps = max_supported;
1145N/A
1064N/A (void) px_lib_set_root_complex_mps(px_p, dip, bus_p->bus_mps);
1064N/A
1064N/A DBG(DBG_MPS, dip, "MPS: Root Complex MPS Set to = %x\n",
0N/A bus_p->bus_mps);
1145N/A }
1064N/A}
0N/A