px.c revision 4fbb58f6b7ca6192a6857d169ee41c3e09dab64a
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* PCI Express nexus driver interface
*/
#include <sys/ddi_impldefs.h>
#include <sys/ddi_subrdefs.h>
#include <sys/iommutsb.h>
#include "px_obj.h"
#include <sys/pci_tools.h>
#include "px_tools.h"
#include "pcie_pwr.h"
/*LINTLIBRARY*/
/*
* function prototypes for dev ops routines:
*/
/*
* bus ops and dev ops structures:
*/
static struct bus_ops px_bus_ops = {
0,
0,
0,
NULL,
NULL, /* (*bus_config)(); */
NULL, /* (*bus_unconfig)(); */
px_fm_init_child, /* (*bus_fm_init)(); */
NULL, /* (*bus_fm_fini)(); */
px_bus_enter, /* (*bus_fm_access_enter)(); */
px_bus_exit, /* (*bus_fm_access_fini)(); */
pcie_bus_power, /* (*bus_power)(); */
px_intr_ops /* (*bus_intr_op)(); */
};
0,
0,
};
/*
* module definitions:
*/
extern struct mod_ops mod_driverops;
&mod_driverops, /* Type of module - driver */
"PCI Express nexus driver %I%", /* Name of module. */
&px_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
};
/* driver soft state */
void *px_state_p;
int
_init(void)
{
int e;
/*
* Initialize per-px bus soft state pointer.
*/
if (e != DDI_SUCCESS)
return (e);
/*
* Install the module.
*/
e = mod_install(&modlinkage);
if (e != DDI_SUCCESS)
return (e);
}
int
_fini(void)
{
int e;
/*
* Remove the module.
*/
e = mod_remove(&modlinkage);
if (e != DDI_SUCCESS)
return (e);
/* Free px soft state */
return (e);
}
int
{
}
/* ARGSUSED */
static int
{
#ifdef HOTPLUG
/*
* Allow hotplug to deal with ones it manages
* Hot Plug will be done later.
*/
#endif /* HOTPLUG */
/* non-hotplug or not attached */
switch (infocmd) {
case DDI_INFO_DEVT2INSTANCE:
return (DDI_SUCCESS);
case DDI_INFO_DEVT2DEVINFO:
return (DDI_FAILURE);
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
}
}
/* device driver entry points */
/*
* attach entry point:
*/
/*ARGSUSED*/
static int
{
int ret = DDI_SUCCESS;
switch (cmd) {
case DDI_ATTACH:
/*
* Allocate and get the per-px soft state structure.
*/
!= DDI_SUCCESS) {
goto err_bad_px_softstate;
}
px_p->px_open_count = 0;
/*
* Get key properties of the pci bridge node and
* determine it's type (psycho, schizo, etc ...).
*/
goto err_bad_px_prop;
goto err_bad_fm;
goto err_bad_dev_init;
/* Initilize device handle */
/*
* Initialize interrupt block. Note that this
* initialize error handling for the PEC as well.
*/
goto err_bad_ib;
goto err_bad_cb;
/*
* Start creating the modules.
* Note that attach() routines should
* register and enable their own interrupts.
*/
goto err_bad_mmu;
goto err_bad_msiq;
goto err_bad_msi;
goto err_bad_pec;
goto err_bad_pec; /* nothing to uninitialize on DMA */
/*
* All of the error handlers have been registered
* by now so it's time to activate the interrupt.
*/
goto err_bad_pec_add_intr;
/*
* Create the "devctl" node for hotplug and pcitool support.
* For non-hotplug bus, we still need ":devctl" to
* support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls.
*/
DDI_NT_NEXUS, 0) != DDI_SUCCESS) {
goto err_bad_devctl_node;
}
goto err_bad_pcitool_node;
/*
* power management setup. Even if it fails, attach will
* succeed as this is a optional feature. Since we are
* always at full power, this is not critical.
*/
}
/*
* add cpr callback
*/
break;
(void) px_lib_dev_fini(dip);
ret = DDI_FAILURE;
break;
case DDI_RESUME:
/* suspend might have not succeeded */
"instance NOT suspended\n");
ret = DDI_FAILURE;
break;
}
(void) pcie_pwr_resume(dip);
break;
default:
ret = DDI_FAILURE;
break;
}
return (ret);
}
/*
* detach entry point:
*/
/*ARGSUSED*/
static int
{
int ret;
/*
* Make sure we are currently attached
*/
return (DDI_FAILURE);
}
switch (cmd) {
case DDI_DETACH:
/*
* remove cpr callback
*/
#ifdef HOTPLUG
/*
* Hot plug will be done later.
*/
return (DDI_FAILURE);
}
}
#endif /* HOTPLUG */
/*
* things which used to be done in obj_destroy
* are now in-lined here.
*/
(void) px_lib_dev_fini(dip);
/*
* Free the px soft state structure and the rest of the
* resources it's using.
*/
/* Free the interrupt-priorities prop if we created it. */ {
int len;
"interrupt-priorities");
}
return (DDI_SUCCESS);
case DDI_SUSPEND:
return (DDI_FAILURE);
}
return (ret);
default:
return (DDI_FAILURE);
}
}
/*
* power management related initialization specific to px
* called by px_attach()
*/
static int
{
/*
* indicate support LDI (Layered Driver Interface)
* Create the property, if it is not already there
*/
DDI_KERNEL_IOCTL)) {
return (DDI_FAILURE);
}
}
/* No support for device PM. We are always at full power */
(void *)(uintptr_t)px_pwr_pil);
(void *)PX_ERR_PIL);
&iblk_cookie) != DDI_SUCCESS) {
goto pwr_setup_err1;
}
(void *)iblk_cookie);
goto pwr_setup_err2;
}
/* Initilize handle */
/* Add PME_TO_ACK message handler */
" PME_TO_ACK intr\n");
goto px_pwrsetup_err;
}
return (DDI_SUCCESS);
return (DDI_FAILURE);
}
/*
* undo whatever is done in px_pwr_setup. called by px_detach()
*/
static void
{
return;
/* Initilize handle */
}
/* bus driver entry points */
/*
* bus map entry point:
*
* if map request is for an rnumber
* get the corresponding regspec from device node
* build a new regspec in our parent's format
* build a new map_req with the new regspec
* call up the tree to complete the mapping
*/
int
{
return (DDI_ME_UNIMPLEMENTED);
case DDI_MT_REGSPEC:
break;
case DDI_MT_RNUMBER:
return (DDI_ME_RNUMBER_RANGE);
return (DDI_ME_RNUMBER_RANGE);
}
break;
default:
return (DDI_ME_INVAL);
}
/*
* There may be a need to differentiate between PCI
* and PCI-Ex devices so the following range check is
* done correctly, depending on the implementation of
* px_pci bridge nexus driver.
*/
if ((off >= PCIE_CONF_HDR_SIZE) ||
(len > PCIE_CONF_HDR_SIZE) ||
return (DDI_ME_INVAL);
/*
* the following function returning a DDI_FAILURE assumes
* that there are no virtual config space access services
* defined in this layer. Otherwise it is availed right
* here and we return.
*/
if (rval == DDI_SUCCESS)
goto done;
}
/*
* No virtual config space services or we are mapping
* to the parent.
*/
/* relocate within 64-bit pci space through "assigned-addresses" */
goto done;
if (len) /* adjust regspec according to mapping request */
/* translate relocated pci regspec into parent space through "ranges" */
goto done;
if (rval == DDI_SUCCESS) {
/*
* Set-up access functions for FM access error capable drivers.
*/
}
done:
return (rval);
}
/*
* bus dma map entry point
* return value:
* DDI_DMA_PARTIAL_MAP 1
* DDI_DMA_MAPOK 0
* DDI_DMA_MAPPED 0
* DDI_DMA_NORESOURCES -1
* DDI_DMA_NOMAPPING -2
* DDI_DMA_TOOBIG -3
*/
int
{
int ret;
return (DDI_DMA_NORESOURCES);
return (DDI_DMA_NOMAPPING);
goto freehandle;
goto freehandle;
switch (PX_DMA_TYPE(mp)) {
case DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */
goto freehandle;
if (PX_DMA_CANFAST(mp)) {
break;
/* LINTED E_NOP_ELSE_STMT */
} else {
}
}
goto freehandle;
break;
case DMAI_FLAGS_PTP: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */
goto freehandle;
break;
case DMAI_FLAGS_BYPASS:
default:
PX_DMA_TYPE(mp));
/*NOTREACHED*/
}
if (ret == DDI_DMA_NORESOURCES)
else
return (ret);
}
/*
* bus dma alloc handle entry point:
*/
int
{
int rval;
return (DDI_DMA_BADATTR);
return (DDI_DMA_NORESOURCES);
/*
* Save requestor's information
*/
/* check and convert dma attributes to handle parameters */
return (rval);
}
return (DDI_SUCCESS);
}
/*
* bus dma free handle entry point:
*/
/*ARGSUSED*/
int
{
if (px_kmem_clid) {
}
return (DDI_SUCCESS);
}
/*
* bus dma bind handle entry point:
*/
int
{
int ret;
return (DDI_DMA_INUSE);
goto err;
goto err;
switch (PX_DMA_TYPE(mp)) {
case DMAI_FLAGS_DVMA:
goto map_err;
if (PX_DMA_CANFAST(mp)) {
goto mapped; /*LINTED E_NOP_ELSE_STMT*/
} else {
}
}
goto map_err;
*ccountp = 1;
break;
case DMAI_FLAGS_BYPASS:
case DMAI_FLAGS_PTP:
goto map_err;
break;
default:
/*NOTREACHED*/
}
/* insert dma handle into FMA cache */
err:
return (ret);
}
/*
* bus dma unbind handle entry point:
*/
/*ARGSUSED*/
int
{
return (DDI_FAILURE);
}
/* remove dma handle from FMA cache */
}
}
/*
* Here if the handle is using the iommu. Unload all the iommu
* translations.
*/
switch (PX_DMA_TYPE(mp)) {
case DMAI_FLAGS_DVMA:
break;
case DMAI_FLAGS_BYPASS:
case DMAI_FLAGS_PTP:
break;
default:
/*NOTREACHED*/
}
if (mmu_p->mmu_dvma_clid != 0) {
}
if (px_kmem_clid) {
}
return (DDI_SUCCESS);
}
/*
* bus dma win entry point:
*/
int
{
int ret;
return (DDI_FAILURE);
}
switch (PX_DMA_TYPE(mp)) {
case DMAI_FLAGS_DVMA:
/* map_window sets dmai_mapping/size/offset */
return (ret);
}
if (cookiep)
if (ccountp)
*ccountp = 1;
break;
case DMAI_FLAGS_PTP:
case DMAI_FLAGS_BYPASS: {
int i;
win_p->win_curseg = 0;
if (ccountp)
}
break;
default:
PX_DMA_TYPE(mp));
return (DDI_FAILURE);
}
if (cookiep)
"cookie - dmac_address=%x dmac_size=%x\n",
if (offp)
if (lenp)
return (DDI_SUCCESS);
}
#ifdef DEBUG
static char *px_dmactl_str[] = {
"DDI_DMA_FREE",
"DDI_DMA_SYNC",
"DDI_DMA_HTOC",
"DDI_DMA_KVADDR",
"DDI_DMA_MOVWIN",
"DDI_DMA_REPWIN",
"DDI_DMA_GETERR",
"DDI_DMA_COFF",
"DDI_DMA_NEXTWIN",
"DDI_DMA_NEXTSEG",
"DDI_DMA_SEGTOC",
"DDI_DMA_RESERVE",
"DDI_DMA_RELEASE",
"DDI_DMA_RESETH",
"DDI_DMA_CKSYNC",
"DDI_DMA_IOPB_ALLOC",
"DDI_DMA_IOPB_FREE",
"DDI_DMA_SMEM_ALLOC",
"DDI_DMA_SMEM_FREE",
"DDI_DMA_SET_SBUS64"
};
#endif /* DEBUG */
/*
* bus dma control entry point:
*/
/*ARGSUSED*/
int
{
#ifdef DEBUG
#endif /* DEBUG */
switch (cmd) {
case DDI_DMA_FREE:
return (DDI_SUCCESS);
case DDI_DMA_RESERVE: {
}
case DDI_DMA_RELEASE: {
}
default:
break;
}
switch (PX_DMA_TYPE(mp)) {
case DMAI_FLAGS_DVMA:
cache_flags));
case DMAI_FLAGS_PTP:
case DMAI_FLAGS_BYPASS:
cache_flags));
default:
mp->dmai_flags);
/*NOTREACHED*/
}
return (0);
}
/*
* control ops entry point:
*
* Requests handled completely:
* DDI_CTLOPS_INITCHILD see init_child() for details
* DDI_CTLOPS_UNINITCHILD
* DDI_CTLOPS_REPORTDEV see report_dev() for details
* DDI_CTLOPS_XLATE_INTRS nothing to do
* DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1
* DDI_CTLOPS_REGSIZE
* DDI_CTLOPS_NREGS
* DDI_CTLOPS_NINTRS
* DDI_CTLOPS_DVMAPAGESIZE
* DDI_CTLOPS_POKE
* DDI_CTLOPS_PEEK
*
* All others passed to parent.
*/
int
{
struct detachspec *ds;
struct attachspec *as;
switch (op) {
case DDI_CTLOPS_INITCHILD:
case DDI_CTLOPS_UNINITCHILD:
case DDI_CTLOPS_ATTACH:
case DDI_PRE:
return (pcie_pm_hold(dip));
}
DDI_SUCCESS) {
}
}
return (DDI_SUCCESS);
case DDI_POST:
return (DDI_SUCCESS);
default:
break;
}
break;
case DDI_CTLOPS_DETACH:
case DDI_POST:
}
return (DDI_SUCCESS);
default:
break;
}
break;
case DDI_CTLOPS_REPORTDEV:
return (px_report_dev(rdip));
case DDI_CTLOPS_IOMIN:
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE:
case DDI_CTLOPS_NREGS:
return (DDI_SUCCESS);
case DDI_CTLOPS_DVMAPAGESIZE:
return (DDI_SUCCESS);
case DDI_CTLOPS_POKE: /* platform dependent implementation. */
(peekpoke_ctlops_t *)arg));
case DDI_CTLOPS_PEEK: /* platform dependent implementation. */
case DDI_CTLOPS_POWER:
default:
break;
}
/*
* Now pass the request up to our parent.
*/
}
/* ARGSUSED */
int
{
/* Process DDI_INTROP_SUPPORTED_TYPES request here */
if (intr_op == DDI_INTROP_SUPPORTED_TYPES) {
DDI_INTR_TYPE_FIXED : 0;
&intr_types)) == DDI_SUCCESS) {
/*
* Double check supported interrupt types vs.
* what the host bridge supports.
*/
}
return (ret);
}
/*
* PCI-E nexus driver supports fixed, MSI and MSI-X interrupts.
* Return failure if interrupt type is not supported.
*/
case DDI_INTR_TYPE_FIXED:
break;
case DDI_INTR_TYPE_MSI:
case DDI_INTR_TYPE_MSIX:
break;
default:
ret = DDI_ENOTSUP;
break;
}
return (ret);
}