pcie_pwr.h revision bf8fc2340620695a402331e5da7c7db43264174d
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCIE_PWR_H
#define _SYS_PCIE_PWR_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/* index of counters for each level */
#define PCIE_D3_INDEX PM_LEVEL_D3
#define PCIE_D2_INDEX PM_LEVEL_D2
#define PCIE_D1_INDEX PM_LEVEL_D1
#define PCIE_D0_INDEX PM_LEVEL_D0
#define PCIE_MAX_PWR_LEVELS 5
/*
* PCIe nexus power management data structure
*/
typedef struct pcie_pwr {
/*
* general data structure fields
*/
/* power level change */
int pwr_pmcaps; /* pm capability */
int pwr_link_lvl; /* link level. Currently not used */
int pwr_func_lvl; /* function power level */
int pwr_flags; /* flags */
int pwr_hold; /* for temporarily keeping busy */
/*
* counters to keep track of child's power level.
* D3,D2,D1,D0 and unknown respectively.
*/
} pcie_pwr_t;
typedef struct pcie_pwr_child {
/*
* Per child dip counters decsribing
* a child's components
*/
typedef struct pcie_pm {
} pcie_pm_t;
#define PCIE_PMINFO(dip) \
#define PCIE_NEXUS_PMINFO(dip) \
#define PCIE_PAR_PMINFO(dip) \
#define PCIE_CHILD_COUNTERS(cdip) \
#define PCIE_RESET_PMINFO(dip) \
#define PCIE_IS_COMPS_COUNTED(cdip) \
/*
* pmcap field: device power management capability.
* First 4 bits must indicate support for D3, D2, D1 and D0
* respectively. Their bit position matches with their index
* into the counters array.
*/
#define PCIE_SUPPORTS_DEVICE_PM(dip) \
/*
* flags field
*/
#define PCIE_ASPM_ENABLED 0x01
#define PCIE_SLOT_LOADED 0x02
#define PCIE_PM_BUSY 0x04
#define PCIE_NO_CHILD_PM 0x08
#define PM_LEVEL_L3 0
#define PM_LEVEL_L2 1
#define PM_LEVEL_L1 2
#define PM_LEVEL_L0 3
/* ioctl definitions for ppm drivers */
#define PPMREQ_MASK 0xffff
/* settle time in microseconds before PCI operation */
#define PCI_CLK_SETTLE_TIME 10000
/*
* Interface with other parts of the driver(s) code
*/
/*
* We link pcie_pwr.o into several drivers (px, px_pci, pxb_bcm, pxb_plx), which
* causes the symbols below to be duplicated. This isn't an issue in
* practice, since they aren't used from outside the module that they're
* part of. However, lint does not know this, and when it does global
* crosschecks for the kernel, it complains. To prevent this, we rename the
* symbols to driver-specific names when we're doing a lint run.
*/
#if defined(lint)
#if defined(PX_MOD_NAME)
#endif /* PX_MOD_NAME */
#if defined(PX_PLX)
#endif /* PX_PLX */
#endif /* lint */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCIE_PWR_H */