pcicfg.e.c revision f500b19684bd0346ac05bec02a50af07f369da1a
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* PCI configurator (pcicfg)
*/
#include <sys/isa_defs.h>
#include <sys/autoconf.h>
#include <sys/ddi_impldefs.h>
#include <sys/pcie_impl.h>
#include <sys/ndi_impldefs.h>
#define PCICFG_DEVICE_TYPE_PCI 1
#define PCICFG_DEVICE_TYPE_PCIE 2
#define EFCODE21554 /* changes for supporting 21554 */
#ifdef PCICFG_INTERPRET_FCODE
#endif /* PCICFG_INTERPRET_FCODE */
/*
* ************************************************************************
* *** Implementation specific local data structures/definitions. ***
* ************************************************************************
*/
static int pcicfg_start_devno = 0; /* for Debug only */
#define PCICFG_MAX_DEVICE 32
#define PCICFG_MAX_FUNCTION 8
#define PCICFG_MAX_REGISTER 64
#define PCICFG_MAX_BUS_DEPTH 255
#define PCICFG_NODEVICE 42
#define PCICFG_NOMEMORY 43
#define PCICFG_NOMULTI 44
#define PCICFG_MEMGRAN 0x100000
#define PCICFG_IOGRAN 0x1000
#define PCICFG_4GIG_LIMIT 0xFFFFFFFFUL
#define PCICFG_MEM_MULT 4
#define PCICFG_IO_MULT 4
static int pcicfg_slot_busnums = 8;
static int pcicfg_chassis_per_tree = 1;
static int pcicfg_sec_reset_delay = 1000000;
/*
* The following typedef is used to represent a
* 1275 "bus-range" property of a PCI Bus node.
* DAF - should be in generic include file...
*/
typedef struct pcicfg_bus_range {
typedef struct pcicfg_range {
struct hole {
};
typedef struct pcicfg_phdl pcicfg_phdl_t;
struct pcicfg_phdl {
int error;
};
struct pcicfg_standard_prop_entry {
};
struct pcicfg_name_entry {
char *name;
};
struct pcicfg_find_ctrl {
};
typedef struct pcicfg_err_regs {
/*
* List of Indirect Config Map Devices. At least the intent of the
* design is to look for a device in this list during the configure
* operation, and if the device is listed here, then it is a nontransparent
* bridge, hence load the driver and avail the config map services from
* the driver. Class and Subclass should be as defined in the PCI specs
* ie. class is 0x6, and subclass is 0x9.
*/
static struct {
} pcicfg_indirect_map_devs[] = {
0, 0, 0,
};
(\
((ulong_t)(register & 0x3f)))
/*
* debug macros:
*/
#if defined(DEBUG)
extern void prom_printf(const char *, ...);
/*
* Following values are defined for this debug flag.
*
* 1 = dump configuration header only.
* 2 = dump generic debug data only (no config header dumped)
* 3 = dump everything (both 1 and 2)
*/
int pcicfg_debug = 0;
int pcicfg_dump_fcode = 0;
#else
#endif
#ifdef PCICFG_INTERPRET_FCODE
int pcicfg_dont_interpret = 0;
#else
int pcicfg_dont_interpret = 1;
#endif
/*
* forward declarations for routines defined in this module (called here)
*/
static int pcicfg_add_config_reg(dev_info_t *,
uint_t *);
#ifdef PCICFG_INTERPRET_FCODE
#endif
uint_t *);
static int pcicfg_free_all_resources(dev_info_t *);
static int pcicfg_alloc_new_resources(dev_info_t *);
static int pcicfg_match_dev(dev_info_t *, void *);
static int pcicfg_destroy_phdl(dev_info_t *);
static int pcicfg_sum_resources(dev_info_t *, void *);
static int pcicfg_find_resource_end(dev_info_t *, void *);
static int pcicfg_allocate_chunk(dev_info_t *);
static int pcicfg_program_ap(dev_info_t *);
static int pcicfg_device_assign(dev_info_t *);
static int pcicfg_bridge_assign(dev_info_t *, void *);
static int pcicfg_free_resources(dev_info_t *);
dev_info_t *);
static void pcicfg_device_on(ddi_acc_handle_t);
static void pcicfg_device_off(ddi_acc_handle_t);
static int pcicfg_free_bridge_resources(dev_info_t *);
static int pcicfg_free_device_resources(dev_info_t *);
static int pcicfg_teardown_device(dev_info_t *);
static void pcicfg_config_teardown(ddi_acc_handle_t *);
static int pcicfg_dump_assigned(dev_info_t *);
static int pcicfg_is_ntbridge(dev_info_t *);
static int pcicfg_ntbridge_allocate_resources(dev_info_t *);
static int pcicfg_ntbridge_configure_done(dev_info_t *);
static int pcicfg_ntbridge_unconfigure(dev_info_t *);
static void pcicfg_free_hole(hole_t *);
#ifdef DEBUG
static void pcicfg_dump_device_config(ddi_acc_handle_t);
#else
#define PCICFG_DUMP_COMMON_CONFIG(handle)
#define PCICFG_DUMP_DEVICE_CONFIG(handle)
#define PCICFG_DUMP_BRIDGE_CONFIG(handle)
#endif
#ifndef _DONT_USE_1275_GENERIC_NAMES
/*
* Class code table
*/
static struct pcicfg_name_entry pcicfg_class_lookup [] = {
{ 0x001, "display" },
{ 0x100, "scsi" },
{ 0x101, "ide" },
{ 0x102, "fdc" },
{ 0x103, "ipi" },
{ 0x104, "raid" },
{ 0x200, "ethernet" },
{ 0x201, "token-ring" },
{ 0x202, "fddi" },
{ 0x203, "atm" },
{ 0x300, "display" },
{ 0x400, "video" },
{ 0x401, "sound" },
{ 0x500, "memory" },
{ 0x501, "flash" },
{ 0x600, "host" },
{ 0x601, "isa" },
{ 0x602, "eisa" },
{ 0x603, "mca" },
{ 0x604, "pci" },
{ 0x605, "pcmcia" },
{ 0x606, "nubus" },
{ 0x607, "cardbus" },
{ 0x609, "pci" },
{ 0x700, "serial" },
{ 0x701, "parallel" },
{ 0x800, "interrupt-controller" },
{ 0x801, "dma-controller" },
{ 0x802, "timer" },
{ 0x803, "rtc" },
{ 0x900, "keyboard" },
{ 0x901, "pen" },
{ 0x902, "mouse" },
{ 0xa00, "dock" },
{ 0xb00, "cpu" },
{ 0xc00, "firewire" },
{ 0xc01, "access-bus" },
{ 0xc02, "ssa" },
{ 0xc03, "usb" },
{ 0xc04, "fibre-channel" },
{ 0, 0 }
};
#endif /* _DONT_USE_1275_GENERIC_NAMES */
/*
* Module control operations
*/
extern struct mod_ops mod_miscops;
&mod_miscops, /* Type of module */
};
static struct modlinkage modlinkage = {
};
#ifdef DEBUG
static void
{
if ((pcicfg_debug & 1) == 0)
return;
}
static void
{
if ((pcicfg_debug & 1) == 0)
return;
}
static void
{
if ((pcicfg_debug & 1) == 0)
return;
}
#endif
int
_init()
{
DEBUG0("PCI configurator installed - Fcode Interpretation/21554\n");
return (mod_install(&modlinkage));
}
int
_fini(void)
{
int error;
if (error != 0) {
return (error);
}
return (0);
}
int
{
}
/*ARGSUSED*/
static uint8_t
{
&cap_ptr)) == DDI_SUCCESS) {
== DDI_SUCCESS) {
== DDI_SUCCESS) {
if ((port_type == PCIE_PCIECAP_DEV_TYPE_DOWN) &&
num_slots = 1;
}
DEBUG3("%s#%d has %d slots",
return (num_slots);
}
/*ARGSUSED*/
static uint8_t
{
DDI_FAILURE) {
if (PCI_CAPSLOT_FIC(esr_reg))
return (B_TRUE);
}
return (B_FALSE);
}
/*ARGSUSED*/
static int
{
/* get parent device's device_type property */
char *device_type;
int rc = DDI_FAILURE;
!= DDI_PROP_SUCCESS) {
DEBUG2("device_type property missing for %s#%d",
return (DDI_FAILURE);
}
switch (bus_type) {
case PCICFG_DEVICE_TYPE_PCIE:
rc = DDI_SUCCESS;
}
break;
case PCICFG_DEVICE_TYPE_PCI:
rc = DDI_SUCCESS;
break;
default:
break;
}
return (rc);
}
/*ARGSUSED*/
static int
{
int port_type = -1;
return (port_type);
}
static int
{
/* No PCIe CAP regs, we are not PCIe device_type */
if (port_type < 0)
return (DDI_FAILURE);
/* check for all PCIe device_types */
if ((port_type == PCIE_PCIECAP_DEV_TYPE_UP) ||
(port_type == PCIE_PCIECAP_DEV_TYPE_DOWN) ||
return (DDI_SUCCESS);
return (DDI_FAILURE);
}
/*
* In the following functions ndi_devi_enter() without holding the
* parent dip is sufficient. This is because pci dr is driven through
* opens on the nexus which is in the device tree path above the node
* being operated on, and implicitly held due to the open.
*/
/*
* This entry point is called to configure a device (and
* all its children) on the given bus. It is called when
* a new device is added to the PCI domain. This routine
* will create the device tree and program the devices
* registers.
*/
int
{
int len;
int func;
int rv;
int circ;
uint_t highest_bus = 0;
/*
* Start probing at the device specified in "device" on the
* "bus" specified.
*/
len = sizeof (pcicfg_bus_range_t);
DEBUG0("no bus-range property\n");
return (PCICFG_FAILURE);
}
/*
* Try executing fcode if available.
*/
&highest_bus)) {
case PCICFG_FAILURE:
DEBUG2("configure failed: "
"bus [0x%x] device [0x%x]\n",
break;
case PCICFG_NODEVICE:
DEBUG3("no device : bus "
"[0x%x] slot [0x%x] func [0x%x]\n",
if (func)
continue;
break;
default:
DEBUG3("configure: bus => [%d] "
"slot => [%d] func => [%d]\n",
break;
}
if (rv != PCICFG_SUCCESS)
break;
DEBUG0("Did'nt find device node just created\n");
goto cleanup;
}
}
if (func == 0)
return (PCICFG_FAILURE); /* probe failed */
else
return (PCICFG_SUCCESS);
/*
* Clean up a partially created "probe state" tree.
* There are no resources allocated to the in the
* probe state.
*/
DEBUG0("No more devices to clean up\n");
continue;
}
DEBUG2("Cleaning up device [0x%x] function [0x%x]\n",
/*
* If this was a bridge device it will have a
* probe handle - if not, no harm in calling this.
*/
(void) pcicfg_destroy_phdl(new_device);
/*
* This will free up the node
*/
}
return (PCICFG_FAILURE);
}
/*
* configure the child nodes of ntbridge. new_device points to ntbridge itself
*/
/*ARGSUSED*/
static uint_t
{
int devno;
uint8_t pcie_device_type = 0;
/*
* If we need to do indirect config, lets create a property here
* to let the child conf map routine know that it has to
* go through the DDI calls, and not assume the devices are
* mapped directly under the host.
*/
PCI_DEV_CONF_MAP_PROP, (int)DDI_SUCCESS))
!= DDI_SUCCESS) {
DEBUG0("Cannot create indirect conf map property.\n");
return ((uint_t)PCICFG_FAILURE);
}
return ((uint_t)PCICFG_FAILURE);
/* check if we are PCIe device */
pcie_device_type = 1;
/* create Bus node properties for ntbridge. */
DEBUG0("Failed to set busnode props\n");
return (rc);
}
/* For now: Lets only support one layer of child */
NDI_RA_PASS) != NDI_SUCCESS) {
DEBUG0("ntbridge: Failed to get a bus number\n");
return (rc);
}
/*
* Following will change, as we detect more bridges
* on the way.
*/
DEBUG0("Cannot set ntbridge bus-range property");
return (rc);
}
/*
* The other interface (away from the host) will be
* initialized by the nexus driver when it loads.
* We just have to set the registers and the nexus driver
* figures out the rest.
*/
/*
* finally, lets load and attach the driver
* before configuring children of ntbridge.
*/
if (rc != NDI_SUCCESS) {
"pcicfg: Fail: can\'t load non-transparent bridge \
driver.\n");
rc = PCICFG_FAILURE;
return (rc);
}
DEBUG0("pcicfg: Success loading nontransparent bridge nexus driver..");
/* Now set aside pci resources for our children. */
max_devs = 0;
rc = PCICFG_FAILURE;
} else
/* Probe devices on 2nd bus */
!= NDI_SUCCESS) {
DEBUG0("pcicfg: Failed to alloc test node\n");
rc = PCICFG_FAILURE;
break;
}
!= DDI_PROP_SUCCESS) {
"Failed to add conf reg for ntbridge child.\n");
(void) ndi_devi_free(new_ntbridgechild);
rc = PCICFG_FAILURE;
break;
}
&config_handle)) != PCICFG_SUCCESS) {
"Cannot map ntbridge child %x\n", devno);
(void) ndi_devi_free(new_ntbridgechild);
rc = PCICFG_FAILURE;
break;
}
/*
* See if there is any PCI HW at this location
* by reading the Vendor ID. If it returns with 0xffff
* then there is no hardware at this location.
*/
(void) ndi_devi_free(new_ntbridgechild);
if (vid == 0xffff)
continue;
/* Lets fake attachments points for each child, */
int old_dev = pcicfg_start_devno;
"Error configuring ntbridge child dev=%d\n", devno);
rc = PCICFG_FAILURE;
"Unconfig Error ntbridge child "
"dev=%d\n", old_dev);
old_dev++;
}
break;
}
} /* devno loop */
if (rc != PCICFG_FAILURE)
else {
int k;
&k) != DDI_PROP_SUCCESS) {
DEBUG0("Failed to read bus-range property\n");
rc = PCICFG_FAILURE;
return (rc);
}
DEBUG2("Need to free bus [%d] range [%d]\n",
DEBUG0("Failed to free a bus number\n");
rc = PCICFG_FAILURE;
/*
* Don't forget to free up memory from ddi_getlongprop
*/
return (rc);
}
/*
* Since no memory allocations are done for non transparent
* bridges (but instead we just set the handle with the
* already allocated memory, we just need to reset the
* following values before calling the destroy_phdl()
* function next, otherwise the it will try to free
* memory allocated as in case of a transparent bridge.
*/
entry->memory_len = 0;
/* the following will free hole data. */
(void) pcicfg_destroy_phdl(new_device);
/*
* Don't forget to free up memory from ddi_getlongprop
*/
}
/*
* Unload driver just in case child configure failed!
*/
if (rc1 != NDI_SUCCESS) {
"pcicfg: can\'t unload ntbridge driver children.\n");
rc = PCICFG_FAILURE;
}
return (rc);
}
static int
{
/* Set Memory space handle for ntbridge */
PCI_BASE_SPACE_MEM) != DDI_SUCCESS) {
"ntbridge: Mem resource information failure\n");
phdl->memory_len = 0;
return (PCICFG_FAILURE);
}
/*
* mem_request->ra_len =
* PCICFG_ROUND_UP(mem_request->ra_len, PCICFG_MEMGRAN);
*/
DEBUG2("AP requested [0x%llx], needs [0x%llx] bytes of memory\n",
/* set up a memory resource map for NT bridge */
DEBUG0("Can not setup ntbridge memory resource map\n");
return (PCICFG_FAILURE);
}
/* initialize the memory map */
NDI_RA_PASS) != NDI_SUCCESS) {
DEBUG0("Can not initalize ntbridge memory resource map\n");
return (PCICFG_FAILURE);
}
/* Set IO space handle for ntbridge */
PCI_BASE_SPACE_IO) != DDI_SUCCESS) {
return (PCICFG_FAILURE);
}
/*
* io_request->ra_len =
* PCICFG_ROUND_UP(io_request->ra_len, PCICFG_IOGRAN);
*/
DEBUG2("AP requested [0x%llx], needs [0x%llx] bytes of IO\n",
DEBUG2("MEMORY BASE = [0x%x] length [0x%x]\n",
DEBUG2("IO BASE = [0x%x] length [0x%x]\n",
/* set up a IO resource map for NT bridge */
DEBUG0("Can not setup ntbridge memory resource map\n");
return (PCICFG_FAILURE);
}
/* initialize the IO map */
NDI_RA_PASS) != NDI_SUCCESS) {
DEBUG0("Can not initalize ntbridge memory resource map\n");
return (PCICFG_FAILURE);
}
return (PCICFG_SUCCESS);
}
static int
{
int new_bus_range[2];
sizeof (pcicfg_range_t) * PCICFG_RANGE_LEN);
(PCI_REG_REL_M | PCI_ADDR_IO);
len = sizeof (pcicfg_bus_range_t);
DEBUG0("no bus-range property\n");
return (PCICFG_FAILURE);
}
"ntbridge bus range invalid !(%d,%d)\n",
}
else
}
else
DEBUG2("ntbridge: bus range lo=%x, hi=%x\n",
DEBUG0("Failed to set bus-range property");
return (PCICFG_FAILURE);
}
#ifdef DEBUG
{
DEBUG2("ntbridge: Unused IO space %llx bytes over %d holes\n",
}
#endif
DEBUG0("Failed to update ranges (i/o)\n");
return (PCICFG_FAILURE);
}
#ifdef DEBUG
{
DEBUG2("ntbridge: Unused Mem space %llx bytes over %d holes\n",
}
#endif
DEBUG0("Failed to update ranges (memory)\n");
return (PCICFG_FAILURE);
}
return (PCICFG_SUCCESS);
}
static int
{
len = sizeof (pcicfg_bus_range_t);
DEBUG0("no bus-range property\n");
return (PCICFG_FAILURE);
}
DEBUG0("pcicfg: Failed to alloc test node\n");
return (PCICFG_FAILURE);
}
!= DDI_PROP_SUCCESS) {
"Unconfigure: Failed to add conf reg prop for ntbridge "
"child.\n");
(void) ndi_devi_free(new_ntbridgechild);
return (PCICFG_FAILURE);
}
!= DDI_SUCCESS) {
"pcicfg: Cannot map ntbridge child %x\n", devno);
(void) ndi_devi_free(new_ntbridgechild);
return (PCICFG_FAILURE);
}
/*
* See if there is any PCI HW at this location
* by reading the Vendor ID. If it returns with 0xffff
* then there is no hardware at this location.
*/
(void) ndi_devi_free(new_ntbridgechild);
if (vid == 0xffff)
return (PCICFG_NODEVICE);
}
static int
{
int k, rc = PCICFG_FAILURE;
if (entry->memory_len)
DEBUG1("cannot destroy ntbridge memory map size=%x\n",
entry->memory_len);
return (PCICFG_FAILURE);
}
DEBUG1("cannot destroy ntbridge io map size=%x\n",
return (PCICFG_FAILURE);
}
&k) != DDI_PROP_SUCCESS) {
DEBUG0("ntbridge: Failed to read bus-range property\n");
return (rc);
}
DEBUG2("ntbridge: Need to free bus [%d] range [%d]\n",
DEBUG0("ntbridge: Failed to free a bus number\n");
/*
* Don't forget to free up memory from ddi_getlongprop
*/
return (rc);
}
/*
* Don't forget to free up memory from ddi_getlongprop
*/
/*
* Since our resources will be freed at the parent level,
* just reset these values.
*/
entry->memory_len = 0;
/* the following will also free hole data. */
return (pcicfg_destroy_phdl(dip));
}
static int
{
int rc = DDI_SUCCESS;
"pcicfg: cannot map config space, to get map type\n");
return (DDI_FAILURE);
}
/* check for class=6, subclass=9, for non transparent bridges. */
rc = DDI_FAILURE;
DEBUG3("pcicfg: checking device %x,%x for indirect map. rc=%d\n",
rc);
return (rc);
}
/*
* this function is called only for SPARC platforms, where we may have
* a mix n' match of direct vs indirectly mapped configuration space.
* On x86, this function does not get called. We always return TRUE
* via a macro for x86.
*/
/*ARGSUSED*/
static int
{
#if defined(__sparc)
int rc = DDI_FAILURE;
rc = DDI_SUCCESS;
else
DDI_FAILURE) != DDI_FAILURE)
rc = DDI_SUCCESS;
return (rc);
#else
return (DDI_SUCCESS);
#endif
}
static uint_t
{
return (found);
&length) != DDI_PROP_SUCCESS) {
return (found);
}
DEBUG1("pcicfg: ntbridge child range: dip = %s\n",
for (i = 0; i < acount; i++) {
(space_type == PCI_BASE_SPACE_MEM)) {
found = DDI_SUCCESS;
break;
} else {
(space_type == PCI_BASE_SPACE_IO)) {
found = DDI_SUCCESS;
break;
}
}
}
DEBUG3("pcicfg: ntbridge child range: space=%x, base=%lx, len=%lx\n",
if (found == DDI_SUCCESS) {
}
return (found);
}
/*
* This will turn resources allocated by pcicfg_configure()
* and remove the device tree from the attachment point
* and below. The routine assumes the devices have their
* drivers detached.
*/
int
{
int func;
int i;
/*
* Cycle through devices to make sure none are busy.
* If a single device is busy fail the whole unconfigure.
*/
continue;
continue;
/*
* Device function is busy. Before returning we have to
* put all functions back online which were taken
* offline during the process.
*/
for (i = 0; i < func; i++) {
== NULL) {
"No more devices to put back on line!!\n");
/*
* Made it through all functions
*/
continue;
}
!= NDI_SUCCESS) {
DEBUG0("Failed to put back devices state\n");
return (PCICFG_FAILURE);
}
}
return (PCICFG_FAILURE);
}
/*
* Now, tear down all devinfo nodes for this AP.
*/
DEBUG0("No more devices to tear down!\n");
continue;
}
DEBUG2("Tearing down device [0x%x] function [0x%x]\n",
if (pcicfg_ntbridge_unconfigure(child_dip) !=
"ntbridge: unconfigure failed\n");
return (PCICFG_FAILURE);
}
DEBUG2("Failed to tear down device [0x%x]"
"function [0x%x]\n",
return (PCICFG_FAILURE);
}
}
return (PCICFG_SUCCESS);
}
static int
{
/*
* Free up resources associated with 'dip'
*/
DEBUG0("Failed to free resources\n");
return (PCICFG_FAILURE);
}
/*
* This will disable the device
*/
return (PCICFG_FAILURE);
}
/*
* The framework provides this routine which can
* tear down a sub-tree.
*/
DEBUG0("Failed to offline and remove node\n");
return (PCICFG_FAILURE);
}
return (PCICFG_SUCCESS);
}
/*
* BEGIN GENERIC SUPPORT ROUTINES
*/
static pcicfg_phdl_t *
{
return (entry);
}
}
/*
* Did'nt find entry - create one
*/
return (pcicfg_create_phdl(dip));
}
static pcicfg_phdl_t *
{
KM_SLEEP);
return (new);
}
static int
{
if (entry == pcicfg_phdl_list) {
} else {
}
/*
* If this entry has any allocated memory
* or IO space associated with it, that
* must be freed up.
*/
if (entry->memory_len > 0) {
}
}
/*
* Destroy this entry
*/
return (PCICFG_SUCCESS);
}
}
/*
* Did'nt find the entry
*/
return (PCICFG_FAILURE);
}
static int
{
DEBUG0("Failed to map config space!\n");
return (PCICFG_FAILURE);
}
(void) pcicfg_config_teardown(&handle);
DEBUG0("Not enough memory to hotplug\n");
(void) pcicfg_destroy_phdl(dip);
return (PCICFG_FAILURE);
}
DEBUG0("Problem assigning bridge\n");
(void) pcicfg_destroy_phdl(dip);
}
/*
* Successfully allocated and assigned
* memory. Set the memory and IO length
* to zero so when the handle is freed up
* it will not de-allocate assigned resources.
*/
/*
* Free up the "entry" structure.
*/
(void) pcicfg_destroy_phdl(dip);
} else {
return (PCICFG_FAILURE);
}
}
return (PCICFG_SUCCESS);
}
static int
{
int length;
int rcount;
int i;
int offset;
int count;
int bus_range[2];
DEBUG0("Failed to get entry\n");
return (DDI_WALK_TERMINATE);
}
DEBUG0("Failed to map config space!\n");
return (DDI_WALK_TERMINATE);
}
sizeof (pcicfg_range_t) * PCICFG_RANGE_LEN);
(PCI_REG_REL_M | PCI_ADDR_IO);
pcicfg_bridge_assign, (void *)entry);
DEBUG0("Failed to set bus-range property");
return (DDI_WALK_TERMINATE);
}
DEBUG0("Failed to update ranges (i/o)\n");
return (DDI_WALK_TERMINATE);
}
}
if (entry->memory_len > 0) {
DEBUG0("Failed to update ranges (memory)\n");
return (DDI_WALK_TERMINATE);
}
}
(void) pcicfg_device_on(handle);
return (DDI_WALK_PRUNECHILD);
}
/*
* If there is an interrupt pin set program
* interrupt line with default values.
*/
}
/*
* A single device (under a bridge).
* For each "reg" property with a length, allocate memory
* and program the base registers.
*/
&length) != DDI_PROP_SUCCESS) {
DEBUG0("Failed to read reg property\n");
return (DDI_WALK_TERMINATE);
}
for (i = 0; i < rcount; i++) {
if ((reg[i].pci_size_low != 0)||
(reg[i].pci_size_hi != 0)) {
case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
(void) pcicfg_get_mem(entry,
DEBUG2("REGISTER off %x (64)LO ----> [0x%x]\n",
DEBUG2("REGISTER off %x (64)HI ----> [0x%x]\n",
offset + 4,
reg[i].pci_phys_mid =
break;
case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
/* allocate memory space from the allocator */
(void) pcicfg_get_mem(entry,
DEBUG2("REGISTER off %x(32)LO ----> [0x%x]\n",
break;
case PCI_REG_ADDR_G(PCI_ADDR_IO):
/* allocate I/O space from the allocator */
(void) pcicfg_get_io(entry,
DEBUG2("REGISTER off %x (I/O)LO ----> [0x%x]\n",
break;
default:
DEBUG0("Unknown register type\n");
(void) pcicfg_config_teardown(&handle);
return (DDI_WALK_TERMINATE);
} /* switch */
/*
* Now that memory locations are assigned,
* update the assigned address property.
*/
®[i]) != PCICFG_SUCCESS) {
(void) pcicfg_config_teardown(&handle);
return (DDI_WALK_TERMINATE);
}
}
}
(void) pcicfg_device_on(handle);
(void) pcicfg_config_teardown(&handle);
/*
* Don't forget to free up memory from ddi_getlongprop
*/
return (DDI_WALK_CONTINUE);
}
static int
{
int length;
int rcount;
int i;
int offset;
/*
* XXX Failure here should be noted
*/
&length) != DDI_PROP_SUCCESS) {
DEBUG0("Failed to read reg property\n");
return (PCICFG_FAILURE);
}
DEBUG0("Failed to map config space!\n");
/*
* Don't forget to free up memory from ddi_getlongprop
*/
return (PCICFG_FAILURE);
}
/*
* A single device
*
* For each "reg" property with a length, allocate memory
* and program the base registers.
*/
/*
* If there is an interrupt pin set program
* interrupt line with default values.
*/
}
request.ra_boundbase = 0;
for (i = 0; i < rcount; i++) {
if ((reg[i].pci_size_low != 0)||
(reg[i].pci_size_hi != 0)) {
case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
/* allocate memory space from the allocator */
!= NDI_SUCCESS) {
DEBUG0("Failed to allocate 64b mem\n");
(void) pcicfg_config_teardown(&handle);
return (PCICFG_FAILURE);
}
DEBUG3("64 addr = [0x%x.%x] len [0x%x]\n",
alen);
/* program the low word */
/* program the high word with value zero */
/*
* currently support 32b address space
* assignments only.
*/
offset += 8;
break;
case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
/* allocate memory space from the allocator */
!= NDI_SUCCESS) {
DEBUG0("Failed to allocate 32b mem\n");
(void) pcicfg_config_teardown(&handle);
return (PCICFG_FAILURE);
}
DEBUG3("32 addr = [0x%x.%x] len [0x%x]\n",
alen);
/* program the low word */
offset += 4;
break;
case PCI_REG_ADDR_G(PCI_ADDR_IO):
/* allocate I/O space from the allocator */
!= NDI_SUCCESS) {
DEBUG0("Failed to allocate I/O\n");
(void) pcicfg_config_teardown(&handle);
return (PCICFG_FAILURE);
}
DEBUG3("I/O addr = [0x%x.%x] len [0x%x]\n",
alen);
offset += 4;
break;
default:
DEBUG0("Unknown register type\n");
(void) pcicfg_config_teardown(&handle);
return (PCICFG_FAILURE);
} /* switch */
/*
* Now that memory locations are assigned,
* update the assigned address property.
*/
®[i]) != PCICFG_SUCCESS) {
(void) pcicfg_config_teardown(&handle);
return (PCICFG_FAILURE);
}
}
}
(void) pcicfg_device_on(handle);
(void) pcicfg_config_teardown(&handle);
return (PCICFG_SUCCESS);
}
/*
* The "dip" passed to this routine is assumed to be
* the device at the attachment point. Currently it is
* assumed to be a bridge.
*/
static int
{
int count;
/*
* This should not find an existing entry - so
* it will create a new one.
*/
/*
* From this point in the tree - walk the devices,
* The function passed in will read and "sum" up
* the memory and I/O requirements and put them in
* structure "phdl".
*/
DEBUG0("Failure summing resources\n");
}
/*
* Call into the memory allocator with the request.
* Record the addresses returned in the phdl
*/
DEBUG1("AP requires [0x%x] bytes of memory space\n",
DEBUG1("AP requires [0x%x] bytes of I/O space\n",
io_request->ra_len);
io_request->ra_boundbase = 0;
io_request->ra_len =
DEBUG0("Failed to allocate memory\n");
return (PCICFG_FAILURE);
}
DEBUG0("Failed to allocate I/O space\n");
return (PCICFG_FAILURE);
}
DEBUG2("MEMORY BASE = [0x%x] length [0x%x]\n",
DEBUG2("IO BASE = [0x%x] length [0x%x]\n",
return (PCICFG_SUCCESS);
}
#ifdef DEBUG
/*
* This function is useful in debug mode, where we can measure how
* much memory was wasted/unallocated in bridge device's domain.
*/
static uint64_t
{
do {
count++;
} while (hole);
*hole_count = count;
return (len);
}
#endif
/*
* This function frees data structures that hold the hole information
* which are allocated in pcicfg_alloc_hole(). This is not freeing
* any memory allocated through NDI calls.
*/
static void
{
while (hole) {
}
}
static uint64_t
{
do {
DEBUG3("hole found. start %llx, len %llx, req=%x\n",
/* current hole parameters adjust */
} else {
KM_SLEEP);
DEBUG2("put new hole to %llx, %llx\n",
}
DEBUG2("adjust current hole to %llx, %llx\n",
break;
}
actual_hole_start = 0;
} while (hole);
return (actual_hole_start);
}
static void
{
/* See if there is a hole, that can hold this request. */
length);
if (new_mem) { /* if non-zero, found a hole. */
} else
}
static void
{
/*
* See if there is a hole, that can hold this request.
* Pass 64 bit parameters and then truncate to 32 bit.
*/
if (new_io) { /* if non-zero, found a hole. */
} else
}
static int
{
int length;
int rcount;
int i;
DEBUG0("Failed to map config space!\n");
return (DDI_WALK_TERMINATE);
}
/*
* If its a bridge - just record the highest bus seen
*/
PCI_BCNF_SECBUS)) {
entry->highest_bus =
}
(void) pcicfg_config_teardown(&handle);
return (DDI_WALK_CONTINUE);
} else {
&length) != DDI_PROP_SUCCESS) {
/*
* If one node in (the subtree of nodes)
* does'nt have a "reg" property fail the
* allocation.
*/
entry->memory_len = 0;
return (DDI_WALK_TERMINATE);
}
/*
* For each "reg" property with a length, add that to the
* total memory (or I/O) to allocate.
*/
for (i = 0; i < rcount; i++) {
case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
pci_rp[i].pci_size_low +
pci_rp[i].pci_size_low);
DEBUG1("ADDING 32 --->0x%x\n",
pci_rp[i].pci_size_low);
break;
case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
pci_rp[i].pci_size_low +
pci_rp[i].pci_size_low);
DEBUG1("ADDING 64 --->0x%x\n",
pci_rp[i].pci_size_low);
break;
case PCI_REG_ADDR_G(PCI_ADDR_IO):
io_request->ra_len =
pci_rp[i].pci_size_low +
pci_rp[i].pci_size_low);
DEBUG1("ADDING I/O --->0x%x\n",
pci_rp[i].pci_size_low);
break;
default:
/* Config space register - not included */
break;
}
}
/*
* free the memory allocated by ddi_getlongprop
*/
/*
* continue the walk to the next sibling to sum memory
*/
(void) pcicfg_config_teardown(&handle);
return (DDI_WALK_CONTINUE);
}
}
static int
{
int length;
int rcount;
int i;
DEBUG0("Don't include parent bridge node\n");
return (DDI_WALK_CONTINUE);
}
DDI_PROP_DONTPASS, "ranges",
DEBUG0("Node doesn't have ranges\n");
goto ap;
}
for (i = 0; i < rcount; i++) {
case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
break;
case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
break;
case PCI_REG_ADDR_G(PCI_ADDR_IO):
break;
}
}
return (DDI_WALK_CONTINUE);
DDI_PROP_DONTPASS, "assigned-addresses",
DEBUG0("Node doesn't have assigned-addresses\n");
return (DDI_WALK_CONTINUE);
}
for (i = 0; i < rcount; i++) {
case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
if ((pci_ap[i].pci_phys_low +
pci_ap[i].pci_size_low) >
entry_p->memory_base) {
pci_ap[i].pci_phys_low +
pci_ap[i].pci_size_low;
}
break;
case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
pci_ap[i].pci_phys_mid) +
pci_ap[i].pci_size_low) >
entry_p->memory_base) {
pci_ap[i].pci_phys_low,
pci_ap[i].pci_phys_mid) +
pci_ap[i].pci_size_low;
}
break;
case PCI_REG_ADDR_G(PCI_ADDR_IO):
if ((pci_ap[i].pci_phys_low +
pci_ap[i].pci_size_low) >
pci_ap[i].pci_phys_low +
pci_ap[i].pci_size_low;
}
break;
}
}
/*
* free the memory allocated by ddi_getlongprop
*/
/*
* continue the walk to the next sibling to sum memory
*/
return (DDI_WALK_CONTINUE);
}
static int
{
int k;
int length;
int i;
&length) != DDI_PROP_SUCCESS) {
DEBUG0("Failed to read ranges property\n");
if (ddi_get_child(dip)) {
ddi_get_name(dip));
/*
* strictly speaking, we can check for children with
* assigned-addresses but for now it is better to
* be conservative and assume that if there are child
* nodes, then they do consume PCI memory or IO
* resources, Hence return failure.
*/
return (PCICFG_FAILURE);
}
length = 0;
}
for (i = 0; i < length / sizeof (pcicfg_range_t); i++) {
case PCI_ADDR_IO:
DEBUG2("Free I/O "
!= NDI_SUCCESS) {
DEBUG0("Trouble freeing "
"PCI i/o space\n");
return (PCICFG_FAILURE);
}
break;
case PCI_ADDR_MEM32:
case PCI_ADDR_MEM64:
"[0x%x.%x]/[0x%x]\n",
!= NDI_SUCCESS) {
DEBUG0("Trouble freeing "
"PCI memory space\n");
return (PCICFG_FAILURE);
}
break;
default:
DEBUG0("Unknown memory space\n");
break;
}
}
}
if (length)
&k) != DDI_PROP_SUCCESS) {
DEBUG0("Failed to read bus-range property\n");
return (PCICFG_FAILURE);
}
DEBUG2("Need to free bus [%d] range [%d]\n",
/*EMPTY*/
DEBUG0("Failed to free a bus number\n");
}
/*
* Don't forget to free up memory from ddi_getlongprop
*/
return (PCICFG_SUCCESS);
}
static int
{
int length;
int acount;
int i;
&length) != DDI_PROP_SUCCESS) {
DEBUG0("Failed to read assigned-addresses property\n");
return (PCICFG_FAILURE);
}
/*
* For each "assigned-addresses" property entry with a length,
* call the memory allocation routines to return the
* resource.
*/
for (i = 0; i < acount; i++) {
/*
* Workaround for Devconf (x86) bug to skip extra entries
* beyond the PCI_CONF_BASE5 offset. But we want to free up
* any memory for expansion roms if allocated.
*/
break;
DEBUG1("pcicfg_free_device_resources - Trouble freeing "
/*
* Don't forget to free up memory from ddi_getlongprop
*/
return (PCICFG_FAILURE);
}
}
return (PCICFG_SUCCESS);
}
static int
{
DEBUG0("Failed to map config space!\n");
return (PCICFG_FAILURE);
}
(void) pci_config_teardown(&handle);
/*
* A different algorithm is used for bridges and leaf devices.
*/
DEBUG0("Failed freeing up bridge resources\n");
return (PCICFG_FAILURE);
}
} else {
DEBUG0("Failed freeing up device resources\n");
return (PCICFG_FAILURE);
}
}
return (PCICFG_SUCCESS);
}
#ifndef _DONT_USE_1275_GENERIC_NAMES
static char *
{
struct pcicfg_name_entry *ptr;
}
}
return (NULL);
}
#endif /* _DONT_USE_1275_GENERIC_NAMES */
static dev_info_t *
{
struct pcicfg_find_ctrl ctrl;
int count;
}
static int
{
int length;
int pci_dev;
int pci_func;
return (DDI_WALK_TERMINATE);
}
/* get the PCI device address info */
/*
* free the memory allocated by ddi_prop_lookup_int_array
*/
/* found the match for the specified device address */
return (DDI_WALK_TERMINATE);
}
/*
* continue the walk to the next sibling to look for a match.
*/
return (DDI_WALK_PRUNECHILD);
}
static int
{
int alen;
DEBUG0("pcicfg_update_assigned_prop()\n");
switch (status) {
case DDI_PROP_SUCCESS:
break;
case DDI_PROP_NO_MEMORY:
DEBUG0("no memory for assigned-addresses property\n");
return (PCICFG_FAILURE);
default:
"assigned-addresses", (int *)newone,
sizeof (*newone)/sizeof (int));
(void) pcicfg_dump_assigned(dip);
return (PCICFG_SUCCESS);
}
/*
* Allocate memory for the existing
* assigned-addresses(s) plus one and then
* build it.
*/
/*
* Write out the new "assigned-addresses" spec
*/
"assigned-addresses", (int *)newreg,
/*
* Don't forget to free up memory from ddi_getlongprop
*/
(void) pcicfg_dump_assigned(dip);
return (PCICFG_SUCCESS);
}
static int
{
int rlen;
switch (status) {
case DDI_PROP_SUCCESS:
break;
case DDI_PROP_NO_MEMORY:
DEBUG0("ranges present, but unable to get memory\n");
return (PCICFG_FAILURE);
default:
DEBUG0("no ranges property - creating one\n");
sizeof (pcicfg_range_t)/sizeof (int))
!= DDI_SUCCESS) {
DEBUG0("Did'nt create ranges property\n");
return (PCICFG_FAILURE);
}
return (PCICFG_SUCCESS);
}
/*
* Allocate memory for the existing reg(s) plus one and then
* build it.
*/
/*
* Write out the new "ranges" property
*/
(rlen + sizeof (pcicfg_range_t))/sizeof (int));
return (PCICFG_SUCCESS);
}
static int
{
int rlen;
switch (status) {
case DDI_PROP_SUCCESS:
break;
case DDI_PROP_NO_MEMORY:
DEBUG0("reg present, but unable to get memory\n");
return (PCICFG_FAILURE);
default:
DEBUG0("no reg property\n");
return (PCICFG_FAILURE);
}
/*
* Allocate memory for the existing reg(s) plus one and then
* build it.
*/
/*
* Build the regspec, then add it to the existing one(s)
*/
if (reg_offset == PCI_CONF_ROM) {
hiword |= PCI_ADDR_MEM32;
} else {
hiword |= PCI_ADDR_MEM32;
} else if ((PCI_BASE_TYPE_M & regvalue)
== PCI_BASE_TYPE_ALL) {
hiword |= PCI_ADDR_MEM64;
}
} else {
hiword |= PCI_ADDR_IO;
}
}
addition.pci_phys_mid = 0;
addition.pci_phys_low = 0;
addition.pci_size_hi = 0;
/*
* Write out the new "reg" property
*/
(rlen + sizeof (pci_regspec_t))/sizeof (int));
return (PCICFG_SUCCESS);
}
static int
{
int alen;
DEBUG2("pcicfg_update_available_prop() - Address %lx Size %x\n",
switch (status) {
case DDI_PROP_SUCCESS:
break;
case DDI_PROP_NO_MEMORY:
DEBUG0("no memory for available property\n");
return (PCICFG_FAILURE);
default:
"available", (int *)newone,
sizeof (*newone)/sizeof (int));
return (PCICFG_SUCCESS);
}
/*
* Allocate memory for the existing available plus one and then
* build it.
*/
/* Write out the new "available" spec */
"available", (int *)new_avail,
/* Don't forget to free up memory from ddi_getlongprop */
return (PCICFG_SUCCESS);
}
static void
{
/*
* Enable memory, IO, and bus mastership
* XXX should we enable parity, SERR#,
* fast back-to-back, and addr. stepping?
*/
}
static void
{
/*
* Disable I/O and memory traffic through the bridge
*/
}
/*
* Setup the basic 1275 properties based on information found in the config
* header of the PCI device
*/
static int
{
int ret;
/* These two exists only for non-bridges */
return (ret);
}
return (ret);
}
}
/*
* These should always exist and have the value of the
* corresponding register value
*/
return (ret);
}
return (ret);
}
return (ret);
}
return (ret);
}
/* devsel-speed starts at the 9th bit */
return (ret);
}
/*
* The next three are bits set in the status register. The property is
* present (but with no value other than its own existence) if the bit
* is set, non-existent otherwise
*/
if ((!pcie_dev) &&
PCI_STAT_FBBC)) {
"fast-back-to-back", 0)) != DDI_SUCCESS) {
return (ret);
}
}
if ((!pcie_dev) &&
PCI_STAT_66MHZ)) {
"66mhz-capable", 0)) != DDI_SUCCESS) {
return (ret);
}
}
"udf-supported", 0)) != DDI_SUCCESS) {
return (ret);
}
}
/*
* These next three are optional and are not present
* if the corresponding register is zero. If the value
* is non-zero then the property exists with the value
* of the register.
*/
PCI_CONF_SUBVENID)) != 0) {
return (ret);
}
}
PCI_CONF_SUBSYSID)) != 0) {
return (ret);
}
}
PCI_CONF_CACHE_LINESZ)) != 0) {
return (ret);
}
}
/*
* If the Interrupt Pin register is non-zero then the
* interrupts property exists
*/
/*
* If interrupt pin is non-zero,
* record the interrupt line used
*/
return (ret);
}
}
/* if slot implemented, get physical slot number */
if (val) {
cap_ptr, PCIE_SLOTCAP) >>
!= DDI_SUCCESS) {
return (ret);
}
}
}
return (PCICFG_SUCCESS);
}
static int
{
int ret;
char device_type[8];
if (pcie_device_type)
else
return (ret);
}
return (ret);
}
return (ret);
}
/*
* Create primary-bus and secondary-bus properties to be used
* to restore bus numbers in the pcicfg_setup_bridge() routine.
*/
return (ret);
}
return (ret);
}
}
return (PCICFG_SUCCESS);
}
static int
{
int ret;
char *name;
char *compat[24];
int i;
int n;
/* set the property prefix based on the device type */
if (pcie_dev)
else
/*
* NOTE: These are for both a child and PCI-PCI bridge node
*/
/*
* "name" property rule
* --------------------
*
*
* | \svid |
* | \ |
* | \ |
* | ssid \ | =0 | != 0 |
* |------------|-----------------------|-----------------------|
* | | | |
* | =0 | vid,did | svid,ssid |
* | | | |
* |------------|-----------------------|-----------------------|
* | | | |
* | !=0 | svid,ssid | svid,ssid |
* | | | |
* |------------|-----------------------|-----------------------|
*
* where:
* vid = vendor id
* did = device id
* svid = subsystem vendor id
* ssid = subsystem id
*/
} else {
}
/*
* In some environments, trying to use "generic" 1275 names is
* not the convention. In those cases use the name as created
* above. In all the rest of the cases, check to see if there
* is a generic name first.
*/
#ifdef _DONT_USE_1275_GENERIC_NAMES
#else
/*
* Set name to the above fabricated name
*/
}
#endif
/*
* The node name field needs to be filled in with the name
*/
DEBUG0("Failed to set nodename for node\n");
return (PCICFG_FAILURE);
}
/*
* Create the compatible property as an array of pointers
* to strings. Start with the buffer created above.
*/
n = 0;
/*
* Setup 'compatible' as per the PCI2.1 bindings document.
* pci[ex]VVVV,DDDD.SSSS.ssss.RR
* pci[ex]VVVV,DDDD.SSSS.ssss
* pciSSSS.ssss -> not created for PCIe as per PCIe bindings
* pci[ex]VVVV,DDDD.RR
* pci[ex]VVVV,DDDD
* pci[ex]class,CCSSPP
* pci[ex]class,CCSS
*/
/* pci[ex]VVVV,DDDD.SSSS.ssss.RR */
/* pci[ex]VVVV,DDDD.SSSS.ssss */
/* pciSSSS.ssss -> not created for PCIe as per PCIe bindings */
if (!pcie_dev) {
}
/* pci[ex]VVVV,DDDD.RR */
/* pci[ex]VVVV,DDDD */
/* pci[ex]class,CCSSPP */
/* pci[ex]class,CCSS */
return (ret);
}
for (i = 0; i < n; i++) {
}
DEBUG0("pcicfg_set_childnode_props - Unable to create name "
"property\n");
return (ret);
}
return (PCICFG_SUCCESS);
}
/*
* Program the bus numbers into the bridge
*/
static void
{
/*
* Primary bus#
*/
/*
* Secondary bus#
*/
/*
* Subordinate bus#
*/
}
/*
* Put bridge registers into initial state
*/
static void
{
/*
* The highest bus seen during probing is the max-subordinate bus
*/
/*
* If there exists more than 1 downstream bridge, it
* will be reset by the below secondary bus reset which
* will clear the bus numbers assumed to be programmed in
* the pcicfg_probe_children() routine. We therefore restore
* them here.
*/
} else {
%s%d: pbus = 0x%x, sbus = 0x%x",
sbus);
}
}
/*
* Reset the secondary bus
*/
drv_usecwait(100);
/*
* Program the memory base register with the
* start of the memory range
*/
/*
* Program the I/O base register with the start of the I/O range
*/
/*
* Clear status bits
*/
/*
* Turn off prefetchable range
*/
/*
* Needs to be set to this value
*/
/*
* After a Reset, we need to wait 2^25 clock cycles before the
* first Configuration access. The worst case is 33MHz, which
* is a 1 second wait.
*/
}
static void
{
/*
* Program the memory limit register with the end of the memory range
*/
DEBUG1("DOWN ROUNDED ===>[0x%x]\n",
PCICFG_MEMGRAN))));
/*
* Since this is a bridge, the rest of this range will
* be responded to by the bridge. We have to round up
* so no other device claims it.
*/
DEBUG1("Added [0x%x]at the top of "
"the bridge (mem)\n", length);
}
/*
* Program the I/O limit register with the end of the I/O range
*/
PCICFG_IOGRAN)))));
PCICFG_IOGRAN))));
/*
* Same as above for I/O space. Since this is a
* bridge, the rest of this range will be responded
* to by the bridge. We have to round up so no
* other device claims it.
*/
DEBUG1("Added [0x%x]at the top of "
"the bridge (I/O)\n", length);
}
}
/*ARGSUSED*/
static void
{
/* disable SERR generated in the context of Master Aborts. */
val &= ~PCI_COMM_SERR_ENABLE;
/* clear any current pending errors */
/* if we are a PCIe device, disable the generation of UR, CE and NFE */
return;
}
}
/*ARGSUSED*/
static void
{
/* clear any pending errors */
/* restore original settings */
}
}
static int
{
int i;
int ret;
/*
* This node will be put immediately below
* "parent". Allocate a blank device node. It will either
* be filled in or freed up based on further probing.
*/
/*
* ndi_devi_alloc() is called as ndi_devi_alloc_sleep()
*/
!= NDI_SUCCESS) {
DEBUG0("pcicfg_probe_children(): Failed to alloc child node\n");
return (PCICFG_FAILURE);
}
DEBUG0("pcicfg_probe_children():"
"Failed to add candidate REG\n");
goto failedconfig;
}
!= PCICFG_SUCCESS) {
if (ret == PCICFG_NODEVICE) {
(void) ndi_devi_free(new_child);
return (ret);
}
DEBUG0("pcicfg_probe_children():"
"Failed to setup config space\n");
goto failedconfig;
}
/*
* As soon as we have access to config space,
* turn off device. It will get turned on
* later (after memory is assigned).
*/
(void) pcicfg_device_off(config_handle);
/* check if we are PCIe device */
== DDI_SUCCESS) {
DEBUG0("PCIe device detected\n");
pcie_dev = 1;
}
/*
* Set 1275 properties common to all devices
*/
pcie_dev) != PCICFG_SUCCESS) {
DEBUG0("Failed to set standard properties\n");
goto failedchild;
}
/*
* Child node properties NOTE: Both for PCI-PCI bridge and child node
*/
pcie_dev) != PCICFG_SUCCESS) {
goto failedchild;
}
/*
* If this is not a multi-function card only probe function zero.
*/
(void) pcicfg_config_teardown(&config_handle);
(void) ndi_devi_free(new_child);
return (PCICFG_NODEVICE);
}
DEBUG1("---Vendor ID = [0x%x]\n",
DEBUG1("---Device ID = [0x%x]\n",
/*
* Attach the child to its parent
*/
DEBUG3("--Bridge found bus [0x%x] device"
(void) pcicfg_free_bridge_resources(new_child);
goto failedchild;
}
} else {
DEBUG3("--Leaf device found bus [0x%x] device"
"[0x%x] func [0x%x]\n",
i = PCI_CONF_BASE0;
while (i <= PCI_CONF_BASE5) {
/*
* If its a zero length, don't do
* any programming.
*/
if (request != 0) {
/*
* Add to the "reg" property
*/
request, i) != PCICFG_SUCCESS) {
goto failedchild;
}
} else {
DEBUG1("BASE register [0x%x] asks for "
"[0x0]=[0x0](32)\n", i);
i += 4;
continue;
}
/*
* Increment by eight if it is 64 bit address space
*/
DEBUG3("BASE register [0x%x] asks for "
"[0x%x]=[0x%x] (64)\n",
i, request,
i += 8;
} else {
DEBUG3("BASE register [0x%x] asks for "
"[0x%x]=[0x%x](32)\n",
i, request,
i += 4;
}
}
/*
* Get the ROM size and create register for it
*/
/*
* If its a zero length, don't do
* any programming.
*/
if (request != 0) {
DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]\n",
/*
* Add to the "reg" property
*/
goto failedchild;
}
}
/* now allocate & program the resources */
(void) pcicfg_free_device_resources(new_child);
goto failedchild;
}
(void) ndi_devi_bind_driver(new_child, 0);
}
(void) pcicfg_config_teardown(&config_handle);
return (PCICFG_SUCCESS);
(void) pcicfg_config_teardown(&config_handle);
(void) ndi_devi_free(new_child);
return (PCICFG_FAILURE);
}
static int
{
int ret;
ddi_acc_handle_t h, ph;
int error = 0;
extern int pcicfg_dont_interpret;
#ifdef PCICFG_INTERPRET_FCODE
struct pci_ops_bus_args po;
fco_handle_t c;
char unit_address[64];
int fcode_size = 0;
#endif
/*
* check if our parent is of type pciex.
* if so, program config space to disable error msgs during probe.
*/
== DDI_SUCCESS) {
/*
* disable parent generating URs or SERR#s during probing
* alone.
*/
return (DDI_FAILURE);
}
/*
* This node will be put immediately below
* "parent". Allocate a blank device node. It will either
* be filled in or freed up based on further probing.
*/
!= NDI_SUCCESS) {
DEBUG0("pcicfg_fcode_probe(): Failed to alloc child node\n");
/* return (PCICFG_FAILURE); */
goto failed2;
}
/*
* Create a dummy reg property. This will be replaced with
* a real reg property when fcode completes or if we need to
* produce one by hand.
*/
goto failed3;
}
#ifdef EFCODE21554
!= PCICFG_SUCCESS) {
DEBUG0("pcicfg_fcode_probe():"
"Failed to setup config space\n");
goto failed3;
}
#else
p.pci_phys_mid = p.pci_phys_low = 0;
p.pci_size_hi = p.pci_size_low = 0;
/*
* Map in configuration space (temporarily)
*/
DEBUG0("pcicfg_fcode_probe():"
"Failed to setup config space\n");
goto failed3;
}
/*
* First use ddi_peek16 so that if there is not a device there,
* a bus error will not cause a panic.
*/
v = virt + PCI_CONF_VENID;
DEBUG0("Can not read Vendor ID");
pcicfg_unmap_phys(&h, &p);
goto failed3;
}
#endif
DEBUG0("fcode_probe: conf space mapped.\n");
/*
* As soon as we have access to config space,
* turn off device. It will get turned on
* later (after memory is assigned).
*/
(void) pcicfg_device_off(h);
/* check if we are PCIe device */
== DDI_SUCCESS) {
/*EMPTY*/
}
/*
* Set 1275 properties common to all devices
*/
DEBUG0("Failed to set standard properties\n");
goto failed;
}
/*
* Child node properties NOTE: Both for PCI-PCI bridge and child node
*/
goto failed;
}
/*
* If this is not a multi-function card only probe function zero.
*/
goto failed;
}
/*
* XXX - Transparent bridges are handled differently
* than other devices with regards to fcode. Since
* no transparent bridge currently ships with fcode,
* there is no reason to try to extract it from its rom
* or call the fcode interpreter to try to load a drop-in.
* If fcode is developed to handle transparent bridges,
* this code will have to change.
*/
DEBUG3("--Bridge found bus [0x%x] device"
(void) pcicfg_free_bridge_resources(new_child);
goto done;
} else {
DEBUG3("--Leaf device found bus [0x%x] device"
"[0x%x] func [0x%x]\n",
/*
* link in tree, but don't bind driver
* We don't have compatible property yet
*/
if (pci_config_get8(h, PCI_CONF_IPIN)) {
}
#ifdef PCICFG_INTERPRET_FCODE
/*
* Some platforms (x86) don't run fcode, so don't interpret
* fcode that might be in the ROM.
*/
if (pcicfg_dont_interpret == 0) {
/* This platform supports fcode */
/*
* Get the ROM size and create register for it
*/
/*
* If its a zero length, don't do
* any programming.
*/
if (request != 0) {
/*
* Add resource to assigned-addresses.
*/
if (pcicfg_fcode_assign_bars(h, new_child,
!= PCICFG_SUCCESS) {
DEBUG0("Failed to assign addresses to "
"implemented BARs");
goto failed;
}
/* Turn device on */
(void) pcicfg_device_on(h);
/*
* Attempt to load fcode.
*/
/* Turn device off */
(void) pcicfg_device_off(h);
/*
* Free the ROM resources.
*/
(void) pcicfg_free_resource(new_child, p);
DEBUG2("configure: fcode addr %lx size %x\n",
/*
* Create the fcode-rom-offset property. The
* buffer containing the fcode always starts
* with 0xF1, so the fcode offset is zero.
*/
new_child, "fcode-rom-offset", 0)
!= DDI_SUCCESS) {
DEBUG0("Failed to create "
"fcode-rom-offset property\n");
goto failed;
}
} else {
DEBUG0("There is no Expansion ROM\n");
fcode_addr = NULL;
fcode_size = 0;
}
/*
* Fill in the bus specific arguments. For
* PCI, it is the config address.
*/
/*
* Build unit address.
*/
DEBUG3("pci_fc_ops_alloc_handle ap=%lx "
"new device=%lx unit address=%s\n",
DEBUG0("calling fcode_interpreter()\n");
DEBUG3("Before int DIP=%lx binding name %s major %d\n",
DEBUG1("returned from fcode_interpreter() - "
"returned %x\n", error);
/*
* We don't need the fcode anymore. While allocating
* we had rounded up to a page size.
*/
if (fcode_size) {
}
} else {
/* This platform does not support fcode */
DEBUG0("NOT calling fcode_interpreter()\n");
}
#endif /* PCICFG_INTERPRET_FCODE */
if ((error == 0) && (pcicfg_dont_interpret == 0)) {
/*
* The interpreter completed successfully.
* We need to redo the resources based on the new reg
* property.
*/
/*
* Readjust resources specified by reg property.
*/
if (pcicfg_alloc_new_resources(new_child) ==
goto failed;
}
/* no fcode, bind driver now */
(void) ndi_devi_bind_driver(new_child, 0);
goto done;
} else if ((error != FC_NO_FCODE) &&
(pcicfg_dont_interpret == 0)) {
/*
* The interpreter located fcode, but had an error in
* processing. Cleanup and fail the operation.
*/
DEBUG0("Interpreter detected fcode failure\n");
(void) pcicfg_free_resources(new_child);
goto failed;
} else {
/*
* Either the interpreter failed with FC_NO_FCODE or we
* chose not to run the interpreter
* (pcicfg_dont_interpret).
*
* If the interpreter failed because there was no
* dropin, then we need to probe the device ourself.
*/
/*
* Free any resources that may have been assigned
* to start over.
*/
(void) pcicfg_free_resources(new_child);
#ifdef EFCODE21554
#else
pcicfg_unmap_phys(&h, &p);
#endif
(void) ndi_devi_free(new_child);
DEBUG0("No Drop-in Probe device ourself\n");
if (ret != PCICFG_SUCCESS) {
DEBUG0("Could not self probe child\n");
goto failed2;
}
/*
* We successfully self probed the device.
*/
if ((new_child = pcicfg_devi_find(
DEBUG0("Did'nt find device node "
"just created\n");
goto failed2;
}
#ifdef EFCODE21554
/*
* Till now, we have detected a non transparent bridge
* (ntbridge) as a part of the generic probe code and
* configured only one configuration
* header which is the side facing the host bus.
* Now, configure the other side and create children.
*
* To make the process simpler, lets load the device
* driver for the non transparent bridge as this is a
* Solaris bundled driver, and use its configuration map
* services rather than programming it here.
* If the driver is not bundled into Solaris, it must be
* first loaded and configured before performing any
* hotplug operations.
*
* This not only makes the code simpler but also more
* generic.
*
* So here we go.
*/
DEBUG0("Found nontransparent bridge.\n");
}
if (ret != PCICFG_SUCCESS) {
/*
* Bridge configure failed. Free up the self
* probed entry. The bus resource allocation
* maps need to be cleaned up to prevent
* warnings on retries of the failed configure.
*/
(void) pcicfg_ntbridge_unconfigure(new_child);
(void) pcicfg_teardown_device(new_child);
}
#endif
goto done2;
}
}
done:
#ifdef EFCODE21554
#else
pcicfg_unmap_phys(&h, &p);
#endif
if (ret != PCICFG_SUCCESS)
(void) ndi_devi_free(new_child);
if (parent_regs.pcie_dev) {
}
return (ret);
}
static int
{
int rval, i, j;
int bus_range[2];
int count;
uint8_t pcie_device_type = 0;
req.ra_boundbase = 0;
if (rval != NDI_SUCCESS) {
if (rval == NDI_RA_PARTIAL_REQ) {
/*EMPTY*/
DEBUG0("NDI_RA_PARTIAL_REQ returned for bus range\n");
} else {
"Failed to allocate bus range for bridge\n");
return (PCICFG_FAILURE);
}
}
DEBUG2("Bus Range Allocated [base=%d] [len=%d]\n",
== NDI_FAILURE) {
DEBUG0("Can not setup resource map - NDI_RA_TYPE_PCI_BUSNUM\n");
return (PCICFG_FAILURE);
}
/*
* Put available bus range into the pool.
* Take the first one for this bridge to use and don't give
* to child.
*/
/* Keep track of highest bus for subordinate bus programming */
*highest_bus = new_bus;
/*
* Allocate Memory Space for Bridge
*/
req.ra_boundbase = 0;
/*
* Note: To support a 32b system, boundlen and len need to be
* 32b quantities
*/
if (rval != NDI_SUCCESS) {
if (rval == NDI_RA_PARTIAL_REQ) {
/*EMPTY*/
DEBUG0("NDI_RA_PARTIAL_REQ returned\n");
} else {
"Failed to allocate memory for bridge\n");
return (PCICFG_FAILURE);
}
}
DEBUG3("Bridge Memory Allocated [0x%x.%x] len [0x%x]\n",
mem_alen);
DEBUG0("Can not setup resource map - NDI_RA_TYPE_MEM\n");
return (PCICFG_FAILURE);
}
/*
* Put available memory into the pool.
*/
/*
* Allocate I/O Space for Bridge
*/
req.ra_boundbase = 0;
if (rval != NDI_SUCCESS) {
if (rval == NDI_RA_PARTIAL_REQ) {
/*EMPTY*/
DEBUG0("NDI_RA_PARTIAL_REQ returned\n");
} else {
DEBUG0("Failed to allocate io space for bridge\n");
/* return (PCICFG_FAILURE); */
}
}
if (io_alen) {
DEBUG3("Bridge IO Space Allocated [0x%x.%x] len [0x%x]\n",
io_alen);
NDI_FAILURE) {
DEBUG0("Can not setup resource map - NDI_RA_TYPE_IO\n");
return (PCICFG_FAILURE);
}
/*
* Put available I/O into the pool.
*/
}
DEBUG0("Failed to set bus-range property");
return (PCICFG_FAILURE);
}
/*
* Reset the secondary bus
*/
drv_usecwait(100);
/*
* Program the memory base register with the
* start of the memory range
*/
/*
* Program the memory limit register with the
* end of the memory range.
*/
/*
* Allocate the chunk of memory (if any) not programmed into the
* bridge because of the round down.
*/
!= (mem_answer + mem_alen)) {
DEBUG0("Need to allocate Memory round off chunk\n");
}
/*
* Program the I/O Space Base
*/
PCICFG_LOADDR(io_answer))));
/*
* Program the I/O Space Limit
*/
PCICFG_IOGRAN)))) - 1);
- 1);
/*
* Allocate the chunk of I/O (if any) not programmed into the
* bridge because of the round down.
*/
DEBUG0("Need to allocate I/O round off chunk\n");
}
/*
* Clear status bits
*/
/*
* Turn off prefetchable range
*/
/*
* Needs to be set to this value
*/
/* check our device_type as defined by Open Firmware */
pcie_device_type = 1;
/*
* Set bus properties
*/
DEBUG0("Failed to set busnode props\n");
return (PCICFG_FAILURE);
}
(void) pcicfg_device_on(h);
!= NDI_SUCCESS) {
DEBUG0("Unable to online bridge\n");
return (PCICFG_FAILURE);
}
DEBUG0("Bridge is ONLINE\n");
/*
* After a Reset, we need to wait 2^25 clock cycles before the
* first Configuration access. The worst case is 33MHz, which
* is a 1 second wait.
*/
/*
* Probe all children devices
*/
DEBUG0("Bridge Programming Complete - probe children\n");
for (i = 0; i < PCICFG_MAX_DEVICE; i++) {
for (j = 0; j < PCICFG_MAX_FUNCTION; j++) {
new_bus, i, j, highest_bus))
!= PCICFG_SUCCESS) {
if (rval == PCICFG_NODEVICE) {
DEBUG3("No Device at bus [0x%x]"
"device [0x%x] "
"func [0x%x]\n", new_bus, i, j);
if (j)
continue;
} else {
DEBUG3("Failed to configure bus "
"[0x%x] device [0x%x] "
"func [0x%x]\n", new_bus, i, j);
}
break;
}
}
/* if any function fails to be configured, no need to proceed */
if (rval != PCICFG_NODEVICE) {
break;
}
}
/* if empty topology underneath, it is still a success. */
if (rval != PCICFG_FAILURE)
/*
* Offline the bridge to allow reprogramming of resources.
*/
DEBUG0("Failure summing resources\n");
return (PCICFG_FAILURE);
}
DEBUG3("Start of Unallocated Bridge(%d slots) Resources "
/*
* if the bridge a slots, then preallocate. If not, assume static
* configuration. Also check for preallocation limits and spit
* warning messages appropriately (perhaps some can be in debug mode).
*/
if (num_slots) {
#ifdef DEBUG
DEBUG3("Memory space consumed by bridge"
" more than planned for %d slot(s)(%lx, %lx)",
DEBUG3("IO space consumed by bridge"
" more than planned for %d slot(s)(%lx, %lx)",
if (*highest_bus > highest_bus_reqd)
DEBUG3("Buses consumed by bridge"
" more than planned for %d slot(s)(%x, %x)",
DEBUG3("Memory space required by bridge"
" more than available for %d slot(s)(%lx, %lx)",
DEBUG3("IO space required by bridge"
" more than available for %d slot(s)(%lx, %lx)",
if (highest_bus_reqd > max_bus)
DEBUG3("Bus numbers required by bridge"
" more than available for %d slot(s)(%x, %x)",
#endif
mem_end);
*highest_bus);
DEBUG3("mem_end %lx, io_end %lx, highest_bus %x\n",
if (io_size > 0) {
DEBUG0("Failed to update available prop "
"(io)\n");
return (PCICFG_FAILURE);
}
}
if (mem_size > 0) {
DEBUG0("Failed to update available prop "
"(memory)\n");
return (PCICFG_FAILURE);
}
}
}
/*
* Give back unused memory space to parent.
*/
if (mem_end == mem_answer) {
DEBUG0("No memory resources used\n");
/*
* To prevent the bridge from forwarding any Memory
* transactions, the Memory Limit will be programmed
* with a smaller value than the Memory Base.
*/
pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 0);
mem_size = 0;
} else {
/*
* Reprogram the end of the memory.
*/
}
/*
* Give back unused io space to parent.
*/
DEBUG0("No IO Space resources used\n");
/*
* To prevent the bridge from forwarding any I/O
* transactions, the I/O Limit will be programmed
* with a smaller value than the I/O Base.
*/
pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 0);
pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 0);
pci_config_put16(h, PCI_BCNF_IO_BASE_HI, 0);
io_size = 0;
} else {
/*
* Reprogram the end of the io space.
*/
}
if ((max_bus - *highest_bus) > 0) {
/*
* Give back unused bus numbers
*/
}
/*
* Remove the bus-range property if it exists since we will create
* a new one.
*/
/*
* Set bus numbers to ranges encountered during scan
*/
DEBUG0("Failed to set bus-range property");
return (PCICFG_FAILURE);
}
/*
* Remove the ranges property if it exists since we will create
* a new one.
*/
DEBUG2("Creating Ranges property - Mem Address %lx Mem Size %x\n",
DEBUG2(" - I/O Address %lx I/O Size %x\n",
if (io_size > 0) {
DEBUG0("Failed to update ranges (io)\n");
return (PCICFG_FAILURE);
}
}
if (mem_size > 0) {
DEBUG0("Failed to update ranges (memory)\n");
return (PCICFG_FAILURE);
}
}
/*
* Remove the resource maps for the bridge since we no longer
* need them. Note that the failure is ignored since the
* ndi_devi_offline above may have already taken care of it via
* driver detach.
* It has been checked that there are no other reasons for
* failure other than map itself being non-existent. So we are Ok.
*/
/*EMPTY*/
DEBUG0("Can not destroy resource map - NDI_RA_TYPE_MEM\n");
}
/*EMPTY*/
DEBUG0("Can not destroy resource map - NDI_RA_TYPE_IO\n");
}
== NDI_FAILURE) {
/*EMPTY*/
DEBUG0("Can't destroy resource map - NDI_RA_TYPE_PCI_BUSNUM\n");
}
return (rval);
}
/*
* Return PCICFG_SUCCESS if device exists at the specified address.
* Return PCICFG_NODEVICE is no device exists at the specified address.
*
*/
int
{
int status;
int rlen;
int ret = DDI_SUCCESS;
/*
* flags = PCICFG_CONF_INDIRECT_MAP if configuration space is indirectly
* mapped, otherwise it is 0. "flags" is introduced in support of any
* non transparent bridges, where configuration space is indirectly
* mapped.
* Indirect mapping is always true on sun4v systems.
*/
int flags = 0;
/*
* Get the pci register spec from the node
*/
switch (status) {
case DDI_PROP_SUCCESS:
break;
case DDI_PROP_NO_MEMORY:
DEBUG0("reg present, but unable to get memory\n");
return (PCICFG_FAILURE);
default:
DEBUG0("no reg property\n");
return (PCICFG_FAILURE);
}
/*
* Map in configuration space (temporarily)
*/
#ifdef EFCODE21554
#else
!= DDI_SUCCESS)
#endif
{
DEBUG0("pcicfg_config_setup():"
"Failed to setup config space\n");
return (PCICFG_FAILURE);
}
if (flags & PCICFG_CONF_INDIRECT_MAP) {
/*
* need to use DDI interfaces as the conf space is
* cannot be directly accessed by the host.
*/
} else {
}
if (ret == DDI_SUCCESS) {
if (tmp == -1) {
} else {
/* XXX - Need to check why HV is returning 0 */
if (tmp == 0) {
DEBUG0("Device Not Ready yet ?");
} else {
}
}
} else {
DEBUG0("ddi_peek failed, must be NODEVICE\n");
}
/*
* A bug in XMITS 3.0 causes us to miss the Master Abort Split
* Completion message. The result is the error message being
* sent back as part of the config data. If the first two words
* of the config space happen to be the same as the Master Abort
* message, then report back that there is no device there.
*/
#define PCICFG_PCIX_SCM 0x10000004
pcix_scm = 0;
if (pcix_scm == PCICFG_PCIX_SCM) {
pcix_scm = 0;
(void) ddi_peek32(dip,
if (pcix_scm == PCICFG_PCIX_SCM)
}
}
if (ret == PCICFG_NODEVICE)
#ifdef EFCODE21554
#else
#endif
return (ret);
}
static void
{
(void) ddi_regs_map_free(handle);
}
static int
{
}
static int
{
int length;
int rcount;
int i;
&length) != DDI_PROP_SUCCESS) {
DEBUG0("Failed to read assigned-addresses property\n");
return (PCICFG_FAILURE);
}
for (i = 0; i < rcount; i++) {
DEBUG4("pcicfg_dump_assigned - size=%x low=%x mid=%x high=%x\n",
}
/*
* Don't forget to free up memory from ddi_getlongprop
*/
return (PCICFG_SUCCESS);
}
#ifdef PCICFG_INTERPRET_FCODE
static int
{
int pci_data;
int start_of_fcode;
int image_length;
int code_type;
#ifdef DEBUG
int i;
#endif
DEBUG4("pcicfg_load_fcode() - "
"bus %x device =%x func=%x rom_paddr=%lx\n",
DEBUG2("pcicfg_load_fcode() - vendor_id=%x device_id=%x\n",
*fcode_size = 0;
*fcode_addr = NULL;
func, PCI_CONF_ROM);
p.pci_phys_mid = 0;
p.pci_phys_low = 0;
p.pci_size_low = rom_size;
p.pci_size_hi = 0;
return (PCICFG_FAILURE);
}
/*
* Walk the ROM to find the proper image for this device.
*/
image_not_found = 1;
while (image_not_found) {
#ifdef DEBUG
if (pcicfg_dump_fcode) {
for (i = 0; i < 100; i++)
DEBUG2("ROM 0x%x --> 0x%x\n", i,
}
#endif
/*
* Some device say they have an Expansion ROM, but do not, so
* for non-21554 devices use peek so we don't panic due to
* accessing non existent memory.
*/
} else {
if (ddi_peek16(dip,
"PCI Expansion ROM is not accessible");
pcicfg_unmap_phys(&h, &p);
return (PCICFG_FAILURE);
}
}
/*
* Validate the ROM Signature.
*/
pcicfg_unmap_phys(&h, &p);
return (PCICFG_FAILURE);
}
DEBUG0("Valid ROM Signature Found\n");
addr);
/*
* Validate the PCI Data Structure Signature.
* 0x52494350 = "PCIR"
*/
DEBUG0("Invalid PCI Data Structure Signature\n");
pcicfg_unmap_phys(&h, &p);
return (PCICFG_FAILURE);
}
DEBUG0("Invalid PCI Data Structure Signature\n");
pcicfg_unmap_phys(&h, &p);
return (PCICFG_FAILURE);
}
DEBUG0("Invalid PCI Data Structure Signature\n");
pcicfg_unmap_phys(&h, &p);
return (PCICFG_FAILURE);
}
DEBUG0("Invalid PCI Data Structure Signature\n");
pcicfg_unmap_phys(&h, &p);
return (PCICFG_FAILURE);
}
/*
* Is this image for this device?
*/
vendor_id_img = ddi_get16(h,
device_id_img = ddi_get16(h,
DEBUG2("This image is for vendor_id=%x device_id=%x\n",
switch (code_type) {
case PCI_PDS_CODE_TYPE_PCAT:
break;
DEBUG0("ROM is of Open Firmware Type\n");
break;
default:
break;
}
if ((vendor_id_img != vendor_id) ||
(device_id_img != device_id) ||
(code_type != PCI_PDS_CODE_TYPE_OPEN_FW)) {
DEBUG0("Firmware Image is not for this device..."
"goto next image\n");
/*
* Read indicator byte to see if there is another
* image in the ROM
*/
if (indicator != 1) {
/*
* There is another image in the ROM.
*/
addr += image_length;
} else {
/*
* There are no more images.
*/
DEBUG0("There are no more images in the ROM\n");
pcicfg_unmap_phys(&h, &p);
return (PCICFG_FAILURE);
}
} else {
DEBUG0("Correct image was found\n");
image_not_found = 0; /* Image was found */
}
}
/*
* Allocate page aligned buffer space
*/
if (*fcode_addr == NULL) {
DEBUG0("kmem_zalloc returned NULL\n");
pcicfg_unmap_phys(&h, &p);
return (PCICFG_FAILURE);
}
pcicfg_unmap_phys(&h, &p);
return (PCICFG_SUCCESS);
}
static int
{
/*
* Assign values to all BARs so that it is safe to turn on the
* device for accessing the fcode on the PROM. On successful
* exit from this function, "assigned-addresses" are created
* for all BARs and ROM BAR is enabled. Also, rom_regspec is
* filled with the values that can be used to free up this
* resource later.
*/
int i;
/*
* Process the BARs.
*/
for (i = PCI_CONF_BASE0; i <= PCI_CONF_BASE5; ) {
pci_config_put32(h, i, 0xffffffff);
request = pci_config_get32(h, i);
/*
* Check if implemented
*/
if (request == 0) {
DEBUG1("pcicfg_fcode_assign_bars :"
"BASE register [0x%x] asks for 0(32)\n", i);
i += 4;
continue;
}
/*
* Build the phys_spec for this BAR
*/
DEBUG3("pcicfg_fcode_assign_bars :"
"BASE register [0x%x] asks for [0x%x]=[0x%x]\n",
hiword |= PCI_ADDR_MEM32;
} else if ((PCI_BASE_TYPE_M & request)
== PCI_BASE_TYPE_ALL) {
hiword |= PCI_ADDR_MEM64;
}
if (request & PCI_BASE_PREF_M)
hiword |= PCI_REG_PF_M;
} else {
hiword |= PCI_ADDR_IO;
}
phys_spec.pci_phys_mid = 0;
phys_spec.pci_phys_low = 0;
phys_spec.pci_size_hi = 0;
/*
* The following function
* - allocates address space
* - programs the BAR
* - adds an "assigned-addresses" property
*/
" for dev %s BASE register [0x%x]\n",
goto failure;
}
/*
* 64 bit, should be in memory space.
*/
i += 8;
} else {
/*
* 32 bit, either memory or I/O space.
*/
i += 4;
}
}
/*
* Handle ROM BAR. We do not use the common
* resource allocator function because we need to
* return reg spec to the caller.
*/
DEBUG3("BASE register [0x%x] asks for "
req.ra_boundbase = 0;
" for dev %s ROM BASE register\n",
goto failure;
}
DEBUG3("ROM addr = [0x%x.%x] len [0x%x]\n",
/*
* Assign address space and enable ROM.
*/
/*
* Add resource to assigned-addresses.
*/
if (fc_request & PCI_BASE_PREF_M)
phys_spec.pci_phys_mid = 0;
phys_spec.pci_size_hi = 0;
!= PCICFG_SUCCESS) {
" assigned-address property for dev %s\n",
goto failure;
}
/*
* Copy out the reg spec.
*/
*rom_regspec = phys_spec;
return (PCICFG_SUCCESS);
/*
* We came in with no "assigned-addresses".
* Free up the resources we may have allocated.
*/
(void) pcicfg_free_device_resources(dip);
return (PCICFG_FAILURE);
}
#endif /* PCICFG_INTERPRET_FCODE */
static int
{
int assigned_len;
int acount;
int i;
&assigned_len) != DDI_PROP_SUCCESS) {
DEBUG0("Failed to read assigned-addresses property\n");
return (PCICFG_FAILURE);
}
for (i = 0; i < acount; i++) {
/*
* Dont forget to free mem from ddi_getlongprop
*/
return (PCICFG_FAILURE);
}
}
/*
* Don't forget to free up memory from ddi_getlongprop
*/
if (assigned_len)
return (PCICFG_SUCCESS);
}
static int
{
int assigned_len, reg_len;
int i, j, alloc_size;
®_len) != DDI_PROP_SUCCESS) {
DEBUG0("Failed to read reg property\n");
return (PCICFG_FAILURE);
}
DEBUG2("pcicfg_alloc_new_resources() reg size=%x entries=%x\n",
&assigned_len) != DDI_PROP_SUCCESS) {
acount = 0;
} else {
}
/*
* For each address described by reg, search for it in the
* assigned-addresses property. If it does not exist, allocate
* resources for it. If it does exist, check the size in both.
* The size needs to be bigger of the two.
*/
for (i = 1; i < rcount; i++) {
for (j = 0; j < acount; j++) {
/*
* There is an exact match. Check size.
*/
DEBUG1("pcicfg_alloc_new_resources "
"- %x - MATCH\n",
reg[i].pci_phys_hi);
if (reg[i].pci_size_low >
assigned[j].pci_size_low) {
/*
* Fcode wants more.
*/
DEBUG3("pcicfg_alloc_new_resources"
" - %x - RESIZE"
" assigned 0x%x reg 0x%x\n",
assigned[j].pci_phys_hi,
assigned[j].pci_size_low,
reg[i].pci_size_low);
/*
* Free the old resource.
*/
(void) pcicfg_free_resource(dip,
assigned[j]);
} else {
DEBUG3("pcicfg_alloc_new_resources"
" - %x - ENOUGH"
" assigned 0x%x reg 0x%x\n",
assigned[j].pci_phys_hi,
assigned[j].pci_size_low,
reg[i].pci_size_low);
}
break;
}
/*
* Fcode may have set one or more of the
* NPT bits in phys.hi.
*/
DEBUG2("pcicfg_alloc_new_resources "
"- PARTIAL MATCH assigned 0x%x "
reg[i].pci_phys_hi);
/*
* Changing the SS bits is an error
*/
if (PCI_REG_ADDR_G(
assigned[j].pci_phys_hi) !=
DEBUG2("Fcode changing"
" SS bits of - 0x%x -"
}
/*
* We are going to allocate new resource.
* Free the old resource. Again, adjust
* the size to be safe.
*/
assigned[j].pci_size_low);
break;
}
}
/*
* We are allocating resources for one of three reasons -
* - Fcode wants a larger address space
* - It is a new "reg", it should be only ROM bar, but
* we don't do the checking.
*/
DEBUG1("pcicfg_alloc_new_resources : creating 0x%x\n",
reg[i].pci_phys_hi);
/*
* Dont forget to free mem from
* ddi_getlongprop
*/
if (acount != 0)
return (PCICFG_FAILURE);
}
}
}
/*
* Don't forget to free up memory from ddi_getlongprop
*/
if (acount != 0)
return (PCICFG_SUCCESS);
}
static int
{
int offset;
int assigned_len, entries, i;
&assigned_len) == DDI_PROP_SUCCESS) {
DEBUG0("pcicfg_alloc_resource - "
"searching assigned-addresses\n");
/*
* Walk through the assigned-addresses entries. If there is
* a match, there is no need to allocate the resource.
*/
for (i = 0; i < entries; i++) {
DEBUG1("pcicfg_alloc_resource - MATCH %x\n",
assigned[i].pci_phys_hi);
return (0);
}
}
}
/*
* Map in configuration space (temporarily)
*/
DEBUG0("Can not map in config space\n");
return (1);
}
request.ra_boundbase = 0;
/*
* Use size stored in phys_spec parameter.
*/
/* allocate memory space from the allocator */
!= NDI_SUCCESS) {
DEBUG0("(ROM)Failed to allocate 32b mem");
pcicfg_unmap_phys(&h, &config);
return (1);
}
DEBUG3("ROM addr = [0x%x.%x] len [0x%x]\n",
alen);
/* program the low word */
} else {
case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
/* allocate memory space from the allocator */
!= NDI_SUCCESS) {
DEBUG0("Failed to allocate 64b mem\n");
pcicfg_unmap_phys(&h, &config);
return (1);
}
DEBUG3("64 addr = [0x%x.%x] len [0x%x]\n",
alen);
/* program the low word */
/* program the high word with value zero */
v += 4;
/*
* currently support 32b address space
* assignments only.
*/
break;
case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
/* allocate memory space from the allocator */
!= NDI_SUCCESS) {
DEBUG0("Failed to allocate 32b mem\n");
pcicfg_unmap_phys(&h, &config);
return (1);
}
DEBUG3("32 addr = [0x%x.%x] len [0x%x]\n",
alen);
/* program the low word */
break;
case PCI_REG_ADDR_G(PCI_ADDR_IO):
/* allocate I/O space from the allocator */
!= NDI_SUCCESS) {
DEBUG0("Failed to allocate I/O\n");
pcicfg_unmap_phys(&h, &config);
return (1);
}
DEBUG3("I/O addr = [0x%x.%x] len [0x%x]\n",
alen);
break;
default:
DEBUG0("Unknown register type\n");
pcicfg_unmap_phys(&h, &config);
return (1);
} /* switch */
}
/*
* Now that memory locations are assigned,
* update the assigned address property.
*/
pcicfg_unmap_phys(&h, &config);
return (1);
}
pcicfg_unmap_phys(&h, &config);
return (0);
}
static int
{
int offset;
int l;
/*
* Map in configuration space (temporarily)
*/
DEBUG0("Can not map in config space\n");
return (1);
}
/*
* Use size stored in phys_spec parameter.
*/
l = phys_spec.pci_size_low;
/* free memory back to the allocator */
DEBUG0("(ROM)Can not free 32b mem");
pcicfg_unmap_phys(&h, &config);
return (1);
}
/* Unmap the BAR by writing a zero */
} else {
case PCI_REG_ADDR_G(PCI_ADDR_MEM64):
/* free memory back to the allocator */
l, NDI_RA_TYPE_MEM,
NDI_RA_PASS) != NDI_SUCCESS) {
DEBUG0("Can not free 64b mem");
pcicfg_unmap_phys(&h, &config);
return (1);
}
break;
case PCI_REG_ADDR_G(PCI_ADDR_MEM32):
/* free memory back to the allocator */
l, NDI_RA_TYPE_MEM,
NDI_RA_PASS) != NDI_SUCCESS) {
DEBUG0("Can not free 32b mem");
pcicfg_unmap_phys(&h, &config);
return (1);
}
break;
case PCI_REG_ADDR_G(PCI_ADDR_IO):
/* free I/O space back to the allocator */
l, NDI_RA_TYPE_IO,
NDI_RA_PASS) != NDI_SUCCESS) {
DEBUG0("Can not free I/O space");
pcicfg_unmap_phys(&h, &config);
return (1);
}
break;
default:
DEBUG0("Unknown register type\n");
pcicfg_unmap_phys(&h, &config);
return (1);
} /* switch */
}
/*
* Now that memory locations are assigned,
* update the assigned address property.
*/
pcicfg_unmap_phys(&h, &config);
return (1);
}
pcicfg_unmap_phys(&h, &config);
return (0);
}
static int
{
int alen, num_entries, i;
switch (status) {
case DDI_PROP_SUCCESS:
break;
case DDI_PROP_NO_MEMORY:
DEBUG0("no memory for assigned-addresses property\n");
return (1);
default:
DEBUG0("assigned-addresses property does not exist\n");
return (0);
}
/*
* Make a copy of old assigned-addresses property.
*/
if (status != DDI_PROP_SUCCESS) {
/*
* If "assigned-addresses" is retrieved from PROM, the
* ndi_prop_remove() will fail.
*/
DEBUG1("pcicfg_remove_assigned_prop: 0x%x not removed\n",
/*
* Free up allocated memory
*/
return (0);
}
/*
* Rebuild the assigned-addresses property.
*/
for (i = 0; i < num_entries; i++) {
(void) pcicfg_update_assigned_prop(dip,
&assigned_copy[i]);
}
}
/*
* Free the copy of the original assigned-addresses.
*/
/*
* Don't forget to free up memory from ddi_getlongprop
*/
return (0);
}
static int
{
int result;
hp->ah_rnumber = 0;
if (result != DDI_SUCCESS) {
} else {
}
return (result);
}
void
{
}
#ifdef DEBUG
static void
{
if (pcicfg_debug == 1) {
prom_printf("pcicfg: ");
} else
if (pcicfg_debug)
}
#endif