stp4020_var.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1995-1999 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _STP4020_VAR_H
#define _STP4020_VAR_H
#pragma ident "%W% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#define DRT_REG_SETS 8
struct drt_window {
int drtw_flags;
/* XXX int drtw_status; XXX */
int drtw_ctl0;
int drtw_speed; /* unprocessed speed */
int drtw_len;
};
#define DRW_ENABLED 0x04
struct stpramap {
};
typedef struct stpra_request {
/* general flags */
/* length of resource */
/* specific address */
/* address mask */
/* bounds on addresses */
/* alignment mask */
#define STP_RA_ALIGN_MASK 0x0001
#define STP_RA_ALIGN_SIZE 0x0002
#define STP_RA_ALLOC_POW2 0x0020
#define STP_RA_ALLOC_SPECIFIED 0x0040
typedef struct stpra_return {
int ra_error;
typedef struct drt_socket {
int drt_flags;
int drt_state;
int drt_intmask;
int drt_vcc;
int drt_vpp1;
int drt_vpp2;
int drt_irq; /* high or low */
} drt_socket_t;
#define DRT_SOCKET_IO 0x01
#define DRT_CARD_ENABLED 0x02
#define DRT_CARD_PRESENT 0x04
#define DRT_BATTERY_DEAD 0x08
#define DRT_BATTERY_LOW 0x10
#define DRT_INTR_ENABLED 0x20
#define DRT_INTR_HIPRI 0x40
typedef
struct drtdev {
int pc_type;
int pc_numsockets;
int (*pc_callback)(); /* used to inform nexus of events */
int pc_cb_arg;
int pc_numpower;
struct power_entry *pc_power;
int pc_numintr;
} drt_dev_t;
#define PCF_CALLBACK 0x0001
#define PCF_INTRENAB 0x0002
#define DRT_DEFAULT_CTL_CAPS (0)
/*
* The following two defines are for CPR support
*/
#define DRT_SAVE_HW_STATE 1
#define DRT_RESTORE_HW_STATE 2
#ifdef __cplusplus
}
#endif
#endif /* _STP4020_VAR_H */