stp4020_reg.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1995-1999 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _STP4020_REG_H
#define _STP4020_REG_H
#pragma ident "%W% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* this is the header file that describes the registers for the STP4020,
* a PCMCIA bus controller that supports two Type-3 PCMCIA cards
*/
/*
* define some general constants that will probably never change
*/
/*
* PCMCIA ASIC Address Map
* define as constants for convenience
*/
#define DRMAP_PROM 0 /* the Forth PROM */
/*
* Socket interface control register definitions
*
* Each PCMCIA socket has two interface control registers and two inteface
* status registers associated with it.
*
* The interface control registers are used to specify the various interrupt
* enables, reset the PC card, perform various power management
* fucntions on the PC card, and control a few miscellaneous functions
* of the socket.
*
* The interface status registers are used to report the current status of
* various interrupt and status signals on the PC card and socket, as
* well as to clear pending interrupts by writing to the status bit
* that is set and indicating an interrupt. Note that some signals
* in interface status register 0 change meaning depending on whether
* the socket is configured for an interface type of memory-only or
* memory and I/O.
*/
/*
* bit definitions for socket interface control register 0
* note that bits 0x00020, 0x04000 and 0x08000 are reserved
*/
/*
* card status change interrupt level control; we can route a status
* change interrupt to one of two interrupt levels on the SBus
*/
#define DRT_SBM_DEFAULT (SBM_CD)
/*
* I/O (*IRQ) interrupt level control; we can route a PC card I/O interrupt
* to one of two interrupt levels on the SBus
*/
/*
* bit definitions for socket interface control register 1
* note that bit 0x00080 is reserved
*/
/*
* the Vpp controls are two-bit fields which specify which voltage
* should be switched onto Vpp for this socket
* both of the "no connect" states are equal
*/
/*
* Socket interface status register definitions
*
* bit definitions for socket interface status register 0 when
* the socket is in memory-only mode
*/
#define DRSTAT_PRESENT_OK DRSTAT_CD_MASK
#define DRSTAT_BATT_LOW DRSTAT_BVD2ST
/*
* additional bit definitions for socket interface status register 0 when
* the socket is in memory and I/O mode
*
* these are just alternate names for the bit definitions described for
* this register when the socket is in memory-only mode
*/
/*
* bit definitions for socket interface status register 1; these are
* valid no matter what mode the socket is in
*
* note that bits 0x0ffc0 are reserved
*/
#define DRSTAT_REV_S 0 /* STP4020 ASIC revision level bit shift */
/*
*
* Each PCMCIA socket has three windows associated with it; each of these
* windows can be programmed to map in either the AM, CM or IO space
* on the PC card. Each window can also be programmed with a
* starting or base address relative to the PC card's address zero.
* Each window is a fixed 1Mb in size.
*
* Each window has two window control registers associated with it to
* control the window's PCMCIA bus timing parameters, PC card address
* space that that window maps, and the base address in the
* selected PC card's address space.
*/
/*
* control registers
*
* The SET_XXX macros shift their normalized arguments to the correct
* position for the window control register and return the shifted
* value.
*
* The GET_XXX macros take a window control register value and return
* the appropriate normalized value.
*/
/*
* PC card window control register 0
* note that bit 0x08000 is reserved
*/
#define MEM_SPEED_MIN 100
#define MEM_SPEED_MAX 1370
/*
* the ASPSEL bits control which of the three PC card address spaces
* this window maps in
*/
#define DRWIN_BASE_S 0 /* base address bit shift */
#define ADDR2PAGE(x) ((x) >> 20)
/*
* PC card window control register 1
* note that bits 0x0ffe0 are reserved
*/
#define SET_DRWIN_WAITDLY(x) (((int)(x) << DRWIN_WAITDLY_S) & \
#define GET_DRWIN_WAITDLY(x) (((int)(x) & DRWIN_WAITDLY_M) >> \
#define DRWIN_WAITREQ_S 0 /* *WAIT signal is required bit shift */
#define SET_DRWIN_WAITREQ(x) (((int)(x) << DRWIN_WAITREQ_S) & \
#define GET_DRWIN_WAITREQ(x) (((int)(x) & DRWIN_WAITREQ_M) >> \
/*
* STP4020 CSR structures
*
* There is one stp4020_regs_t structure per instance, and it refers to
* the complete Stp4020 register set.
*
* For each socket, there is one stp4020_socket_csr_t structure, which
* refers to all the registers for that socket. That structure is
* made up of the window register structures as well as the registers
* that control overall socket operation.
*
* For each window, there is one stp4020_window_ctl_t structure, which
* refers to all the registers for that window.
*/
/*
* per-window CSR structure
*/
typedef struct stp4020_window_ctl_t {
/*
* per-socket CSR structure
*/
typedef struct stp4020_socket_csr_t {
/*
* per-instance CSR structure
*/
typedef struct stp4020_regs_t {
#ifdef __cplusplus
}
#endif
#endif /* _STP4020_REG_H */