socalreg.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* Copyright (c) 1995,1997-1998 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_SOCALREG_H
#define _SYS_SOCALREG_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* socalreg.h:
*
* SOC+ Register Definitions, Interface Adaptor to Fiber Channel
*/
#define N_SOCAL_NPORTS 2
/*
* Define the SOC+ configuration register bits.
*/
typedef union socal_cr_register {
struct cr {
} reg;
uint32_t w;
/*
* Define Configuration register bits.
*/
#define SOCAL_CR_SBUS_BURST_SIZE_MASK 0x007
#define SOCAL_CR_SBUS_BURST_SIZE_64BIT_MASK 0x700
#define SOCAL_CR_SBUS_BURST_SIZE_64BIT(a) \
(((a) & SOCAL_CR_SBUS_BURST_SIZE_64BIT_MASK) >> 8)
#define SOCAL_CR_BURST_4 0x0
#define SOCAL_CR_BURST_8 0x3
#define SOCAL_CR_BURST_16 0x4
#define SOCAL_CR_BURST_32 0x5
#define SOCAL_CR_BURST_64 0x6
#define SOCAL_CR_BURST_128 0x7
#define SOCAL_CR_SBUS_ENHANCED 0x08
#define SOCAL_CR_SBUS_PARITY_CHK 0x10
#define SOCAL_CR_SBUS_PARITY_TEST 0x20
#define SOCAL_CR_EEPROM_BANK_MASK 0x30000
#define SOCAL_CR_EXTERNAL_RAM_BANK_MASK 0x7000000
#define SOCAL_CR_EXTERNAL_RAM_BANK(a) \
(((a) & SOCAL_CR_EXTERNAL_RAM_BANK_MASK) >> 24)
/*
* Define SOC+ Slave Access Register.
*/
typedef union socal_sae_register {
struct sae {
} reg;
uint32_t w;
/*
* Define the Slave Access Regsiter Bits.
*/
#define SOCAL_SAE_PARITY_ERROR 0x01
#define SOCAL_SAE_UNSUPPORTED_TRANSFER 0x02
#define SOCAL_SAE_ALIGNMENT_ERROR 0x04
/*
* Define SOC+ Command and Status Register.
*/
typedef union socal_csr_register {
struct csr {
} reg;
uint32_t w;
/*
* Define SOC+ CSR Register Macros.
*/
#define SOCAL_CSR_ZEROS 0x00000070
#define SOCAL_CSR_SOCAL_TO_HOST 0x000f0000
#define SOCAL_CSR_HOST_TO_SOCAL 0x00000f00
#define SOCAL_CSR_SLV_ACC_ERR 0x00000080
#define SOCAL_CSR_INT_PENDING 0x00000008
#define SOCAL_CSR_NON_Q_CMD 0x00000004
#define SOCAL_CSR_IDLE 0x00000002
#define SOCAL_CSR_SOFT_RESET 0x00000001
#define SOCAL_CSR_1ST_S_TO_H 0x00010000
#define SOCAL_CSR_1ST_H_TO_S 0x00000100
#define SOCAL_CSR_RSP_QUE_1 0x00020000
#define SOCAL_CSR_RSP_QUE_2 0x00040000
#define SOCAL_CSR_RSP_QUE_3 0x00080000
#define SOCAL_CSR_REQ_QUE_1 0x00000200
#define SOCAL_CSR_REQ_QUE_2 0x00000400
#define SOCAL_CSR_REQ_QUE_3 0x00000800
/*
* Define SOC Interrupt Mask Register Bits.
*/
#define SOCAL_IMR_NON_QUEUED_STATE 0x04
#define SOCAL_IMR_SLAVE_ACCESS_ERROR 0x80
#define SOCAL_IMR_REQUEST_QUEUE_0 0x100
#define SOCAL_IMR_REQUEST_QUEUE_1 0x200
#define SOCAL_IMR_REQUEST_QUEUE_2 0x400
#define SOCAL_IMR_REQUEST_QUEUE_3 0x800
#define SOCAL_IMR_RESPONSE_QUEUE_0 0x10000
#define SOCAL_IMR_RESPONSE_QUEUE_1 0x20000
#define SOCAL_IMR_RESPONSE_QUEUE_2 0x40000
#define SOCAL_IMR_RESPONSE_QUEUE_3 0x80000
/*
* Define SOC+ Request Queue Index Register
*/
typedef union socal_reqp_register {
struct reqp {
} reg;
uint32_t w;
#define SOCAL_REQUESTQ0_MASK 0xff000000
#define SOCAL_REQUESTQ1_MASK 0x00ff0000
#define SOCAL_REQUESTQ2_MASK 0x0000ff00
#define SOCAL_REQUESTQ3_MASK 0x000000ff
#define SOCAL_REQUESTQ3_INDEX(a) ((a) & SOCAL_REQUESTQ3_MASK)
/*
* Define SOC+ Response Queue Index Register
*/
typedef union socal_rspp_register {
struct rspp {
} reg;
uint32_t w;
#define SOCAL_RESPONSEQ0_MASK 0xff000000
#define SOCAL_RESPONSEQ1_MASK 0x00ff0000
#define SOCAL_RESPONSEQ2_MASK 0x0000ff00
#define SOCAL_RESPONSEQ3_MASK 0x000000ff
#define SOCAL_RESPONSEQ3_INDEX(a) ((a) & SOCAL_RESPONSEQ3_MASK)
typedef struct _socalreg_ {
} socal_reg_t;
/*
* Device Address Space Offsets.
*/
#define SOCAL_XRAM_OFFSET 0x10000
#define SOCAL_XRAM_SIZE 0x10000
#define SOCAL_MAX_XCHG 1024
(((csr) & SOCAL_CSR_SOCAL_TO_HOST) | \
/*
* Bus dma burst sizes
*/
#ifndef BURSTSIZE
#define BURSTSIZE
#define BURST1 0x01
#define BURST2 0x02
#define BURST4 0x04
#define BURST8 0x08
#define BURST16 0x10
#define BURST32 0x20
#define BURST64 0x40
#define BURST128 0x80
#define BURSTSIZE_MASK 0xff
#endif /* BURSTSIZE */
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_SOCALREG_H */