/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1983, 1991, by Sun Microsystems, Inc.
*/
#ifndef _SYS_SER_ZSCC_H
#define _SYS_SER_ZSCC_H
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Zilog 8530 SCC Serial Communications Controller
*
* This is a dual uart chip with on-chip baud rate generators.
* It is about as brain-damaged as the typical modern uart chip,
* but it does have a lot of features as well as the usual lot of
* brain damage around addressing, write-onlyness, etc.
*/
#ifdef __cplusplus
extern "C" {
#endif
/*
* SCC registers:
*
* There are 16 write registers and 9 read registers in each channel.
* As usual, the two channels are ALMOST orthogonal, not exactly. Most regs
* can only be written to, or read, but not both. To access one, you must
* first write to register 0 with the number of the register you
* nobody interrupts you in between.
*/
/* bits in RR0 */
/* bits in RR1 */
/*
*
* NOTE that RR2 in channel A is unmodified, while in channel B it is
* modified by the current status of the UARTs. (This is independent
* of the setting of WR9_VIS.) If no interrupts are pending, the modified
* status is Channel B Special Receive. It can be written from
* either channel.
*/
/*
* bits in RR3 -- Interrupt Pending flags for both channels (this reg can
* only be read in Channel A, tho. Thanks guys.)
*/
/* bits in RR8 -- this is the same as reading the Data port */
/* bits in RR10 -- DPLL and SDLC Loop Mode status -- not entered */
/* Write register 0 -- common commands and Register Pointers */
/* bits in WR1 */
/* Also see R15 for individual enabs */
/* There are other Receive interrupt options defined, see data sheet. */
/* bits in WR3 */
/* bits in WR4 */
/* bits in WR5 */
/* bits in WR6 -- Sync characters or SDLC address field. */
/* bits in WR7 -- Sync character or SDLC flag */
/* bits in WR8 -- transmit buffer. Same as writing to data port. */
/*
* bits in WR9 -- Master interrupt control and reset. Accessible thru
* either channel, there's only one of them.
*/
/* bits in WR10 -- SDLC, NRZI, FM control bits */
/* bits in WR11 -- clock mode control */
/* bits in WR14 -- misc control bits, and DPLL control */
/*
* UART register addressing
*
* It would be nice if they used 4 address pins to address 15 registers,
* but they only used 1. So you have to write to the control port then
* read or write it; the 2nd cycle is done to whatever register number
* you wrote in the first cycle.
*
*/
#ifdef _KERNEL
struct zscc_device {
volatile unsigned char zscc_control;
volatile unsigned char :8; /* Filler */
volatile unsigned char zscc_data;
volatile unsigned char :8; /* Filler */
};
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_SER_ZSCC_H */