/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1996-1998 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_SCSI_ADAPTERS_FASREG_H
#define _SYS_SCSI_ADAPTERS_FASREG_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* FAS register definitions.
*/
/*
* All current Sun implementations use the following layout.
* That is, the FAS registers are always byte-wide, but are
* accessed longwords apart. Notice also that the byte-ordering
* is big-endian.
*/
struct fasreg {
};
/*
* FAS command register definitions
*/
/*
* These commands may be used at any time with the FAS chip.
* None generate an interrupt, per se, although if you have
* enabled detection of SCSI reset in setting the configuration
* register, a CMD_RESET_SCSI will generate an interrupt.
* Therefore, it is recommended that if you use the CMD_RESET_SCSI
* command, you at least temporarily disable recognition of
* SCSI reset in the configuration register.
*/
/*
* These commands will only work if the FAS is in the
* 'disconnected' state:
*/
/*
* These commands will only work if the FAS is connected as
* an initiator to a target:
*/
/*
* These commands will only work if the FAS is connected as
* a target to an initiator:
*/
/*
* DMA enable bit
*/
/*
* FAS fifo register definitions (read only)
*/
/*
* FAS status register definitions (read only)
*/
#define FAS_STAT_BITS \
"\20\10IPND\07GERR\06PERR\05XZERO\04XCMP\03MSG\02CD\01IO"
/*
* settings of status to reflect different information transfer phases
*/
#define FAS_PHASE_DATA_OUT 0
/*
* FAS interrupt status register definitions (read only)
*/
#define FAS_INT_BITS \
"\20\10RST\07ILL\06DISC\05BUS\04FCMP\03RESEL\02SATN\01SEL"
/*
* FAS step register- only the least significant 3 bits are valid
*/
/* Not MESSAGE OUT phase. ATN* asserted. */
/* (SELECT AND STOP command only). */
/* Sent one message byte. ATN* off. */
/* Not COMMAND phase. */
/* For SELECT WITHOUT ATN command: */
/* Not COMMAND phase. */
/* For SELECT WITH ATN3 command: */
/* Sent one to three message bytes. */
/* Stopped due to unexpected phase */
/* change. If third message byte */
/* not sent, ATN* asserted. */
/* due to premature phase change. */
/*
*/
/*
*/
/*
*/
/*
*/
/*
* FAS configuration #4 register definitions
*/
/*
* FAS part-unique id code definitions (read only)
*/
/*
* registers that constitute the FAS's counter register.
*/
}
/*
* to save time, read back 3 registers
*/
}
/*
* FAS Clock constants
*/
/*
* The probe routine will select amongst these values
* and stuff it into the tag f_clock_conv in the private host
* adapter structure (see below) (as well as the the register fas_clock_conv
* on the chip)
*/
/*
* This yields nanoseconds per input clock tick
*/
/*
*
* Time_unit = 7682 * CCF * Input_Clock_Period
*
* where Time_unit && Input_Clock_Period should be in the same units.
* CCF = Clock Conversion Factor from CLOCK_XMHZ above.
* Desired_Timeout_Period = 250 ms.
*
*/
/*
*/
/*
*/
(uint_t)1000
(uint_t)1000
/*
* We round up here to make sure that we are always slower
* (longer time period).
*/
/*
* According to the Emulex application notes for this part,
* the ability to receive synchronous data is independent
* of the FAS chip's input clock rate, and is fixed at
*
* Therefore, we could tell targets that we can *receive*
* synchronous data this fast.
* simple, we negotiate 200 ns
* On a c2, a period of 45 and 50 result in the same register value (8) and
*/
/*
* Short hand macro convert parameter in
* nanoseconds/byte into k-bytes/second.
*/
/*
* Default Synchronous offset.
* (max # of allowable outstanding REQ)
* IBS allows only 11 bytes offset
*/
/*
* Chip type defines && macros
*/
#define FAS366 0
/* status register #2 definitions (read only) */
/*
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_SCSI_ADAPTERS_FASREG_H */