espreg.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1996-1998 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_SCSI_ADAPTERS_ESPREG_H
#define _SYS_SCSI_ADAPTERS_ESPREG_H
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Hardware definitions for ESP (Enhanced SCSI Processor) generation chips.
*/
/*
* Include definition of DMA, DMA+, and ESC gate arrays
*/
#ifdef __cplusplus
extern "C" {
#endif
/*
* ESP register definitions.
*/
/*
* All current Sun implementations use the following layout.
* That is, the ESP registers are always byte-wide, but are
* accessed 32-bit words apart. Notice also that the byte-ordering
* is big-endian.
*/
struct espreg {
};
/*
* ESP command register definitions
*/
/*
* These commands may be used at any time with the ESP chip.
* None generate an interrupt, per se, although if you have
* enabled detection of SCSI reset in setting the configuration
* register, a CMD_RESET_SCSI will generate an interrupt.
* Therefore, it is recommended that if you use the CMD_RESET_SCSI
* command, you at least temporarily disable recognition of
* SCSI reset in the configuration register.
*/
#define CMD_NOP 0x0
#define CMD_FLUSH 0x1
#define CMD_RESET_ESP 0x2
#define CMD_RESET_SCSI 0x3
/*
* These commands will only work if the ESP is in the
* 'disconnected' state:
*/
#define CMD_RESEL_SEQ 0x40
#define CMD_SEL_NOATN 0x41
#define CMD_SEL_ATN 0x42
#define CMD_SEL_STOP 0x43
#define CMD_DIS_RESEL 0x45
/*
* These commands will only work if the ESP is connected as
* an initiator to a target:
*/
#define CMD_TRAN_INFO 0x10
#define CMD_COMP_SEQ 0x11
#define CMD_MSG_ACPT 0x12
#define CMD_TRAN_PAD 0x18
/*
* These commands will only work if the ESP is connected as
* a target to an initiator:
*/
/*
* DMA enable bit
*/
#define CMD_DMA 0x80
/*
* ESP fifo register definitions (read only)
*
* The first four bits are the count of bytes
* in the fifo.
*
* Bit 5 is a 'offset counter not zero' flag for
* the ESP100 only. On the ESP100A, the top 3 bits
* of the fifo register are the 3 bits of the Sequence
* Step register (if the ESP100A is not in TEST mode.
* If the ESP100A is in TEST mode, then bit 5 has
* the 'offset counter not zero' function). At least,
* so states the documentation.
*
*/
#define FIFOSIZE 16
#define ESP_FIFO_ONZ 0x20
/*
* ESP status register definitions (read only)
*/
#define ESP_STAT_BITS \
"\20\10IPND\07GERR\06PERR\05XZERO\04XCMP\03MSG\02CD\01IO"
/*
* settings of status to reflect different information transfer phases
*/
#define ESP_PHASE_DATA_OUT 0
#define ESP_PHASE_DATA_IN (ESP_STAT_IO)
#define ESP_PHASE_COMMAND (ESP_STAT_CD)
/*
* ESP interrupt status register definitions (read only)
*/
#define ESP_INT_BITS \
"\20\10RST\07ILL\06DISC\05BUS\04FCMP\03RESEL\02SATN\01SEL"
/*
* ESP step register- only the least significant 3 bits are valid
*/
#define ESP_STEP_MASK 0x7
#define ESP_STEP_ARBSEL 0 /* Arbitration and select completed. */
/* Not MESSAGE OUT phase. ATN* asserted. */
/* (SELECT AND STOP command only). */
/* Sent one message byte. ATN* off. */
/* Not COMMAND phase. */
/* For SELECT WITHOUT ATN command: */
/* Not COMMAND phase. */
/* For SELECT WITH ATN3 command: */
/* Sent one to three message bytes. */
/* Stopped due to unexpected phase */
/* change. If third message byte */
/* not sent, ATN* asserted. */
/* due to premature phase change. */
/*
*/
#define DEFAULT_HOSTID 7
/*
*/
/*
* (ESP100A, ESP200, or ESP236 only)
*/
/* (ESP-236 only) */
/* (ESP-236 only) */
/* (ESP200, ESP236 only) */
/* (ESP200, ESP236 only) */
/*
* (ESP236, FAS236, and FAS100A)
* Unfortunately, emulex has not been very consistent here
*/
/*
* ESP part-unique id code definitions (read only)
* (FAS236 and FAS100A only)
*/
/*
* registers that constitute the ESP's counter register.
*/
else \
else \
/*
* The counter is a 16 bit counter only for the ESP.
* If loaded with zero, it will do the full 64kb. If
* we define maxcount to be 64kb, then the low order
* 16 bits will be zero, and the register will be
* properly loaded.
* For FAS chips we can use the 24 bit counter
*/
#define ESP_MAX_DMACOUNT \
/*
* ESP Clock constants
*/
/*
* The probe routine will select amongst these values
* and stuff it into the tag e_clock_conv in the private host
* adapter structure (see below) (as well as the the register esp_clock_conv
* on the chip)
*/
#define CLOCK_10MHZ 2
#define CLOCK_15MHZ 3
#define CLOCK_20MHZ 4
#define CLOCK_25MHZ 5
#define CLOCK_30MHZ 6
#define CLOCK_35MHZ 7
#define CLOCK_MASK 0x7
/*
* This yields nanoseconds per input clock tick
*/
/*
*
* Time_unit = 7682 * CCF * Input_Clock_Period
*
* where Time_unit && Input_Clock_Period should be in the same units.
* CCF = Clock Conversion Factor from CLOCK_XMHZ above.
* Desired_Timeout_Period = 250 ms.
*
*/
#define ESP_CLOCK_DELAY 7682
#define ESP_CLOCK_TICK(esp) \
/*
*/
#define MIN_SYNC_SLOW(esp) \
#define SYNC_PERIOD_MASK 0x1F
/*
*/
#define MIN_SYNC_TIME(esp) \
(uint_t)1000
#define MAX_SYNC_TIME(esp) \
(uint_t)1000
/*
* We round up here to make sure that we are always slower
* (longer time period).
*/
/*
* According to the Emulex application notes for this part,
* the ability to receive synchronous data is independent
* of the ESP chip's input clock rate, and is fixed at
*
* Therefore, we could tell targets that we can *receive*
* synchronous data this fast.
* simple, we negotiate 200 ns
* On a c2, a period of 45 and 50 result in the same register value (8) and
*/
/*
* Short hand macro convert parameter in
* nanoseconds/byte into k-bytes/second.
*/
/*
* Default Synchronous offset.
* (max # of allowable outstanding REQ)
*/
#define DEFAULT_OFFSET 15
/*
* Chip type defines && macros
*/
#define ESP100 0
#define NCR53C90 0
#define ESP100A 1
#define NCR53C90A 1
#define ESP236 2
#define FAS100 3
#define FAS100A 3
#define FAS236 4
#define FAST 5
/*
* Compatibility hacks
*/
/* for STINGRAY && HYDRA. */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_SCSI_ADAPTERS_ESPREG_H */