i82586.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1991,1997-1998 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_I82586_H
#define _SYS_I82586_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* This is the number of bytes occupied by the 3E interface buffer.
*/
#define IE_TE_MEMSIZE 0x20000
/*
* There are 128 lines of 32 bytes wide IORAM on a Sun4/4XX.
*/
#define IE_IORAM_SIZE 0x1000
#define I82586ALIGN 4
/*
* Register definitions for the Sun 3E Ethernet board.
*
* The prefix for the 3E specific structures is tie (the t stands for
* three).
*
* Board ignores high order nibble of chip generated addresses.
* Reset chip: set tie_csr = TIE_RESET; delay 10us; set tie_csr = 0
*
* The address of the register is base + 0x1FF02.
* The address of the level 3 interrupt vector is base + 0x1FF12.
*/
#define SCSIREG 15
struct tie_device {
};
/*
* Register definitions for the Sun-4 On-board version of the
* Intel EDLC based Ethernet interface.
* Reset: write zeros to register. Must poll to check for OBIE_BUSERR
*/
/*
* System Configuration Pointer
* Must be at 0xFFFFF6 in chip's address space
*/
#define IESCPPAD 5
struct iescp {
};
/*
* Intermediate System Configuration Pointer
* Specifies base of all other control blocks and the offset of the SCB
*/
struct ieiscp {
};
/*
* The remaining chip data structures all start with a 16-bit status
* word. The meaning of the individual bits within a status word
* depends on the kind of descriptor or control block the word is
* embedded in. The driver accesses some status words only through
* their individual bits; others are accessed as words as well.
* These latter are defined as unions.
*/
/*
* System Control Block - the focus of communication
*/
struct iescb {
};
/* iescb_status */
/* IESCB_RUS */
/* IESCB_CUS */
#define IECUS_IDLE 0 /* not executing command */
/* iescb_cmd */
/*
* Command Unit data structures
*/
/*
* Generic command block
* Status word bits that are defined here have the
* same meaning for all command types. Bits not
* defined here don't have a common meaning.
*/
struct iecb {
};
/* iecb_status */
/* iecb_cmd */
/*
* CB commands (iecb_cmd)
*/
#define IE_NOP 0x0000
/*
* Individual address setup command block
*/
#define IEETHERADDRL 6
struct ieiaddr {
};
/*
* Maximum number of multicast addresses allowed per interface.
*/
#define IEMCADDRMAX 64
/*
* Multicast address setup command block
*/
struct iemcaddr {
};
/*
* Configure command
*/
struct ieconf {
};
/* ieconf_data0 */
/* ieconf_data1 */
/* ieconf_data2 */
/* ieconf_data3 */
/*
* Transmit frame descriptor ( Transmit command block )
*/
struct ietcb {
};
/* ietcb_status */
/* ietcb_command */
/*
* Transmit buffer descriptor
*/
struct ietbd {
};
/* ietbd_eofcnthi */
/*
* Receive Unit data structures
*/
/*
* Receive frame descriptor
*/
struct ierfd {
};
/* ierfd_status */
/* ierfd_command */
/*
* Receive buffer descriptor
*/
struct ierbd {
};
/* ierbd_status */
/* ierbd_elsize */
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_I82586_H */