hme_mac.h revision 85025c032d701094e5f35de4f42ce66082924fc1
45e9809aff7304721fddb95654901b32195c9c7avboxsync * CDDL HEADER START
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The contents of this file are subject to the terms of the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Common Development and Distribution License (the "License").
45e9809aff7304721fddb95654901b32195c9c7avboxsync * You may not use this file except in compliance with the License.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
45e9809aff7304721fddb95654901b32195c9c7avboxsync * See the License for the specific language governing permissions
45e9809aff7304721fddb95654901b32195c9c7avboxsync * and limitations under the License.
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45e9809aff7304721fddb95654901b32195c9c7avboxsync * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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45e9809aff7304721fddb95654901b32195c9c7avboxsync * CDDL HEADER END
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Use is subject to license terms.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#pragma ident "%Z%%M% %I% %E% SMI"
45e9809aff7304721fddb95654901b32195c9c7avboxsyncextern "C" {
45e9809aff7304721fddb95654901b32195c9c7avboxsync * HOST MEMORY DATA STRUCTURES
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* The pointers to the Descriptor Ring base Addresses must be 2K-byte aligned */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The transmit and receiver Descriptor Rings are organized as "wrap-around
45e9809aff7304721fddb95654901b32195c9c7avboxsync * descriptors of programmable size.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_TMDMAX (256) /* Transmit descriptor ring size */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_RMDMAX (256) /* Receive descriptor ring size */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Transmit descriptor structure */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t tmd_flags; /* OWN, SOP, EOP, cksum ctl and bufize */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t tmd_addr; /* 8-bye aligned buffer address */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* fields in the tmd_flags */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMETMD_BUFSIZE (0x3fff << 0) /* 0-13 : Tx Data buffer size */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMETMD_CSSTART (0x3f << 14) /* 14-19 : Checksum start offset */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMETMD_CSSTUFF (0xff << 20) /* 20-27 : Checksum stuff offset */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMETMD_CSENABL (1 << 28) /* 28 : Enable checksum computation */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMETMD_EOP (1 << 29) /* 29 : End Of Packet flag */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMETMD_SOP (1 << 30) /* 30 : Start Of Packet flag */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMETMD_OWN (0x80000000) /* 31 : Ownership flag */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /* 0 - owned by software */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /* 1 - owned by hardware */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMETMD_CSSTART_SHIFT 14 /* checksum start bit position */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMETMD_CSSTUFF_SHIFT 20 /* checksum stuff bit position */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Programming Notes:
45e9809aff7304721fddb95654901b32195c9c7avboxsync * 1. If a packet occupies more than one descriptor, the software must
45e9809aff7304721fddb95654901b32195c9c7avboxsync * turn over the ownership of the descriptors to the hardware
45e9809aff7304721fddb95654901b32195c9c7avboxsync * "last-to-first", in order to avoid race conditions.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * 2. If a packet resides in more than one buffer, the Checksum_Enable,
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Checksum_Stuff_Offset and Checksum_Start_Offset fields must have the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * same values in all the descriptors that were allocated to the packet.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * 3. The hardware implementation relies on the fact that if a buffer
45e9809aff7304721fddb95654901b32195c9c7avboxsync * starts at an "odd" boundary, the DMA state machine can "rewind"
45e9809aff7304721fddb95654901b32195c9c7avboxsync * to the nearest burst boundary and execute a full DVMA burst Read.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * There is no other alignment restriction for the transmit data buffer.
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Receive Descriptor structure */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rmd_flags; /* OWN, OVFLOW, buf/data size, cksum */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rmd_addr; /* 8-byte aligned buffer address */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* fields in the rmd_flags */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMERMD_CKSUM (0xffff << 0) /* 0-15 : checksum computed */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMERMD_BUFSIZE (0x3fff << 16) /* 16-29 : buffer/data size */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMERMD_OVFLOW (1 << 30) /* 30 : Rx buffer overflow */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMERMD_OWN (0x80000000) /* 31 : Ownership flag */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /* 0 - owned by software */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /* 1 - owned by hardware */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMERMD_BUFSIZE_SHIFT 16 /* buffer/data size bit position */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* The free receive data buffers must be 64-byte aligned */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* ************************************************************************* */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Global Register set in SEB (Shared Ethernet Block) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t intmask; /* Global Interrupt Mask Register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Global Software Reset Command Register - RW
45e9809aff7304721fddb95654901b32195c9c7avboxsync * These bits become "self cleared" after the corresponding reset command
45e9809aff7304721fddb95654901b32195c9c7avboxsync * has been executed. After a reset, the software must poll this register
45e9809aff7304721fddb95654901b32195c9c7avboxsync * till both the bits are read as 0's.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_RESET_GLOBAL HMEG_RESET_ETX | HMEG_RESET_ERX
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* Global Configuration Register - RW */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_CONFIG_BURSTSZ (0x3 << 0) /* sbus max burst size */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_CONFIG_64BIT_XFER (1 << 2) /* Extended transfer mode */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_CONFIG_PARITY (1 << 3) /* sbus parity enable */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_CONFIG_RES1 (1 << 4) /* reserved, should be 0 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_CONFIG_BURST16 0x00 /* sbus max burst size 16 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_CONFIG_BURST32 0x01 /* sbus max burst size 32 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_CONFIG_BURST64 0x02 /* sbus max burst size 64 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_CONFIG_BURST_RES 0x03 /* sbus max burst size - reserved */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Global Status Register - R-AC
45e9809aff7304721fddb95654901b32195c9c7avboxsync * All the bits in the Global Status Register are automatically cleared when
45e9809aff7304721fddb95654901b32195c9c7avboxsync * read with the exception of bit 23. The MIF status bit will be cleared after
45e9809aff7304721fddb95654901b32195c9c7avboxsync * the MIF Status Register is read.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_FRAME_RCVD (1 << 0) /* from RX_MAC to RxFIFO */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_RXF_CNT_EXP (1 << 1) /* Rx_frame_counter expired */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_ALN_CNT_EXP (1 << 2) /* Alignment_Error_cntr exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_CRC_CNT_EXP (1 << 3) /* CRC_Error_counter expired */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_LEN_CNT_EXP (1 << 4) /* Length_Error_counter exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_RXFIFO_OVFL (1 << 5) /* RxFIFO_Overflow in RX_MAC */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_RCV_CNT_EXP (1 << 6) /* Code_Violation_counter exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_SQE_TST_ERR (1 << 7) /* SQE Test error in XIF */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_FRAME_SENT (1 << 8) /* Frame sent from TX_MAC */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_TXFIFO_UNDR (1 << 9) /* TxFIFO Underrun in TX_MAC */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_MXPKTSZ_ERR (1 << 10) /* Maximum_Packet_Size error */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_NRMCOLC_EXP (1 << 11) /* Normal_collision_cntr exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_EXCOLC_EXP (1 << 12) /* Excessive_coll_cntr exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_LATCOLC_EXP (1 << 13) /* Late_Collision_cntr exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_FSTCOLC_EXP (1 << 14) /* First_Coll_cntr expired */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_DEFTIMR_EXP (1 << 15) /* Defer_Timer expired */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_RINT (1 << 16) /* from RxFIFO to host memory */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_RX_DROP (1 << 17) /* No free Rx descriptors */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_RX_ERR_ACK (1 << 18) /* Error Ack in Rx DMA cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_RX_LATE_ERR (1 << 19) /* Late Error in Rx DMA cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_RX_PAR_ERR (1 << 20) /* Parity error in Rx DMA */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_RX_TAG_ERR (1 << 21) /* No two consecutiv tag bits */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_EOP_ERR (1 << 22) /* EOP not set in Tx desc */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_MIF_INTR (1 << 23) /* MIF interrupt */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_TINT (1 << 24) /* from host mem to TxFIFO */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_TX_ALL (1 << 25) /* TxFIFO empty */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_TX_ERR_ACK (1 << 26) /* Error Ack in Tx DMA cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_TX_LATE_ERR (1 << 27) /* Late error in Tx DMA cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_TX_PAR_ERR (1 << 28) /* Parity error in Tx DMA */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_TX_TAG_ERR (1 << 29) /* No two consecutiv tag bits */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_SLV_ERR_ACK (1 << 30) /* Error Ack in PIO cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_SLV_PAR_ERR (0x80000000) /* Parity error in PIO write */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_FATAL_ERR 0xfc7c0000 /* all fatal errors */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_NONFATAL_ERR 0x0002fefc /* all non-fatal errors */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_NORMAL_INT 0x01810000 /* normal interrupts */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_STATUS_INTR 0xfefffefc /* All interesting interrupts */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Global Interrupt Mask register
45e9809aff7304721fddb95654901b32195c9c7avboxsync * There is one-to-one correspondence between the bits in this register and
45e9809aff7304721fddb95654901b32195c9c7avboxsync * the Global Status register.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The MIF interrupt [bit 23] is not maskable here. It should be masked at the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * source of the interrupt in the MIF.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Default value of the Global Interrupt Mask register is 0xFF7FFFFF.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_FRAME_RCVD (1 << 0) /* from RX_MAC to RxFIFO */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_RXF_CNT_EXP (1 << 1) /* Rx_frame_counter expired */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_ALN_CNT_EXP (1 << 2) /* Alignment_Error_cntr exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_CRC_CNT_EXP (1 << 3) /* CRC_Error_counter expired */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_LEN_CNT_EXP (1 << 4) /* Length_Error_counter exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_RXFIFO_OVFL (1 << 5) /* RxFIFO_Overflow in RX_MAC */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_RCV_CNT_EXP (1 << 6) /* Code_Violation_counter exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_SQE_TST_ERR (1 << 7) /* SQE Test error in XIF */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_FRAME_SENT (1 << 8) /* Frame sent from TX_MAC */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_TXFIFO_UNDR (1 << 9) /* TxFIFO Underrun in TX_MAC */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_MXPKTSZ_ERR (1 << 10) /* Maximum_Packet_Size error */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_NRMCOLC_EXP (1 << 11) /* Normal_collision_cntr exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_EXECOLC_EXP (1 << 12) /* Excessive_coll_cntr exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_LATCOLC_EXP (1 << 13) /* Late_Collision_cntr exp */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_FSTCOLC_EXP (1 << 14) /* First_Coll_cntr expired */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_DEFTIMR_EXP (1 << 15) /* Defer_Timer expired */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_RINT (1 << 16) /* from RxFIFO to host memory */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_RX_DROP (1 << 17) /* No free Rx descriptors */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_RX_ERR_ACK (1 << 18) /* Error Ack in Rx DMA cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_RX_LATE_ERR (1 << 19) /* Late Error in Rx DMA cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_RX_PAR_ERR (1 << 20) /* Parity error in Rx DMA */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_RX_TAG_ERR (1 << 21) /* No two consecutiv tag bits */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_EOP_ERR (1 << 22) /* EOP not set in Tx desc */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_MIF_INTR (1 << 23) /* MIF interrupt */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_TINT (1 << 24) /* from host mem to TxFIFO */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_TX_ALL (1 << 25) /* TxFIFO empty */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_TX_ERR_ACK (1 << 26) /* Error Ack in Tx DMA cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_TX_LATE_ERR (1 << 27) /* Late error in Tx DMA cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_TX_PAR_ERR (1 << 28) /* Parity error in Tx DMA */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_TX_TAG_ERR (1 << 29) /* No two consecutiv tag bits */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_SLV_ERR_ACK (1 << 30) /* Error Ack in PIO cycle */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEG_MASK_SLV_PAR_ERR (0x80000000) /* Parity error in PIO write */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /* uninteresting interrupts */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Interrupts which are not interesting are:
45e9809aff7304721fddb95654901b32195c9c7avboxsync * HMEG_MASK_FRAME_SENT
45e9809aff7304721fddb95654901b32195c9c7avboxsync * HMEG_MASK_RXF_CNT_EXP
45e9809aff7304721fddb95654901b32195c9c7avboxsync * HMEG_MASK_FRAME_RCVD
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* ************************************************************************* */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* ETX Register set */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txring; /* Transmit Descriptor Ring Pointer */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txbuf_base; /* Transmit Data Buffer Base Address */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txbuf_disp; /* Transmit Data Buffer Displacement */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txfifo_sdwr_ptr; /* TxFIFO Shadow Write Pointer */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txfifo_sdrd_ptr; /* TxFIFO Shadow Read pointer */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t state_mach; /* ETX State Machine Register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txbuf_ptr; /* Transmit Data Buffer Pointer */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txfifo_loapert[512]; /* TxFIFO Lower Aperture */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txfifo_hiapert[512]; /* TxFIFO Higher Aperture */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * ETX Transmit Pending Command Register - RW
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This 1-bit command must be issued by the software for every packet that the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * driver posts to the hardware.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This bit becomes "self-cleared" after the command is executed.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMET_TXPEND_TDMD (1 << 0) /* wake up Tx DMA engine */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * ETX Configuration Register
45e9809aff7304721fddb95654901b32195c9c7avboxsync * If the desire is to buffer an entire standard Ethernet frame before its
45e9809aff7304721fddb95654901b32195c9c7avboxsync * transmission is enabled, the Tx-FIFO-Threshold field has to be proframmed
45e9809aff7304721fddb95654901b32195c9c7avboxsync * to "0x1ff".
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The default value for the register is 0x3fe.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Bit 10 is used to modify the functionality of the Tx_All interrupt.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * If it is 0, Tx_All interrupt is generated after processing the last
45e9809aff7304721fddb95654901b32195c9c7avboxsync * transmit descriptor with the OWN bit set. This only implies that the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * data has been copied to the FIFO.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * If it is 1, Tx_All interrupt is generated only after the entire
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Transmit FIFO has been drained.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMET_CONFIG_TXDMA_EN (1 << 0) /* Enable Tx DMA */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMET_CONFIG_TXFIFOTH (0x1ff << 1) /* 1-9 : TX FIFO Threshold */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMET_CONFIG_DRAIN_INT (1 << 10) /* TX_all_int modifier */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Transmit Descriptor Pointer
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This 29-bit register points to the next descriptor in the ring. The 21 most
45e9809aff7304721fddb95654901b32195c9c7avboxsync * significant bits are used as the base address for the desriptor ring,
45e9809aff7304721fddb95654901b32195c9c7avboxsync * and the 8 least significant bits are used as a displacement for the current
45e9809aff7304721fddb95654901b32195c9c7avboxsync * descriptor.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This register should be initialized to a 2KByte-aligned value after power-on
45e9809aff7304721fddb95654901b32195c9c7avboxsync * or Software Reset.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * ETX TX ring size register
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This is a 4-bit register to determine the no. of descriptor entries in the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * TX-ring. The number of entries can vary from 16 through 256 in increments of
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* ************************************************************************* */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* ERX Register Set */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rxring; /* Receive Descriptor Ring Pointer */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rxbuf_ptr; /* Receive Data Buffer Pointer */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rxfifo_sdwr_ptr; /* RxFIFO Shadow Write Pointer */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t state_mach; /* ERX State Machine Register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rxfifo_loapert[512]; /* RxFIFO Lower Aperture */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rxfifo_hiapert[512]; /* RxFIFO Higher Aperture */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * ERX Configuration Register - RW
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This 23-bit register determines the ERX-specific parameters that control the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * operation of the receive DMA channel.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RXDMA_EN (1 << 0) /* 0 : Enable Rx DMA */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RES1 (0x3 << 1) /* 1,2 : reserverd */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_FBOFFSET (0x7 << 3) /* 3-5 : First Byte Offset */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RES2 (0x7 << 6) /* 6-8 : reserverd */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RXRINGSZ (0x3 << 9) /* 9,10 : RX desc. ring size */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RES3 (0x1f << 11) /* 11-15 : reserverd */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RX_CSSTART (0x7f << 16) /* 16-22 : cksum start offset */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RXRINGSZ32 (0x0 << 9) /* Rx descr. ring size 32 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RXRINGSZ64 (0x1 << 9) /* Rx descr. ring size 64 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RXRINGSZ128 (0x2 << 9) /* Rx descr. ring size 128 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMER_CONFIG_RXRINGSZ256 (0x3 << 9) /* Rx descr. ring size 256 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Receive Descriptor Pointer
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This 29-bit register points to the next descriptor in the ring. The 21 most
45e9809aff7304721fddb95654901b32195c9c7avboxsync * significant bits are used as the base address for the desriptor ring,
45e9809aff7304721fddb95654901b32195c9c7avboxsync * and the 8 least significant bits are used as a displacement for the current
45e9809aff7304721fddb95654901b32195c9c7avboxsync * descriptor.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This register should be initialized to a 2KByte-aligned value after power-on
45e9809aff7304721fddb95654901b32195c9c7avboxsync * or Software Reset.
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* ************************************************************************* */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Declarations and definitions specific to the BigMAC functional block.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The BigMAC block will provide the MAC functons for 10 or 100 Mbps CSMA/CD
45e9809aff7304721fddb95654901b32195c9c7avboxsync * protocol based interface.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * BigMAC Register Set.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * BigMAC addresses map on a SBus word boundry. So all registers are
45e9809aff7304721fddb95654901b32195c9c7avboxsync * declared for a size of 32 bits. Registers that use fewer than 32
45e9809aff7304721fddb95654901b32195c9c7avboxsync * bits will return 0 in the bits not used.
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t xifc; /* XIF Configuration register [9-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txcfg; /* tx configuration register [9-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t alimit; /* attempt limit register [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t palen; /* preamble length register [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t papat; /* preamble pattern register [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txsfd; /* tx start frame delimiter [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txmax; /* tx maximum packet size [12-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txmin; /* tx minimum frame size [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t nccnt; /* normal collision counter [15-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t fccnt; /* first succesful coll. counter [15-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t excnt; /* excess collision counter [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t ltcnt; /* late collision counter [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t txsm; /* tx state machine register [8-0] (R) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rxrst; /* rx software reset register (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rxcfg; /* rx configuration register [12-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rxmax; /* rx maximum packet size [12-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t rxmin; /* rx minimum frame size [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t madd2; /* mac address register 2 [47-32] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t madd1; /* mac address register 1 [31-16] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t madd0; /* mac address register 0 [15-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t frcnt; /* receive frame count [15-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t lecnt; /* rx giant length error count [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t aecnt; /* rx alignment error count [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t fecnt; /* receive crc error count [7-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t afr2; /* addr filter register 0_2 [15-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t afr1; /* addr filter register 0_1 [15-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t afr0; /* addr filter register 0_0 [15-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t afmr; /* addr filter mask reg 0 [15-0] (RW) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * BigMAC Register Bit Masks.
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* XIF Configuration Register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_XIFC_ENAB (1 << 0) /* Enable XIF output drivers */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_XIFC_XIFLPBK (1 << 1) /* Enable XIF Loopback mode */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_XIFC_MIILPBK (1 << 2) /* Enable MII Loopback mode */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_XIFC_MIIBUFDIS (1 << 3) /* Disable MII Recv Buffers */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* IN FEPS 2.1 or earlier rev */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_XIFC_SQETSTENB (1 << 4) /* Enable SQE Test */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_XIFC_SQETSTWIN (0x1f << 5) /* SQE Test time window */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* IN FEPS 2.2 or later rev */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_XIFC_LANCE_ENAB (1 << 4) /* Enable LANCE mode */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_XIFC_LANCE_IPG0 (0x1f << 5) /* IPG0 for LANCE mode */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * TX_MAC Software Reset Command Register
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This bit is set to 1 when a PIO write is done. This bit becomes self-cleared.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * after the command has been executed.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_TX_RESET (1 << 0) /* TX_MAC Reset Command */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * TX_MAC Configuration Register
45e9809aff7304721fddb95654901b32195c9c7avboxsync * To Ensure proper operation of the TX_MAC, the TX_MAC_Enable bit must always
45e9809aff7304721fddb95654901b32195c9c7avboxsync * be cleared to 0 and a delay imposed before a PIO write to any of the other
45e9809aff7304721fddb95654901b32195c9c7avboxsync * bits in the TX_MAC Configuration register or any of the MAC parameter
45e9809aff7304721fddb95654901b32195c9c7avboxsync * registers is done.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The amount of delay required depends on the time required to transmit a max.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * size frame.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMACTXRSTDELAY (125) /* 125 us wait period */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_TXCFG_RES1 (0xf << 1) /* 1-4 : reserved */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_TXCFG_SLOW (1 << 5) /* carrier detect before tx */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_TXCFG_IGCOLL (1 << 6) /* tx ignore collision */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_TXCFG_NFCS (1 << 7) /* no FCS will be generated */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_TXCFG_NGU (1 << 10) /* Never Give Up */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * RX_MAC Configuration Register
45e9809aff7304721fddb95654901b32195c9c7avboxsync * A delay of 3.2 us should be allowed after clearing Rx_MAC_Enable or
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Hash_Filter_enable or Address_Filter_Enable bits.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMACRXRSTDELAY (40) /* 3.2 us wait period */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_RXCFG_RES1 (0xf << 1) /* 1-4 : reserved */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_RXCFG_STRIP (1 << 5) /* rx strip pad bytes */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_RXCFG_PROMIS (1 << 6) /* rx enable promiscous */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_RXCFG_ERR (1 << 7) /* rx disable error checking */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_RXCFG_CRC (1 << 8) /* rx disable CRC stripping */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_RXCFG_MYOWN (1 << 9) /* rx filter own packets */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_RXCFG_GRPROM (1 << 10) /* rx promiscuous group mode */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_RXCFG_HASH (1 << 11) /* rx enable hash filter */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define BMAC_RXCFG_ADDR (1 << 12) /* rx enable address filter */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* ************************************************************************* */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * MII Transceiver Interface
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The Management Interface (MIF) allows the host to program and collect status
45e9809aff7304721fddb95654901b32195c9c7avboxsync * from two transceivers connected to the MII. MIF supports three modes of
45e9809aff7304721fddb95654901b32195c9c7avboxsync * operation:
45e9809aff7304721fddb95654901b32195c9c7avboxsync * 1. Bit-Bang Mode
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This mode is imlemented using three 1-bit registers: data, clock,
45e9809aff7304721fddb95654901b32195c9c7avboxsync * and output_enable.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * 2. Frame Mode
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This mode is supported using one 32-bit register: Frame register.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The software loads the Frame Register with avalid instaruction
45e9809aff7304721fddb95654901b32195c9c7avboxsync * ("frame"), and polls the Valid Bit for completion.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * 3. Polling Mode
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The Polling mechanism is used for detecting a status change in the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * transceiver. When this mode is enabled, the MIF will continuously
45e9809aff7304721fddb95654901b32195c9c7avboxsync * poll a specified transceiver register and generate a maskable
45e9809aff7304721fddb95654901b32195c9c7avboxsync * interrupt when a status change is detected. This mode of operation
45e9809aff7304721fddb95654901b32195c9c7avboxsync * can only be used when the MIF is in the "Frame mode".
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint_t mif_bbopenb; /* MIF Bit Bang Output Enable */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* mif_bbc - Bit Bang Clock register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_BBCLK (1 << 0); /* Bit Babg Clock */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* mif_bbdata - bit Bang Data register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_BBDATA (1 << 0); /* Bit Bang Data */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* mif_bbopenb - Bit Bang oOutput Enable register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_BBOPENB (1 << 0); /* Bit Bang output Enable */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Management Frame Structure:
45e9809aff7304721fddb95654901b32195c9c7avboxsync * <IDLE> <ST><OP><PHYAD><REGAD><TA> <DATA> <IDLE>
45e9809aff7304721fddb95654901b32195c9c7avboxsync * READ: <01><10><AAAAA><RRRRR><Z0><DDDDDDDDDDDDDDDD>
45e9809aff7304721fddb95654901b32195c9c7avboxsync * WRITE: <01><01><AAAAA><RRRRR><10><DDDDDDDDDDDDDDDD>
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* mif_frame - MIF control and data register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_FRDATA (0xffff << 0) /* 0-15 : data bits */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_FRTA0 (0x1 << 16) /* 16 : TA bit, 1 for completion */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_FRTA1 (0x1 << 17) /* 16-17 : TA bits */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_FRREGAD (0x1f << 18) /* 18-22 : register address bits */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_FRPHYAD (0x1f << 23) /* 23-27 : PHY ad, should be 0 */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_FROP (0x3 << 28) /* 28-29 : Operation - Write/Read */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_FRST (0xc0000000) /* 30-31 : START bits */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* maximum delay for MIF Register Read/Write operation */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* maximum delay for Transceiver Reset */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* mif_cfg - MIF Configuration Register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_CFGBB (1 << 2) /* Bit Bang Enable */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_CFGPR (0x1f << 3) /* Poll Register address */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_CFGM0 (1 << 8) /* MDIO_0 Data / MDIO_0 attached */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_CFGM1 (1 << 9) /* MDIO_1 Data / MDIO_1 attached */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_CFGPD (0x1f << 10) /* Poll Device PHY address */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * MDIO_0 corresponds to the On Board Transceiver.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * MDIO_1 corresponds to the External Transceiver.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The PHYAD for both is 0.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_INTERNAL_PHYAD 1 /* PHY address for int. transceiver */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_EXTERNAL_PHYAD 0 /* PHY address for ext. transceiver */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* mif_imask - MIF Interrupt Mask Register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This register is bit-to-bit same as Basic/Status Register
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_INTMASK (0xffff << 0) /* 0-15 : Interrupt mask */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* mif_bassts - MIF Basic / Status register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The Basic portion of this register indicates the last value of the register
45e9809aff7304721fddb95654901b32195c9c7avboxsync * read indicated in the POLL REG field of the Configuration Register.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The Status portion indicates bit(s) that have changed.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * The MIF Mask register is corresponding to this register in terms of the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * bit(s) that need to be masked for generating interrupt on the MIF Interrupt
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Bit of the Global Status Rgister.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_STATUS (0xffff << 0) /* 0-15 : Status */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_BASIC (0xffff << 16) /* 16-31 : Basic register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* mif_fsm - MIF State Machine register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HME_MIF_FSM (0x3ff << 0) /* 0-9 : MIF state */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* ************************************************************************ */
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Definition for the time required to wait after a software
45e9809aff7304721fddb95654901b32195c9c7avboxsync * reset has been issued.
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define HMEDELAY(c, n) \
45e9809aff7304721fddb95654901b32195c9c7avboxsync register int N = n / HMEWAITPERIOD; \
45e9809aff7304721fddb95654901b32195c9c7avboxsync while (--N > 0) { \
45e9809aff7304721fddb95654901b32195c9c7avboxsync#endif /* _SYS_HME_MAC_H */