hme_mac.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1992-1999 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_HME_MAC_H
#define _SYS_HME_MAC_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* HOST MEMORY DATA STRUCTURES
*/
/* The pointers to the Descriptor Ring base Addresses must be 2K-byte aligned */
#define HME_HMDALIGN (2048)
/*
* The transmit and receiver Descriptor Rings are organized as "wrap-around
* descriptors of programmable size.
*/
/* Transmit descriptor structure */
struct hme_tmd {
};
/* fields in the tmd_flags */
/* 0 - owned by software */
/* 1 - owned by hardware */
/*
* Programming Notes:
*
* 1. If a packet occupies more than one descriptor, the software must
* turn over the ownership of the descriptors to the hardware
* "last-to-first", in order to avoid race conditions.
*
* 2. If a packet resides in more than one buffer, the Checksum_Enable,
* Checksum_Stuff_Offset and Checksum_Start_Offset fields must have the
* same values in all the descriptors that were allocated to the packet.
*
* 3. The hardware implementation relies on the fact that if a buffer
* starts at an "odd" boundary, the DMA state machine can "rewind"
* to the nearest burst boundary and execute a full DVMA burst Read.
*
* There is no other alignment restriction for the transmit data buffer.
*/
/* Receive Descriptor structure */
struct hme_rmd {
};
/* fields in the rmd_flags */
/* 0 - owned by software */
/* 1 - owned by hardware */
/* The free receive data buffers must be 64-byte aligned */
#define HME_RMD_BUFALIGN 64
/* ************************************************************************* */
/* Global Register set in SEB (Shared Ethernet Block) */
struct hme_global {
};
/*
* Global Software Reset Command Register - RW
* These bits become "self cleared" after the corresponding reset command
* has been executed. After a reset, the software must poll this register
* till both the bits are read as 0's.
*/
/* Global Configuration Register - RW */
#define HMEG_CONFIG_64BIT_SHIFT 2
/*
* Global Status Register - R-AC
*
* All the bits in the Global Status Register are automatically cleared when
* read with the exception of bit 23. The MIF status bit will be cleared after
* the MIF Status Register is read.
*/
/*
* Global Interrupt Mask register
*
* There is one-to-one correspondence between the bits in this register and
* the Global Status register.
*
* The MIF interrupt [bit 23] is not maskable here. It should be masked at the
* source of the interrupt in the MIF.
*
* Default value of the Global Interrupt Mask register is 0xFF7FFFFF.
*/
#define HMEG_MASK_INTR (~HMEG_STATUS_INTR)
/* uninteresting interrupts */
/*
* Interrupts which are not interesting are:
* HMEG_MASK_FRAME_SENT
* HMEG_MASK_RXF_CNT_EXP
* HMEG_MASK_FRAME_RCVD
*/
/* ************************************************************************* */
/* ETX Register set */
struct hme_etx {
};
struct hme_txfifo_aperture {
};
/*
* ETX Transmit Pending Command Register - RW
* This 1-bit command must be issued by the software for every packet that the
* driver posts to the hardware.
* This bit becomes "self-cleared" after the command is executed.
*/
/*
* ETX Configuration Register
* If the desire is to buffer an entire standard Ethernet frame before its
* transmission is enabled, the Tx-FIFO-Threshold field has to be proframmed
* to "0x1ff".
* The default value for the register is 0x3fe.
* Bit 10 is used to modify the functionality of the Tx_All interrupt.
* If it is 0, Tx_All interrupt is generated after processing the last
* transmit descriptor with the OWN bit set. This only implies that the
* data has been copied to the FIFO.
* If it is 1, Tx_All interrupt is generated only after the entire
* Transmit FIFO has been drained.
*/
/*
* Transmit Descriptor Pointer
*
* This 29-bit register points to the next descriptor in the ring. The 21 most
* significant bits are used as the base address for the desriptor ring,
* and the 8 least significant bits are used as a displacement for the current
* descriptor.
*
* This register should be initialized to a 2KByte-aligned value after power-on
* or Software Reset.
*
*/
/*
* ETX TX ring size register
* This is a 4-bit register to determine the no. of descriptor entries in the
* TX-ring. The number of entries can vary from 16 through 256 in increments of
* 16.
*/
#define HMET_RINGSZ_SHIFT 4
/* ************************************************************************* */
/* ERX Register Set */
struct hme_erx {
};
struct hme_rxfifo_aperture {
};
/*
* ERX Configuration Register - RW
* This 23-bit register determines the ERX-specific parameters that control the
* operation of the receive DMA channel.
*/
#define HMER_CONFIG_FBO_SHIFT 3
#define HMER_RXRINGSZ_SHIFT 9
/*
* Receive Descriptor Pointer
*
* This 29-bit register points to the next descriptor in the ring. The 21 most
* significant bits are used as the base address for the desriptor ring,
* and the 8 least significant bits are used as a displacement for the current
* descriptor.
*
* This register should be initialized to a 2KByte-aligned value after power-on
* or Software Reset.
*
*/
/* ************************************************************************* */
/*
* Declarations and definitions specific to the BigMAC functional block.
*
* protocol based interface.
*
*/
/*
* BigMAC Register Set.
* BigMAC addresses map on a SBus word boundry. So all registers are
* declared for a size of 32 bits. Registers that use fewer than 32
* bits will return 0 in the bits not used.
*/
struct hme_bmac {
};
/*
* BigMAC Register Bit Masks.
*/
/* XIF Configuration Register */
/* IN FEPS 2.1 or earlier rev */
/* IN FEPS 2.2 or later rev */
#define BMAC_XIFC_IPG0_SHIFT 5
/*
* TX_MAC Software Reset Command Register
* This bit is set to 1 when a PIO write is done. This bit becomes self-cleared.
* after the command has been executed.
*/
/*
* TX_MAC Configuration Register
* To Ensure proper operation of the TX_MAC, the TX_MAC_Enable bit must always
* be cleared to 0 and a delay imposed before a PIO write to any of the other
* bits in the TX_MAC Configuration register or any of the MAC parameter
* registers is done.
*
* The amount of delay required depends on the time required to transmit a max.
* size frame.
*/
/*
* RX_MAC Configuration Register
* A delay of 3.2 us should be allowed after clearing Rx_MAC_Enable or
* Hash_Filter_enable or Address_Filter_Enable bits.
*/
/* ************************************************************************* */
/*
* MII Transceiver Interface
*
* The Management Interface (MIF) allows the host to program and collect status
* from two transceivers connected to the MII. MIF supports three modes of
* operation:
* 1. Bit-Bang Mode
* This mode is imlemented using three 1-bit registers: data, clock,
* and output_enable.
*
* 2. Frame Mode
* This mode is supported using one 32-bit register: Frame register.
* The software loads the Frame Register with avalid instaruction
* ("frame"), and polls the Valid Bit for completion.
*
* 3. Polling Mode
* The Polling mechanism is used for detecting a status change in the
* transceiver. When this mode is enabled, the MIF will continuously
* poll a specified transceiver register and generate a maskable
* interrupt when a status change is detected. This mode of operation
* can only be used when the MIF is in the "Frame mode".
*
*/
struct hme_mif {
};
/* mif_bbc - Bit Bang Clock register */
#define HME_BBCLK_LOW 0
#define HME_BBCLK_HIGH 1
/* mif_bbdata - bit Bang Data register */
/* mif_bbopenb - Bit Bang oOutput Enable register */
/*
* Management Frame Structure:
* <IDLE> <ST><OP><PHYAD><REGAD><TA> <DATA> <IDLE>
* READ: <01><10><AAAAA><RRRRR><Z0><DDDDDDDDDDDDDDDD>
* WRITE: <01><01><AAAAA><RRRRR><10><DDDDDDDDDDDDDDDD>
*/
/* mif_frame - MIF control and data register */
#define HME_MIF_FRREGAD_SHIFT 18
#define HME_MIF_FRPHYAD_SHIFT 23
#define HME_MIF_FRREAD 0x60020000
#define HME_MIF_FRWRITE 0x50020000
#define HMEMAXMIFDELAY (100)
/* maximum delay for Transceiver Reset */
#define HME_PHYRST_MAXDELAY (500)
/* mif_cfg - MIF Configuration Register */
#define HME_MIF_CFGPR_SHIFT 3
#define HME_MIF_CFGPD_SHIFT 10
#define HME_MIF_POLL_DELAY 200
/*
* MDIO_0 corresponds to the On Board Transceiver.
* MDIO_1 corresponds to the External Transceiver.
* The PHYAD for both is 0.
*/
#define HME_EXTERNAL_PHYAD 0 /* PHY address for ext. transceiver */
/* mif_imask - MIF Interrupt Mask Register */
/*
*/
/* mif_bassts - MIF Basic / Status register */
/*
* The Basic portion of this register indicates the last value of the register
* read indicated in the POLL REG field of the Configuration Register.
* The Status portion indicates bit(s) that have changed.
* The MIF Mask register is corresponding to this register in terms of the
* bit(s) that need to be masked for generating interrupt on the MIF Interrupt
* Bit of the Global Status Rgister.
*/
/* mif_fsm - MIF State Machine register */
/* ************************************************************************ */
/*
* Definition for the time required to wait after a software
* reset has been issued.
*/
#define HMEMAXRSTDELAY (200)
#define HMEWAITPERIOD HMEPERIOD
#define HMEDELAY(c, n) \
{ \
register int N = n / HMEWAITPERIOD; \
while (--N > 0) { \
if (c) \
break; \
} \
}
#ifdef __cplusplus
}
#endif
#endif /* _SYS_HME_MAC_H */