fdreg.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1989-1998,2000 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_FDREG_H
#define _SYS_FDREG_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Floppy Controller Registers
*/
#ifndef _ASM
union fdcreg {
volatile struct {
volatile struct fdc_82077_reg {
#define fdc_msr fdc_control
#define fdc_dsr fdc_control
};
#endif /* !_ASM */
/* DSR - data rate select register */
/* MSR - main status register */
/* command types */
/* commands */
/* 0x00-0x01 not defined */
#define RDTRK 0x02
#define SPECIFY 0x03
#define SNSDSTAT 0x04
#define WRTCMD 0x05
#define RDCMD 0x06
#define RECALIBRATE 0x07
/* 0x10-0x12 not defined */
#define CONFIGURE 0x13
/* 0x14-0x1F not defined */
/* Modifier bits for the command byte */
#define MT 0x80
#define MFM 0x40
#define SK 0x20
#define MOT 0x80
/* results */
/* status reg0 */
/* status reg1 */
/* status reg3 */
/* DOR - Digital Output register - 82077 only */
/* DIR - Digital Input register - 82077 only */
#ifndef _ASM
/* 0.75 seconds */
/* 6 seconds */
/* Macros to set and retrieve data from the controller registers */
{ if (flag) \
else \
#endif /* !_ASM */
/*
* Auxio Registers
*/
/*
* for the muchio, slavio, and cheerio I/O subsystem chips
*
* In general, muchio is found on sun4c, slavio is found on sun4m and sun4u
* with Sbus. Cheerio is found on sun4u with a PCI bus.
*
*
*
* 07 06 05 04 03 02 01 00
* muchio 1 1 DEN CHG SEL TC EJCT LED
* slavio 1 1 DEN 0 IMUX 0 TC LED
*
* The auxio register is designed poorly from a software perspective.
* a) it supports other functions as well as floppy
* b) TC is at a different bit position for muchio versus sun4m
*
* The cheerio auxio register is only for the floppy and it is a 32 bit
* register. It does not contain a TC because the cheerio supports
* floppy DMA. Please note that on the slavio auxio, the Digital
* Output register of the floppy controller contains a Density Select bit.
* On the cheerio, this bit is muxed with another
* signal. So, the cheerio auxio register contains a density select bit.
*
* cheerio auxio bit name bit#
* ------------------------------
* Floppy density sense 0
* Floppy desnity select 1
* Unused 31:1
*
*/
/*
* - when writing to the auxio register, the bits represented by
* AUX_MBO and AUX_MBO4M must be one
*/
/* 1 = transfer over */
/* 1 = transfer over */
/* 1 = high, 0 = low */
/*
* muchio additional floppy auxio bits
* slavio uses internal dor for these bits
*/
/* 1 = new diskette inserted */
/* 1 = selected, 0 = deselected */
/* 0 = eject the diskette */
/*
* cheerio additional floppy auxio bits
*/
#define AUX_HIGH_DENSITY 0x2
/*
* macros to set the Cheerio auxio registers.
*/
/*
* DMA registers (sun4u only)
*/
#ifndef _ASM
struct cheerio_dma_reg {
};
/* complete 0x500 isa registers. */
struct sb_dma_reg {
};
struct fdc_dma_reg {
};
#endif /* !_ASM */
/*
* DMA Control and Status Register(DCSR) definitions. See Cheerio spec
* for more details
*/
| fd_burstsize \
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_FDREG_H */