dmaga.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1988-1996, by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_DMAGA_H
#define _SYS_DMAGA_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* New SUN DMA gate array definitions, revisions 1 and 2.
*
* Generally, this dma engine is owned exclusively by a SCSI host
* adapter chip (ESP or ESP-2). Strictly speaking, a lance chip
* (AMD 7990 Local Area Ethernet Chip) is hung off of it as well,
* but there is very little we can do to the gate array to affect
* the lance.
*
* NOTE: On SS1 with DMA rev 1 it is essential that prior to accessing
* the D-channel (esp) registers, the dma is disabled. If not
* a watchdog reset or data access may follow
*/
struct dmaga {
/*
* Dma Address Register
*
* For DMA Rev1, strictly speaking, the msb is an 8 bit
* register and the 24 lsbs are a counter. This asssumes
* that no transfer will cross a 16mb boundary. This
* restriction does not apply for anything but DMA rev1.
*/
};
/* bits in the dma gate array status register */
/* Clear when device drops INT. */
/* ESC: only ESP interrupt pending. */
/*
* The following two defines apply only to rev1 (DMA) gate arrays
*/
/*
* The following define applies only to rev2 (DMA+), rev3 (DMA2),
* and ESC gate arrays.
*/
#define DMAGA_DRAINING 0x000C
/* Sad but true: you have to turn this */
/* on to get any interrupts from the */
/* ESP SCSI chip..... */
/*
* The following define applies only to rev1 (DMA) gate arrays
*/
/*
* The following define applies only to rev2 (DMA+), rev3 (DMA2),
* and ESC gate arrays.
*/
/* csr read. */
/* May or may not reset attached */
/* devices (e.g. ESP chip). */
/* 1 == TO MEMORY */
/* 0 == FROM MEMORY */
/*
* The following define applies only to rev1 (DMA) and ESC gate arrays
*/
/* NO reset and flush allowed */
/*
* The following defines thru DMAESC_EN_ADD apply only to ESC gate arrays
*/
/* 1 = 16 bytes */
/* 0 = 32 bytes */
/* expiration of count */
/* 1) DMAESC_SCSI_INT - ESP interrupt */
/* 2) DMAESC_TCZERO - transfer count 0 */
/* 3) DMAESC_PERR - parity error */
/* buffer. */
/* ignored if DMAESC_EN_AD set */
/* Note: overlap with DMA2 define */
/* below. */
/*
* The following two defines apply only to rev1 (DMA) gate arrays
*/
/*
* The following two defines apply only to rev1 (DMA) and rev 2 (DMA+)
* gate arrays
*/
/* lance DMA read cycle. This is not */
/* currently implemented and is not available */
/* for DMA2 or ESC. */
/*
* The following define is available only for rev3 (DMA2) gate arrays
*
* Do not set NOBURST and BURST64 at the same time (this is reserved
* and will have undefined effects). Instead, clear the BURSTMASK
* field and set what you want.
*/
/* Comaptible with DMA+. */
#define DMA2_SETNOBURST(d) \
#define DMA2_SETBURST32(d) \
/*
* The following defines up through the DMAGA_DEVID are valid only for
* rev2 (DMA+) gate arrays.
*/
/* (address latch enable) or AS* */
/* (address strobe). 1 = ALE, */
/* 0 = AS* (defaults to 0). This */
/* for different types of lance */
/* dma handshaking. This is not */
/* currently implemented and is */
/* not available on DMA2 or ESC. */
/* Clears on a slave write to LANCE. */
/* This is not currently used by any */
/* standard s/w, and is not */
/* implemented on DMA2 or ESC. */
/* use with the 53C90A scsi chip. */
/* interrupts (if set). Defaults to */
/* 0. Note that in order to get TC */
/* ints you have to enable the byte */
/* counter by setting DMAGA_ENATC. */
/* If you enable the byte counter, */
/* but also set this bit, you can get */
/* dma transfer limited by a byte */
/* counter w/o dealing with */
/* interrupts. */
/*
* The following defines are valid only for rev3 (DMA2) gate arrays.
*/
#define DMAGA_TWO_CYCLE 0x00200000
/*
* The next three defines are for the 'Next-address' autoload mechanism
*
* This mechanism is a somewhat complicated mechanism for pipelining DMA
* transfers. In the rev2 (DMA+) gate array, there are next_address and
* next_bytecnt registers that hide at the same address as the address
* and byte_count registers.
*
* The best way to describe how this works is to paraphrase from the S4-DMA+
* chip document (prelim, 7/12/89):
*
*
* If The DMAGA_ENANXT bit in dmaga_ csr is set, then a write to the
* dmaga_addr register will will write to the NEXT_ADDR register instead.
* If the DMAGA_ENANXT bit is set when the byte counter (dmaga_count)
* expires, and the NEXT_ADDR regsiter has been written to since the last
* time the byte counter expired, then the contents of the NEXT_ADDR
* register are copied to the dmaga_addr register. If DMAGA_ENANXT is set
* when the byte counter (dmaga_count) expires, but the NEXT_ADDR register
* has not been written to since the last time the byte counter expired,
* then DMA activity is stopped and DMA request from the ESP will be
* ignored until NEXT_ADDR is written to, or DMAGA_ENANXT is cleared.
* (Also, the DMAGA_DMAON bit will read as 0 while DMA is stopped because
* of this). When DMA is re-enabled by writing to the NEXT_ADDR register,
* the contents of the NEXT_ADDR register are copied to the dmaga_addr
* register before DMA activity actually begins.
*
* ...
*
* If the DMAGA_ENANXT bit in dmaga_csr is set, then a write to dmaga_count
* will write to the NEXT_BCNT register instead. If the NEXT_ADDR register
* is being copied into dmaga_addr, and DMAGA_ENANXT is set, then the
* NEXT_BCNT register will be copied into dmaga_count at the same time.
*
* (whew!)
*/
/* autoload mechanism (see above). */
/* (DMAGA_ALOAD || DMAGA_NALOAD) && */
/* DMAGA_ENDVMA && */
/* !(DMAGA_ERRPEND) */
/* (see above). */
/*
* burstsizes
*/
#define BURST1 0x01
#define BURST2 0x02
#define BURST4 0x04
#define BURST8 0x08
#define BURST16 0x10
#define BURST32 0x20
#define BURST64 0x40
#define BURSTSIZE_MASK 0x7f
/*
* Gate Array id bits:
*/
/*
* Compound conditions for interrupt and error checking.
*/
/*
* %b formatted error strings
*/
#define DMAGA_BITS \
"\20\20ILACC\17TC\13RQPND\12EN\11IN\10RST\7DRAIN\6FLSH\5INTEN\2ERRPEND\1INTPND"
#ifdef _KERNEL
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_DMAGA_H */