cg6fbc.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 1988-1989, Sun Microsystems, Inc.
*/
#ifndef _SYS_CG6FBC_H
#define _SYS_CG6FBC_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* CG6 register definitions, common to all environments.
*/
/*
* FBC MISC register bits
*/
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
struct l_fbc_misc {
};
/*
* FBC RASTEROP register bits
*/
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
struct l_fbc_rasterop {
};
/*
* FBC PATTALIGN register bits
*/
union l_fbc_pattalign {
#define l_fbc_pattalign_alignx l_fbc_pattalign_array[0]
};
/*
* FBC offsets & structure definition
*/
struct fbc {
/* miscellaneous & clipcheck registers */
struct l_fbc_misc l_fbc_misc;
/* status and command registers */
/* address registers */
/* writing a z-register just sets the corresponding z clip status bits */
/* raster offset registers */
/* autoincrement registers */
/* window registers */
struct l_fbc_rasterop l_fbc_rasterop;
/* attribute registers */
union l_fbc_pattalign l_fbc_pattalign;
/* indexed address registers */
};
/*
* FBC CLIPCHECK register bits.
*/
#define CLIP_MASK 0x3
#define CLIP_IN 0x0
#define CLIP_LT 0x1
#define CLIP_GT 0x2
#define CLIP_BACK 0x3
/*
* FBC STATUS, DRAWSTATUS, and BLITSTATUS register bits.
*/
#define L_FBC_TEC_EXCEPTION 0x40000000
#define L_FBC_FULL 0x20000000
#define L_FBC_BUSY 0x10000000
#define L_FBC_UNSUPPORTED_ATTR 0x02000000
#define L_FBC_HRMONO 0x01000000
#define L_FBC_ACC_OVERFLOW 0x00200000
#define L_FBC_ACC_PICK 0x00100000
#define L_FBC_TEC_HIDDEN 0x00040000
#define L_FBC_TEC_INTERSECT 0x00020000
#define L_FBC_TEC_VISIBLE 0x00010000
#define L_FBC_BLIT_HARDWARE 0x00008000
#define L_FBC_BLIT_SOFTWARE 0x00004000
#define L_FBC_BLIT_SRC_HID 0x00002000
#define L_FBC_BLIT_SRC_INT 0x00001000
#define L_FBC_BLIT_SRC_VIS 0x00000800
#define L_FBC_BLIT_DST_HID 0x00000400
#define L_FBC_BLIT_DST_INT 0x00000200
#define L_FBC_BLIT_DST_VIS 0x00000100
#define L_FBC_DRAW_HARDWARE 0x00000010
#define L_FBC_DRAW_SOFTWARE 0x00000008
#define L_FBC_DRAW_HIDDEN 0x00000004
#define L_FBC_DRAW_INTERSECT 0x00000002
#define L_FBC_DRAW_VISIBLE 0x00000001
/*
*/
#define FHC_CONFIG_FBID_SHIFT 24
#define FHC_CONFIG_FBID_MASK 255
#define FHC_CONFIG_REV_SHIFT 20
#define FHC_CONFIG_REV_MASK 15
#define FHC_CONFIG_1024 (0 << 11)
#define FHC_CONFIG_CPU_SPARC (0 << 9)
#define FHC_CONFIG_TESTX_SHIFT 4
#define FHC_CONFIG_TESTY_SHIFT 0
#define FHC_CONFIG_TESTY_MASK 15
#ifdef __cplusplus
}
#endif
#endif /* _SYS_CG6FBC_H */