audio_4231_impl.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2004 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_AUDIO4231_IMPL_H
#define _SYS_AUDIO4231_IMPL_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Implementation specific header file for the audiocs device driver.
*/
#ifdef _KERNEL
/*
* Global routines.
*/
uint8_t, int, char *);
uint8_t, int, char *);
/*
* These are the registers for the APC DMA channel interface to the
* 4231. One handle provides access the CODEC and the DMA engine's
* registers.
*/
struct cs4231_apc {
};
typedef struct cs4231_apc cs4231_apc_t;
/*
* APC CSR Register bit definitions
*/
#define APC_CLEAR_RESET_VALUE 0x00
/*
* These are the registers for the EBUS2 DMA channel interface to the
* 4231. One struct per channel for playback and record, therefore there
* individual handles for the CODEC and the two DMA engines.
*/
struct cs4231_eb2regs {
};
typedef struct cs4231_eb2regs cs4231_eb2regs_t;
/*
* Audio auxio register definitions
*/
/*
* EBUS 2 CSR definitions
*/
#define EB2_PINTR_MASK (EB2_INT_EN)
#define EB2_RINTR_MASK (EB2_INT_EN)
/*
* Misc. defines
*/
#define CS4231_IDNUM (0x6175)
#define CS4231_MINPACKET (0)
#define CS4231_HIWATER (AM_MAX_QUEUED_MSGS_SIZE)
#define CS4231_LOWATER (AM_MIN_QUEUED_MSGS_SIZE)
#define CS4231_REGS (32)
#define CS4231_NCOMPONENTS (1)
#define CS4231_COMPONENT (0)
#define CS4231_PWR_OFF (0)
#define CS4231_PWR_ON (1)
#define CS4231_TIMEOUT (100000)
#define CS4231_NOT_SUSPENDED (0)
#define CS4231_SUSPENDED (~CS4231_NOT_SUSPENDED)
/*
* Supported dma engines and the ops vector
*/
typedef enum cs_dmae_types cs_dmae_types_e;
/*
* Hardware registers
*/
struct cs4231_pioregs {
};
typedef struct cs4231_pioregs cs4231_pioregs_t;
struct cs4231_eb2 {
};
typedef struct cs4231_eb2 cs4231_eb2_t;
struct cs4231_regs {
};
typedef struct cs4231_regs cs4231_regs_t;
/*
* Misc. state enumerations and structures
*/
struct cs4231_handle {
};
typedef struct cs4231_handle cs4231_handle_t;
/*
* CS_state_t - per instance state and operation data
*/
struct CS_state {
int cs_instance; /* device instance */
int cs_suspended; /* power management state */
int cs_powered; /* device powered up? */
int cs_busy_cnt; /* device busy count */
int cs_pbuf_toggle; /* play DMA buffer toggle */
int cs_cbuf_toggle; /* capture DMA buffer toggle */
};
typedef struct CS_state CS_state_t;
/* CS_state.flags defines */
/*
* DMA ops vector definition
*/
struct cs4231_dma_ops {
char *dma_device;
void (*cs_dma_unmap_regs)(CS_state_t *);
void (*cs_dma_reset)(CS_state_t *);
int (*cs_dma_add_intr)(CS_state_t *);
void (*cs_dma_rem_intr)(dev_info_t *);
int (*cs_dma_p_start)(CS_state_t *);
void (*cs_dma_p_pause)(CS_state_t *);
void (*cs_dma_p_restart)(CS_state_t *);
void (*cs_dma_p_stop)(CS_state_t *);
int (*cs_dma_r_start)(CS_state_t *);
void (*cs_dma_r_stop)(CS_state_t *);
void (*cs_dma_power)(CS_state_t *, int);
};
typedef struct cs4231_dma_ops cs4231_dma_ops_t;
extern cs4231_dma_ops_t cs4231_apcdma_ops;
extern cs4231_dma_ops_t cs4231_eb2dma_ops;
#define CS4231_DMA_MAP_REGS(DIP, S, P, C) \
/*
* Useful bit twiddlers
*/
#define CS4231_RETRIES 10
/*
* CS4231 Register Set Definitions
*/
/* Index Address Register */
/* Status Register */
/* Index 00 - Left ADC Input Control, Modes 1&2 */
/* Index 01 - Right ADC Input Control, Modes 1&2 */
/* Index 02 - Left Aux #1 Input Control, Modes 1&2 */
/* Index 03 - Right Aux #1 Input Control, Modes 1&2 */
/* Index 04 - Left Aux #2 Input Control, Modes 1&2 */
/* Index 05 - Right Aux #2 Input Control, Modes 1&2 */
/* Index 06 - Left DAC Output Control, Modes 1&2 */
/* Index 07 - Right DAC Output Control, Modes 1&2 */
/* Index 08 - Sample Rate and Data Format, Mode 2 only */
/* Index 09 - Interface Configuration, Mode 1&2 */
/* Index 10 - Pin Control, Mode 1&2 */
/* Index 11 - Error Status and Initialization, Mode 1&2 */
/* Index 12 - Mode and ID, Modes 1&2 */
/* Index 13 - Loopback Control, Modes 1&2 */
/* Index 14 - Playback Upper Base, Mode 2 only */
/* Index 15 - Playback Lower Base, Mode 2 only */
/* Index 16 - Alternate Feature Enable 1, Mode 2 only */
/* Index 17 - Alternate Feature Enable 2, Mode 2 only */
/* Index 18 - Left Line Input Control, Mode 2 only */
/* Index 19 - Right Line Input Control, Mode 2 only */
/* Index 20 - Timer Lower Byte, Mode 2 only */
/* Index 21 - Timer Upper Byte, Mode 2 only */
/* Index 22 and 23 are reserved */
/* Index 24 - Alternate Feature Status, Mode 2 only */
/* Index 25 - Version and ID, Mode 2 only */
/* Index 26 - Mono I/O Control, Mode 2 only */
/* Index 27 is reserved */
/* Index 28 - Capture Data Format, Mode 2 only */
/* Index 29 is reserved */
/* Index 30 - Capture Upper Base, Mode 2 only */
/* Index 31 - Capture Lower Base, Mode 2 only */
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_AUDIO4231_IMPL_H */