audio1575_impl.h revision 75d01c9ab5ef6f1bbac9f9d4eb379d5c38583d82
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_AUDIO1575_IMPL_H_
#define _SYS_AUDIO1575_IMPL_H_
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Implementation specific header file for the audio1575 device driver.
*/
#ifdef _KERNEL
/* Misc. defines */
#define M1575_IDNUM (0x5455)
#define M1575_CONFIG_DEVICE_ID M1575_IDNUM
#define M1575_CONFIG_VENDOR_ID (0x10b9)
#define M1575_CONFIG_SUBSYSTEM_ID M1575_IDNUM
#define M1575_AUDIO_PCICFG_SPACE (0)
#define M1575_AUDIO_IO_SPACE (1)
#define M1575_AUDIO_MEM_SPACE (2)
#define M1575_MINPACKET (0)
#define M1575_LOOP_CTR (100)
/* Gain and attenuation shift values */
#define M1575_GAIN_SHIFT3 (3)
#define M1575_GAIN_SHIFT4 (4)
#define M1575_BYTE_SHIFT (8)
/* audio direction */
#define M1575_DMA_PCM_IN (1)
#define M1575_DMA_PCM_OUT (2)
/* last AC97 saved register */
#define M1575_LAST_AC_REG (0x3a)
/* Restore audio flags */
#define M1575_INIT_RESTORE (0)
#define M1575_INIT_NO_RESTORE ~M1575_INIT_RESTORE
/* AC97 codec shadow reg to index macro */
#define M1575_CODEC_REG(r) ((r) >> 1)
/* play and record sample buffer counts */
#define M1575_PLAY_BUFS (2)
#define M1575_REC_BUFS (4)
/* Buffer Descriptor List defines */
#define M1575_BD_NUMS (32)
#define M1575_BD_SIZE \
(M1575_BD_NUMS * sizeof (m1575_bd_entry_t))
/* default buffer size */
#define M1575_MOD_SIZE (16)
#define M1575_PLAY_BUF_SZ (1024)
#define M1575_RECORD_BUF_SZ (1024)
#define M1575_BUF_MIN (512)
#define M1575_BUF_MAX (8192)
/* Audio channel defines */
#define M1575_MAX_CHANNELS (32)
#define M1575_MAX_HW_CHANNELS (6)
#define M1575_MAX_IN_CHANNELS (1)
#define M1575_MAX_OUT_CHANNELS \
#define M1575_INPUT_STREAM 1
#define M1575_PORT_UNMUTE 0xffffffff
/* kstat interrupt counter define */
/* AD1981B Specific Definitions */
#define AC97_MISC_CONTROL_BIT_REGISTER 0x76
#define MIC_20dB_GAIN 0x0000
#define MIC_10dB_GAIN 0x0001
#define MIC_30dB_GAIN 0x0010
#define C2MIC 0x0040
#define C1MIC 0x0000
#define AC97_MIXER_ADC_GAIN_REGISTER 0x64
#define MIXER_GAIN_MUTE 0x8000
#define MIXER_0db_GAIN_ 0x0000
/* PCI CFG SPACE REGISTERS for Audio (Device 29, Function 0) */
/* Bit definitions for PCI AC97 Clk detect Reg */
#define M1575_PCIACD_CLKDET 0x01
#define M1575_PCIMISC_INTENB 0x40
#define M1575_PCIINT_LINE 0x05
/* Base Line Audio I/O Memory Registers */
/* PCM IN Registers */
/* PCM OUT Registers */
/* MIC In Registers */
/* SPIDOF Registers */
/* PCM IN2 Registers */
/* MIC2 IN2 Registers */
/* Bits of FIFO Control Register1 */
/* Bits of FIFO Control Register2 */
/* Bits of FIFO Control Register3 */
/* Bits of DMA Control Register */
#define M1575_DMACR_PCMISTART 0x00000001
#define M1575_DMACR_PCMOSTART 0x00000002
#define M1575_DMACR_MICISTART 0x00000004
#define M1575_DMACR_CSPOSTART 0x00000008
#define M1575_DMACR_CENOSTART 0x00000010
#define M1575_DMACR_LFEOSTART 0x00000020
#define M1575_DMACR_SPISTART 0x00000040
#define M1575_DMACR_SPOSTART 0x00000080
#define M1575_DMACR_I2SISTART 0x00000100
#define M1575_DMACR_PCMI2START 0x00000200
#define M1575_DMACR_MICI2START 0x00000400
#define M1575_DMACR_PCMIPAUSE 0x00010000
#define M1575_DMACR_PCMOPAUSE 0x00020000
#define M1575_DMACR_MICIPAUSE 0x00040000
#define M1575_DMACR_CSPOPAUSE 0x00080000
#define M1575_DMACR_CENOPAUSE 0x00100000
#define M1575_DMACR_LFEOPAUSE 0x00200000
#define M1575_DMACR_SPIPAUSE 0x00400000
#define M1575_DMACR_SPOPAUSE 0x00800000
#define M1575_DMACR_I2SIPAUSE 0x01000000
#define M1575_DMACR_PCMI2PAUSE 0x02000000
#define M1575_DMACR_MICI2PAUSE 0x04000000
#define M1575_DMACR_PAUSE_ALL 0x07ff0000
/* Bits of INTRSR Interrupt Status Register */
#define M1575_INTRSR_GPIOINTR 0x0000002
#define M1575_INTRSR_SPRINTR 0x0000020
#define M1575_INTRSR_CPRINTR 0x0000080
#define M1575_INTRSR_PCMIINTR 0x0010000
#define M1575_INTRSR_PCMOINTR 0x0020000
#define M1575_INTRSR_MICIINTR 0x0040000
#define M1575_INTRSR_CSPOINTR 0x0080000
#define M1575_INTRSR_CENOINTR 0x0100000
#define M1575_INTRSR_LFEOINTR 0x0200000
#define M1575_INTRSR_SPIINTR 0x0400000
#define M1575_INTRSR_SPOINTR 0x0800000
#define M1575_INTRSR_I2SIINTR 0x1000000
#define M1575_INTRSR_PCMI2INTR 0x2000000
#define M1575_INTRSR_MICI2INTR 0x4000000
#define M1575_INTR_MASK (M1575_INTRSR_GPIOINTR |\
#define M1575_UNUSED_INTR_MASK (M1575_INTRSR_GPIOINTR |\
/* Defines a generic clear for all MIC and PCM Status Registers */
#define M1575_STATUS_CLR 0x001e
/* Defines a generic RESET for all MIC and PCM Control Registers */
#define M1575_CR_RR 0x02
#define M1575_SR_DMACS 0x01
/* Bits of PCM In Status Register */
#define M1575_PCMISR_CELV 0x02
#define M1575_PCMISR_LVBCI 0x04
#define M1575_PCMISR_BCIS 0x08
#define M1575_PCMISR_FIFOE 0x10
/* Bits in PCM In Control Register */
/* Bits of PCM Out Status Register */
#define M1575_PCMOSR_CELV 0x02
#define M1575_PCMOSR_LVBCI 0x04
#define M1575_PCMOSR_BCIS 0x08
#define M1575_PCMOSR_FIFOE 0x10
/* Bits in PCM Out Control Register */
/* Bits of MIC In Status Register */
#define M1575_MICISR_CELV 0x02
#define M1575_MICISR_LVBCI 0x04
#define M1575_MICISR_BCIS 0x08
#define M1575_MICISR_FIFOE 0x10
/* Bits in PCM In Control Register */
/* Bits in System Control Register */
#define M1575_SCR_WARMRST 0x00000001
#define M1575_SCR_COLDRST 0x00000002
#define M1575_SCR_DRENT 0x40000000
#define M1575_SCR_MSTRST 0x80000000
/* Bits in System Status Register */
#define M1575_SSR_RSTBLK 0x00000002
#define M1575_SSR_FACCS_MSK 0x00000018
#define M1575_SSR_SCID 0x00000040
/* Bits in Command Port Register */
#define M1575_CPR_READ 0x0080
/* Bits in Cmd Status Port Register */
/* Bits in Interface Control Register */
#define M1575_INTFCR_RSTREL 0x02000000
#define M1575_INTFCR_RSTBLK 0x00200000
#define M1575_INTFCR_MICENB 0x00100000
#define M1575_INTFCR_PCMIENB 0x00080000
#define M1575_INTFCR_MICI2ENB 0x00040000
#define M1575_INTFCR_PCMI2ENB 0x00020000
#define M1575_INTFCR_MICI2SEL 0x00008000
#define M1575_INTFCR_MICISEL 0x00004000
#define M1575_INTFCR_PCMOENB 0x00000002
#define M1575_INTRCR_CPRINTR 0x00000080
#define M1575_INTRCR_SPRINTR 0x00000020
#define M1575_INTRCR_GPIOINTR 0x00000002
/* Bits of Recv Tag Slot Register */
/* Semaphore busy */
#define M1575_CASR_SEMBSY 0x80000000
/* AD1981 codec vendor ID */
#define AD1981_VID1 0x4144
#define AD1981_VID2 0x5374
/* AD1981B Codec Registers */
#define AD1981_RESET_REG 0x00
#define AD1981_MSTVOL_REG 0x02
#define AD1981_HPHVOL_REG 0x04
#define AD1981_MONOVOL_REG 0x06
#define AD1981_MICVOL_REG 0x0E
#define AD1981_CDVOL_REG 0x12
#define AD1981_PCMOVOL_REG 0x18
#define AD1981_RECSEL_REG 0x1A
#define AD1981_RECGAIN_REG 0x1C
#define AD1981_GENPUR_REG 0x20
#define AD1981_PWRCSR_REG 0x26
#define AD1981_EXTID_REG 0x28
#define AD1981_EXTCSR_REG 0x2A
#define AD1981_PCMDAC_REG 0x2C
#define AD1981_PCMADC_REG 0x32
#define AD1981_EQCTRL_REG 0x60
#define AD1981_EQDATA_REG 0x62
#define AD1981_MIXVOL_REG 0x64
#define AD1981_MISCTRL_REG 0x76
#define AD1981_VNDID1_REG 0x7C
#define AD1981_VNDID2_REG 0x7E
/* AD1981B Biquad filter definitions */
#define AD1981_MAX_FILTERS 35
#define AD1981_EQCTRL_EQM 0x8000
#define AD1981_EQCTRL_SYM 0x0080
/*
* Equalizer Biquad Filter Coefficient Address offsets
*/
struct m1575_biquad {
};
typedef struct m1575_biquad m1575_biquad_t;
/*
* chunk buffer
*/
struct m1575_bdlist_chunk {
};
typedef struct m1575_bdlist_chunk m1575_bdlist_chunk_t;
/*
* sample buffer
*/
struct m1575_sample_buf {
int avail; /* the number of available chunk(s) */
};
typedef struct m1575_sample_buf m1575_sample_buf_t;
/*
* buffer descripter list entry, see M1575 datasheet
*/
#define IOC 0x8000
#define BUP 0x4000
struct m1575_bd_entry {
};
typedef struct m1575_bd_entry m1575_bd_entry_t;
/*
* PCI config space register layout
*/
struct audio1575_pci_regs {
};
typedef struct audio1575_pci_regs audio1575_pci_regs_t;
/*
* M1575 audio register layout
*/
struct audio1575_audio_regs {
};
typedef struct audio1575_audio_regs audio1575_audio_regs_t;
/*
* audio1575_state_t per instance state and operation data
*/
struct audio1575_state {
int m1575_inst; /* dev instance */
int m1575_intr_type; /* intr type */
void *m1575_bdl_virtual; /* virt addr of BDL */
int m1575_csamples; /* pcmin samples/int */
int m1575_psamples; /* pcmout samples/int */
int m1575_play_buf_size; /* size of in buf */
int m1575_record_buf_size; /* size of in buffer */
};
typedef struct audio1575_state audio1575_state_t;
/* audio1575_state_t.flags defines */
/* bits of audio1575_state_t.m1575_res_flags */
#define M1575_RS_PCI_REGS 0x0001
#define M1575_RS_AM_REGS 0x0002
#define M1575_RS_BM_REGS 0x0004
#define M1575_RS_DMA_BDL_HANDLE 0x0008
#define M1575_RS_DMA_BDL_MEM 0x0010
#define M1575_RS_DMA_BDL_BIND 0x0020
/* PCI Config register macros */
#define M1575_PCI_GET8(reg) \
#define M1575_PCI_GET16(reg) \
#define M1575_PCI_GET32(reg) \
/* audio i/o register macros */
#define M1575_AM_GET8(reg) \
#define M1575_AM_GET16(reg) \
#define M1575_AM_GET32(reg) \
/* audio memory bus master registers */
#define M1575_BM_GET8(reg) \
#define M1575_BM_GET16(reg) \
#define M1575_BM_GET32(reg) \
"correctly until it is stopped and restarted"); \
} \
}
"correctly until it is stopped and restarted"); \
} \
}
"correctly until it is stopped and restarted"); \
} \
}
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_AUDIO1575_IMPL_H_ */