eri_mac.h revision 297a64e7779d7bd7140d1f3f2fa5db171aa21569
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_ERI_MAC_H
#define _SYS_ERI_MAC_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* HOST MEMORY DATA STRUCTURES
* Transmit and Receive Descriptor Rings
*/
/* The Descriptor Ring base Addresses must be 2K-byte aligned */
#define ERI_GMDALIGN (2048)
/*
* The transmit and receiver Descriptor Rings are organized as "wrap-around
* descriptors and are of programmable size.
* and a pointer to a data buffer.
* The no. of entries is programmable in binary increments, from 32 to 8192.
* TBD: Even though the Receive Desriptor ring size is 8k, provide for a user
* configurable variable to specify the max.no. of Rx buffers posted.
*/
/*
* -----------------------------
* Transmit descriptor structure
* -----------------------------
*/
struct eri_tmd {
};
/* fields in the tmd_flags */
/* valid values in range 0 - 17k */
/* value must be even */
/* value must be even */
/*
* TCP Header offset within Ethernet Packet:
* 14 Bytes Ethernet Header + 20 IP Header.
*/
#define ERI_TCPHDR_OFFSET 34
#define ERI_IPHDR_OFFSET 20
/*
* TCP Checksum stuff offset within Ethernet packet:
* 34 Bytes up to TCP Header + 16 Bytes within TCP header
*/
#define ERI_TCPCSUM_OFFSET 50
#define ERI_TMDCSUM_CTL (ERI_TMD_CSENABL | \
(ERI_TCPHDR_OFFSET << ERI_TMD_CSSTART_SHIFT) | \
/*
* Programming Notes:
*
* 1. TX Kick Register is used to hand over TX descriptors to the hardware.
* TX Completion Register is used by hardware to handover TX descriptors
* back to the software.
*
* 2. ERI never writes back TX descriptors.
*
* 2. If a packet resides in more than one buffer, the Checksum_Enable,
* Checksum_Stuff_Offset, Checksum_Start_Offset and Int_me fields need to
* be set only in the first descriptor for the packet.
*
* 3. The hardware implementation relies on the fact that if a buffer
* starts at an "odd" boundary, the DMA state machine can "rewind"
* to the nearest burst boundary and execute a full DVMA burst Read.
*
* There is no other alignment restriction for the transmit data buffer.
*/
/*
* -----------------------------
* Receive Descriptor structure
* ----------------------------
*/
struct rmd {
};
/*
* fields in the rmd_flags
*/
/* 0 - owned by software */
/* 1 - owned by hardware */
/* 61 : matched alternate MAC adrs */
#define ERI__RMD_BUFALIGN 8
/*
* ERI REGISTER SPACE
* The comments are in the following format:
* Addres_Offset R/W Default Actual_size(bits) Description
*/
/*
* Global Register Space : Paritally Modified for ERI
*/
struct global {
};
/*
*
* SBus IO configuration (RW)
* To configure parameters that define the DMA burst and internal arbitration.
*/
/*
* SEB State Register (RO)
* Reflects the internal state of the arbitration between TX and RX
* DMA Channels. Used for diagnostics only
*/
/*
* Global Configuration Register (RW)
* To configure parameters that define the DMA burst and internal arbitration.
* TX/RX_DMA_LIMIT: No. of data transfers in 64-byte multiples
* 0 - peririty changes at packet boundaries
* default: 0x042
*/
#define ERI_G_CONFIG_TX_DMA_LIM_SHIFT 1
#define ERI_G_CONFIG_RX_DMA_LIM_SHIFT 6
/*
* Global Interrupt Status Register (R-AC)
* size: 32 bits: 0-31
* default: 0x00000000
* This is the top level register used to communicate to the software events
* that were detected by the hardware.
* Top level bits 0-6 are automatically cleared to 0 when the Status Register
* is read.
* Second level interrupts reported by bits 13-18 are cleared at the source.
* The value of the TX Completion Register is replicated in bits 19-31.
*/
#define ERI_G_STATUS_TX_INT_ME (1 << 0)
/* 0 - set when a frame with INT_ME bit set is transferred to FIFO */
#define ERI_G_STATUS_FATAL_ERR (ERI_G_STATUS_RX_TAG_ERR | \
#define ERI_G_STATUS_NONFATAL_ERR (ERI_G_STATUS_TX_MAC_INT | \
#define ERI_G_STATUS_TX_COMPL_SHIFT 19
#define ERI_G_STATUS_TX_COMPL_MASK 0x1fff
/*
* Global Interrupt Mask register (RW)
* size: 32 bits
* default: 0xFFFFFFFF
* There is one-to-one correspondence between the bits in this register and
* the Global Status register.
* If a mask bit is 0, the corresponding event causes an interrupt.
*/
#define ERI_G_MASK_TX_INT_ME (1 << 0)
/* 0 - set when a frame with INT_ME bit set is transferred to FIFO */
#define ERI_G_MASK_ALL (0xffffffffu)
/*
* Interrupt Ack Register (WO)
* Its layout corresponds to the layout of the top level bits of the Interrupt
* Status register.
* Bit positions written high will be cleared, while bit positions written low
* have no effect on the Interrupt Status Register.
*/
/*
* Status Register Alias (RO)
* This location presents the same view as the Interrupt Status Register, except
* that reading from this location does not automatically clear any of the
* register bits.
*/
/*
* PCI Error Status Register (R-AC)
* Other PCI bus errors : The specific error may be read from
* the PCI Status Register in PCI Configuration space
*/
/*
* PCI Error Mask Register (RW)
* size: 32 bits
* default: 0xffffffff
* Same layout as the PCI Error Status Register
*/
#define ERI_G_PCI_ERROR_MASK 0x00
/*
* BIF Configuration Register
* default: 0x0
* Used to configure specific system information for the BIF block to optimize.
* Default values indicate no special knowledge is assumed by BIF.
* M66EN is RO bit.
* 66 MHz operation (RO) May be used by the driver to sense
* whether ERI is operating in a 66MHz or 33 MHz PCI segment
*/
/*
* BIF Diagnostic register (RW)
* TBD
*/
/*
* Global Software Reset Register - RW-AC
* The lower 2bits are used to perform an individual Software Reset to the
* TX or RX functions (when the corresponding bit is set), or
* a Global Software Reset to the ERI (when both bits are set).
* These bits become "self cleared" after the corresponding reset command
* has been executed. After a reset, the software must poll this register
* till both the bits are read as 0's.
* The third bit (RSTOUT) is not self clearing and is used to activate
* the RSTOUT# pin, when set. When clear, RSTOUT# follows the level of the
* PCI reset input pin.
*/
#define ERI_G_CACHE_BIT 16
/*
* Transmit DMA Register set
* tx_kick and tx_completion registers are set to 0 when ETX is reset.
*/
struct etx {
};
/*
* TX Kick Register (RW)
* size: 13-bits
* default: 0x0
* Written by the host CPU with the descriptor value that follows the last
* valid Transmit descriptor.
*/
/*
* TX Completion Register
* size: 13-bits
* default: 0x0
* This register stores the descriptor value that follows the last descriptor
* already processed by ERI.
*
*/
#define ETX_COMPLETION_MASK 0x1fff
/*
* ETX Configuration Register
* default: 0x118010
* This register stores parameters that control the operation of the transmit
* DMA channel.
* If the desire is to buffer an entire standard Ethernet frame before its
* transmission is enabled, the Tx-FIFO-Threshold field has to be programmed
* to a value = > 0xC8. (CHECK). Default value is 0x460.
* Matewos: Changed the above to 0x400. Getting FIFO Underflow in the
* case if Giga bit speed.
* Bit 21 is used to modify the functionality of the Tx_All interrupt.
* If it is 0, Tx_All interrupt is generated after processing the last
* transmit descriptor.
* If it is 1, Tx_All interrupt is generated only after the entire
* Transmit FIFO has been drained.
*/
/*
* RIO specific value: TXFIFO threshold needs to be set to 1518/8.
* It was set to (0x4FF << 10) for GEM.
* set it back to 0x4ff.
* set it to 190 receive TXMAC underrun and hang
* try 0x100
* try 0x4ff
* try 0x100
*/
#define ETX_ERI_THRESHOLD 0x100
/*
* ETX TX ring size
* This is a 4-bit value to determine the no. of descriptor entries in the
* TX-ring. The number of entries can vary from 32 through 8192 in multiples
* of 2.
*/
#define ERI_TX_RINGSZ_SHIFT 1
#define ETX_RINGSZ_32 0
#define ETX_RINGSZ_64 1
#define ETX_RINGSZ_128 2
#define ETX_RINGSZ_256 3
#define ETX_RINGSZ_512 4
#define ETX_RINGSZ_1024 5
#define ETX_RINGSZ_2048 6
#define ETX_RINGSZ_4096 7
#define ETX_RINGSZ_8192 8
/* values 9-15 are reserved. */
/*
* Transmit Descriptor Base Low and High (RW)
* The 53 most significant bits are used as the base address for the TX
* descriptor ring. The 11 least significant bits are not stored and assumed
* to be 0.
* This register should be initialized to a 2KByte-aligned value after power-on
* or Software Reset.
*/
/*
* TX FIFO size (RO)
* This 11-bit RO register indicates the size, in 64 byte multiples, of the
* TX FIFO.
* The value of this register is 0x90, indicating a 9Kbyte TX FIFO.
*/
/*
* ERX Register Set
*/
struct erx {
};
/*
* ERX Configuration Register - RW
* This 27-bit register determines the ERX-specific parameters that control the
* operation of the receive DMA channel.
* Default : 0x1000010
*/
#define ERI_RX_RINGSZ_SHIFT 1
#define ERI_RX_CONFIG_FBO_SHIFT 10
#define ERI_RX_CONFIG_RX_CSSTART_SHIFT 13
#define ERI_RX_CONFIG_RXFIFOTH_SHIFT 24
#define ERX_RINGSZ_32 0
#define ERX_RINGSZ_64 1
#define ERX_RINGSZ_128 2
#define ERX_RINGSZ_256 3
#define ERX_RINGSZ_512 4
#define ERX_RINGSZ_1024 5
#define ERX_RINGSZ_2048 6
#define ERX_RINGSZ_4096 7
#define ERX_RINGSZ_8192 8
/* values 9-15 are reserved. */
#define ERI_RX_FIFOTH_64 0
#define ERI_RX_FIFOTH_128 1
#define ERI_RX_FIFOTH_256 2
#define ERI_RX_FIFOTH_512 3
#define ERI_RX_FIFOTH_1024 4
#define ERI_RX_FIFOTH_2048 5
/* 6 & 7 are reserved values */
/*
* Receive Descriptor Base Low and High (RW)
* The 53 most significant bits are used as the base address for the RX
* descriptor ring. The 11 least significant bits are not stored and assumed
* to be 0.
* This register should be initialized to a 2KByte-aligned value after power-on
* or Software Reset.
*/
/*
* Pause Thresholds Register (RW)
* default: 0x000f8
* Two PAUSE thresholds are used to define when PAUSE flow control frames are
* emitted by ERI. The granularity of these thresholds is in 64 byte increments.
* XOFF PAUSE frames use the pause_time value pre-programmed in the
* Send PAUSE MAC Register.
* XON PAUSE frames use a pause_time of 0.
*/
#define ERI_RX_PTH_OFFTH (0x1ff << 0)
/*
* 0-8: XOFF PAUSE emitted when RX FIFO
* occupancy rises above this value (times 64 bytes)
*/
/*
* 12-20: XON PAUSE emitted when RX FIFO
* occupancy falls below this value (times 64 bytes)
*/
#define ERI_RX_PTH_ONTH_SHIFT 12
/*
* ------------------------------------------------------------------------
* RX Kick Register (RW)
* This is a 13-bit register written by the host CPU.
* The last valid RX descriptor is the one right before the value of the
* register.
* Initially set to 0 on reset.
* RX descriptors must be posted in multiples of 4.
* The first descriptor should be cache-line aligned for best performance.
* -------------------------------------------------------------------------
*/
/*
* RX Completion Register (RO)
* This 13-bit register indicates which descriptors are already used by ERI
* for receive frames.
* All descriptors upto but excluding the register value are ready to be
* processed by the host.
*/
/*
* RX Blanking Register (RW)
* Defines the values used for receive interrupt blanking.
* For INTR_TIME field, every count is 2048 PCI clock time. For 66 Mhz, each
* count is about 16 us.
*/
#define ERI_RX_BLNK_INTR_PACKETS (0x1ff << 0)
/*
* 0-8:no.of pkts to be recvd since the last RX_DONE
* interrupt, before a new interrupt
*/
/*
* 12-19 : no. of clocks to be counted since the last
* RX_DONE interrupt, before a new interrupt
*/
#define ERI_RX_BLNK_INTR_TIME_SHIFT 12
/*
* RX FIFO Size (RO)
* This 11-bit RO register indicates the size, in 64-bit multiples, of the
* RX FIFO. Software should use it to properly configure the PAUSE thresholds.
* The value read is 0x140, indicating a 20kbyte RX FIFO.
*/
/*
* Declarations and definitions specific to the ERI MAC functional block.
*
* The ERI MAC block will provide the MAC functons for 10 or 100 Mbps or
* 1 Gbps CSMA/CD-protocol-based or full-duplex interface.
*/
/*
* ERI MAC Register Set.
* ERI MAC addresses map on a word boundry. So all registers are
* declared for a size of 32 bits. Registers that use fewer than 32
* bits will return 0 in the bits not used.
* TBD: Define the constant values which should be used for initializing
* these registers.
*/
struct bmac {
};
#define BMAC_OVERFLOW_STATE 0x03800000
/*
* Constants used for initializing the MAC registers
*/
#define BMAC_SEND_PAUSE_CMD 0x1BF0
#define BMAC_IPG0 0x00
#define BMAC_IPG1 0x08
#define BMAC_IPG2 0x04
#define BMAC_SLOT_TIME 0x40
#define BMAC_EXT_SLOT_TIME 0x200
#define BMAC_MIN_FRAME_SIZE 0x40
/*
* Hardware bug: set MAC_FRAME_SIZE to 0x7fff to
* get around the problem of tag errors
*/
#ifdef ERI_RX_TAG_ERROR_WORKAROUND
#define BMAC_MAX_FRAME_SIZE_TAG 0x7fff
#endif
#define BMAC_PREAMBLE_SIZE 0x07
#define BMAC_JAM_SIZE 0x04
#define BMAC_ATTEMPT_LIMIT 0x10
#define BMAC_CONTROL_TYPE 0x8808
#define BMAC_ADDRESS_3 0x0000
#define BMAC_ADDRESS_4 0x0000
#define BMAC_ADDRESS_5 0x0000
#define BMAC_ADDRESS_6 0x0001
#define BMAC_ADDRESS_7 0xC200
#define BMAC_ADDRESS_8 0x0180
#define BMAC_AF_0 0x0000
#define BMAC_AF_1 0x0000
#define BMAC_AF_2 0x0000
#define BMAC_AF21_MASK 0x00
#define BMAC_AF0_MASK 0x0000
/*
* ERI MAC Register Bit Masks.
*/
/*
* TX_MAC Software Reset Command Register (RW)
* This bit is set to 1 when a PIO write is done. This bit becomes self-cleared.
* after the command has been executed.
*/
/*
* RX_MAC Software Reset Command Register (RW)
* This bit is set to 1 when a PIO write is done. This bit becomes self-cleared.
* after the command has been executed.
*/
/*
* Send Pause Command Register (RW)
* This command register executes a Pause Flow Control frame transmission.
* Pause_Time_Sent field indicates to the MAC the value of the pause_time
* operand that should be sent on the network using either the Send_Pause
* Command bit or the flow control handshake on the RxDMA < - > MAC interface.
* The pause-time is interpreted in terms of Slot times.
*/
/*
* 0-15: value of pause_time operand
* in terms of slot time
*/
#define ERI_MCTLSP_TIME (0xffff << 0)
/*
* TX_MAC Status Register (R-AC)
*/
/*
* TX_MAC Mask Register (RW)
*/
/* Matewos added defer counter */
/*
* RX_MAC Status Register (R-AC)
*/
/*
* RX_MAC Mask Register (R-AC)
*/
/*
* MAC Control Status Register (R-AC)
*/
#define ERI_MCTLSTS_PAUSE_TIME_SHIFT 16
/*
* MAC Control Mask Register (RW)
* pause time is in slot-time units.
*/
#define ERI_MACCTL_INTR_MASK 0x00000000
/*
* XIF Configuration Register
* This register determines the parameters that control the operation of the
* transceiver interface.
* The Disable-echo bit should be 0 for full-duplex mode.
* Default: 0x00
*/
/*
* TX_MAC Configuration Register
* Ignore_Carrier_Sense should be set to 1 for full-duplex operation and
* cleared to 0 for half-duplex operation..
* Ignore_collisions should be set to 1 for full-duplex operation and cleared
* to 0 for half-duplex operation..
* To Ensure proper operation of the TX_MAC, the TX_MAC_Enable bit must always
* be cleared to 0 and a delay imposed before a PIO write to any of the other
* bits in the TX_MAC Configuration register or any of the MAC parameter
* registers is done.
* The amount of delay required depends on the time required to transmit a max.
* size frame.
* Default: TBD
*/
/* CHECK */
/*
* Enable TX Carrier Extension Carrier Extension is
* required for half-duplex operation at Gbps
*/
/*
* RX_MAC Configuration Register
* A delay of 3.2 ms should be allowed after clearing Rx_MAC_Enable or
* Hash_Filter_enable or Address_Filter_Enable bits.
* Default: TBD
*/
/* CHECK 3ms or us */
/* GEM specification: 3.2msec (3200 usec) */
/*
* Enable RX Carrier Extension.
* Enables the reception of packet bursts
* generated by Carrier Extension with
* packet bursting senders
*/
/*
* MAC Control Configuration Register (RW)
* Default: 0x00
*/
/*
* MAC Control Type Register (RW)
* This 16-bit register specifies the "type" field for the MAC Control frame.
* Default: 0x8808
*/
/*
* MAC Address Registers 0, 1, 2
* Station's Normal peririty MAC address which must be a unicast address.
* 0 - [15:0], 1 - [31:16], 2 - [47:32]
*/
/*
* MAC Address Registers 3, 4, 5
* Station's Alternate MAC address which may be a unicast or multicast address.
* 3 - [15:0], 4 - [31:16], 5 - [47:32]
*/
/*
* MAC Address Registers 6, 7, 8
* Station's Control MAC address which must be the reserved multicast
* address for MAC Control frames.
* 6 - [15:0], 7 - [31:16], 8 - [47:32]
*/
/*
* MII Transceiver Interface
*
* The Management Interface (MIF) allows the host to program and collect status
* from two transceivers connected to the MII. MIF supports three modes of
* operation:
* 1. Bit-Bang Mode
* This mode is imlemented using three 1-bit registers: data, clock,
* and output_enable.
*
* 2. Frame Mode
* This mode is supported using one 32-bit register: Frame register.
* The software loads the Frame Register with avalid instaruction
* ("frame"), and polls the Valid Bit for completion.
*
* 3. Polling Mode
* The Polling mechanism is used for detecting a status change in the
* transceiver. When this mode is enabled, the MIF will continuously
* poll a specified transceiver register and generate a maskable
* interrupt when a status change is detected. This mode of operation
* can only be used when the MIF is in the "Frame mode".
*
*/
struct mif {
};
/*
* mif_bbclk - Bit Bang Clock register
*/
#define ERI_BBCLK_LOW 0
#define ERI_BBCLK_HIGH 1
/* mif_bbdata - bit Bang Data register */
/* mif_bbopenb - Bit Bang oOutput Enable register */
/*
* Management Frame Structure:
* <IDLE> <ST><OP><PHYAD><REGAD><TA> <DATA> <IDLE>
* READ: <01><10><AAAAA><RRRRR><Z0><DDDDDDDDDDDDDDDD>
* WRITE: <01><01><AAAAA><RRRRR><10><DDDDDDDDDDDDDDDD>
*/
/*
* mif_frame - MIF control and data register
*/
#define ERI_MIF_FRREGAD_SHIFT 18
#define ERI_MIF_FRPHYAD_SHIFT 23
#define ERI_MIF_FRREAD 0x60020000
#define ERI_MIF_FRWRITE 0x50020000
/*
*/
#define ERI_MAX_MIF_DELAY (100)
/*
* maximum delay for Transceiver Reset
*/
#define ERI_PHYRST_MAXDELAY (500)
#define ERI_PCS_PHYRST_MAXDELAY (500)
/*
* mif_cfg - MIF Configuration Register
*/
#define ERI_MIF_CFGPR_SHIFT 3
#define ERI_MIF_CFGPD_SHIFT 10
#define ERI_MIF_POLL_DELAY 200
/*
* MDIO_0 corresponds to the On Board Transceiver.
* MDIO_1 corresponds to the External Transceiver.
* The PHYAD for both is 0.
*/
#define ERI_EXTERNAL_PHYAD 0 /* PHY address for ext. transceiver */
/* mif_imask - MIF Interrupt Mask Register */
/*
*/
/* mif_bassts - MIF Basic - Status register */
/*
* The Basic portion of this register indicates the last value of the register
* read indicated in the POLL REG field of the Configuration Register.
* The Status portion indicates bit(s) that have changed.
* The MIF Mask register is corresponding to this register in terms of the
* bit(s) that need to be masked for generating interrupt on the MIF Interrupt
* Bit of the Global Status Rgister.
*/
/* mif_fsm - MIF State Machine register */
/*
* ERI PCS/Serial-Link
*/
struct pcslink {
};
/*
* PCS MII Basic Mode Control Register
* Auto-Negotiation should always be used for 802.3z 8B/10B
* link configuration. May be cleared for diagnostic purposes, or
* as a workaround for possible early product interoperability problems.
*/
#define PCS_AUTONEG_DISABLE 0
/*
* ------------------------------------------------------------------------
* PCS MII Basic Mode Status Register
* -------------------------------------------------------------------------
*/
/*
* ------------------------------------------------------------------------
* PCS MII Auto-Negotiation Advertisement Register (nway1Reg)
* This register will hold the different modes of operation to be advertised to
* the far-end PHY.
* -------------------------------------------------------------------------
*/
/* Capability word */
/* ************************************************************************ */
/*
* PCS MII Auto-Negotiation Link Partner Ability Reg
* This register contains the Link Partners capabilities after NWay
* Auto-Negotiation is complete.
*/
/* Capability word */
/*
* ------------------------------------------------------------------------
* PCS Configuration Register
* Default = 0x8
* -------------------------------------------------------------------------
*/
/* Timer values used for the 802.3z Clause 36 Link Monitor s/m timers */
/*
* ------------------------------------------------------------------------
* PCS Interrupt State Register
* Presently only one bit is implemented, reflecting transitions on the link
* status. Note that there is no mask register at this level.
* THe PCS_INT bit may be masked at the Interrupt Status Register level.
* -------------------------------------------------------------------------
*/
/*
* ------------------------------------------------------------------------
* Datapath Mode Register (RW)
* This register controls which network interface is used.
* Only one bit should be set in this register.
* Default: 0x1
* -------------------------------------------------------------------------
*/
/*
* Selection between MII and GMII is
* controlled by the XIF register
*/
/*
* Applicable only in Serial Mode
* When set, makes the 10-bit Xmit data
* visible at the GMII
*/
/*
* ------------------------------------------------------------------------
* Serial Link Control register (RW)
* This register controls the Serial link
* Default: 0x000
* -------------------------------------------------------------------------
*/
/*
* ------------------------------------------------------------------------
* Shared Output Select Register (RW)
* Default: 0x00
* -------------------------------------------------------------------------
*/
/*
* ------------------------------------------------------------------------
* Serial Link State Register (RO)
* Indicates the progress of the Serial link boot up
* 00 - Undergoing test
* 01 - Waiting 500us while lockrefn is asserted
* 10 - Waiting for comma detect
* 11 - Receive Data is synchronized
* -------------------------------------------------------------------------
*/
/* ************************************************************************ */
/*
* Definition for the time required to wait after a software
* reset has been issued.
*/
#define ERI_MAX_RST_DELAY (200)
#define ERI_WAITPERIOD ERI_PERIOD
#define ERI_DELAY(c, n) \
{ \
register int N = n / ERI_WAITPERIOD; \
while (--N > 0) { \
if (c) \
break; \
} \
}
{ \
register int N = n / ERI_WAITPERIOD; \
(regad << ERI_MIF_FRREGAD_SHIFT))); \
while (--N > 0) { \
break; \
} \
}
#ifdef __cplusplus
}
#endif
#endif /* _SYS_ERI_MAC_H */