privregs.h revision 2c5124a1a74b6e8fcb1cf8eb9a8d46b5a583086f
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PRIVREGS_H
#define _SYS_PRIVREGS_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file is kernel isa dependent.
*/
/*
* This file describes the cpu's privileged register set, and
* how the machine state is saved on the stack when a trap occurs.
*/
#ifndef _ASM
struct regs {
long long r_tstate;
long long r_g1; /* user global regs */
long long r_g2;
long long r_g3;
long long r_g4;
long long r_g5;
long long r_g6;
long long r_g7;
long long r_o0;
long long r_o1;
long long r_o2;
long long r_o3;
long long r_o4;
long long r_o5;
long long r_o6;
long long r_o7;
/*
*/
long r_pc; /* program counter */
long r_npc; /* next program counter */
int r_y; /* the y register */
};
#endif /* _ASM */
#ifdef _KERNEL
/*
*/
#define SAVE_GLOBALS(RP) \
#define RESTORE_GLOBALS(RP) \
#define RESTORE_OUTS(RP) \
#define SAVE_V8WINDOW(SBP) \
#define SAVE_V8WINDOW_ASI(SBP) \
#define RESTORE_V8WINDOW(SBP) \
#define SAVE_V9WINDOW(SBP) \
#define SAVE_V9WINDOW_ASI(SBP) \
#define RESTORE_V9WINDOW(SBP) \
#define STORE_FPREGS(FP) \
#define LOAD_FPREGS(FP) \
#define STORE_DL_FPREGS(FP) \
#define STORE_DU_FPREGS(FP) \
#define LOAD_DL_FPREGS(FP) \
#define LOAD_DU_FPREGS(FP) \
#endif /* _KERNEL */
/*
* V9 privileged registers
*/
/*
* Condition Codes Register (CCR)
*
* |-------------------------------|
* | XCC | ICC |
* | N | Z | V | C | N | Z | V | C |
* |---|---|---|---|---|---|---|---|
* 7 6 5 4 3 2 1 0
*/
#define CCR_ICC 0x0F
#define CCR_XCC 0xF0
/*
* Processor State Register (PSTATE)
*
* |-------------------------------------------------------------|
* | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG |
* |-----|----|-----|-----|----|-----|-----|----|------|----|----|
* 11 10 9 8 7 6 5 4 3 2 1 0
*
* Note that the IG, MG, RED and AG fields are not applicable to sun4v
* compliant processors.
*/
#ifndef GLREG
#endif /* GLREG */
#ifndef GLREG
#endif /* GLREG */
#ifndef GLREG
#endif /* GLREG */
#define PSTATE_BITS \
"\020\014IG\013MG\012CLE\011TLE\010MM-RMO\
\07MM-PSO\06RED\05PEF\04AM\03PRIV\02IE\01AG"
/*
* Definition of MM (Memory Mode) bit field of pstate.
*/
/*
* Trap State Register (TSTATE)
*
* |------------------------------------------|
* | GL | CCR | ASI | --- | PSTATE | -- | CWP |
* |----|-----|-----|-----|--------|----|-----|
* 42 40 39 32 31 24 23 20 19 8 7 5 4 0
*
* Note that the GL field is applicable to sun4v compliant processors only.
*/
#define TSTATE_CWP_MASK 0x01F
#define TSTATE_CWP_SHIFT 0
#define TSTATE_PSTATE_MASK 0xFFF
#define TSTATE_PSTATE_SHIFT 8
#define TSTATE_ASI_MASK 0x0FF
#define TSTATE_ASI_SHIFT 24
#define TSTATE_CCR_MASK 0x0FF
#define TSTATE_CCR_SHIFT 32
#ifdef GLREG
#define TSTATE_GL_MASK 0x7
#define TSTATE_GL_SHIFT 40
#endif /* GLREG */
/*
* Some handy tstate macros
*/
#define TSTATE_CWP TSTATE_CWP_MASK
/*
* as is 64b, but cc is 32b, so we need this hack.
*/
#ifndef _ASM
#else
#endif
/*
* Initial kernel and user %tstate.
*/
#define PTSTATE_KERN_COMMON \
#define TSTATE_KERN \
#define PSTATE_KERN \
#define TSTATE_USER32 \
((long long)ASI_PNF << TSTATE_ASI_SHIFT))
#define TSTATE_USER64 \
((long long)ASI_PNF << TSTATE_ASI_SHIFT))
#define USERMODE(x) (!((x) & TSTATE_PRIV))
/*
* Window State Register (WSTATE)
*
* |------------|
* |OTHER|NORMAL|
* |-----|------|
* 5 3 2 0
*/
#define WSTATE_BAD 0 /* unused */
#define WSTATE_CLEAN_OFFSET 2
#define WSTATE(o, n) (((o) << WSTATE_SHIFT) | (n))
/*
* Processor Interrupt Level Register (PIL)
*
* |-----|
* | PIL |
* |-----|
* 3 0
*/
/*
* Version Register (VER)
*
* |-------------------------------------------------|
* | manuf | impl | mask | ---- | maxtl | - | maxwin |
* |-------|------|------|------|-------|---|--------|
* 63 48 47 32 31 24 23 16 15 8 7 5 4 0
*/
#define VER_MANUF 0xFFFF000000000000
#define VER_IMPL 0x0000FFFF00000000
#define VER_MASK 0x00000000FF000000
#define VER_MAXTL 0x000000000000FF00
#define VER_MAXWIN 0x000000000000001F
#define VER_MAXTL_SHIFT 8
/*
* Tick Register (TICK)
*
* |---------------|
* | npt | counter |
* |-----|---------|
* 63 62 0
*
* Note: UltraSparc III Stick register has the same layout. When
* present, we clear it too.
*/
#define TICK_NPT 0x8000000000000000
#define TICK_COUNTER 0x7FFFFFFFFFFFFFFF
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PRIVREGS_H */