1N/A/*
1N/A * CDDL HEADER START
1N/A *
1N/A * The contents of this file are subject to the terms of the
1N/A * Common Development and Distribution License (the "License").
1N/A * You may not use this file except in compliance with the License.
1N/A *
1N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
1N/A * or http://www.opensolaris.org/os/licensing.
1N/A * See the License for the specific language governing permissions
1N/A * and limitations under the License.
1N/A *
1N/A * When distributing Covered Code, include this CDDL HEADER in each
1N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1N/A * If applicable, add the following below this CDDL HEADER, with the
1N/A * fields enclosed by brackets "[]" replaced with your own identifying
1N/A * information: Portions Copyright [yyyy] [name of copyright owner]
1N/A *
1N/A * CDDL HEADER END
1N/A */
1N/A/*
1N/A * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
1N/A * Use is subject to license terms.
1N/A */
1N/A
1N/A#ifndef _SYS_MACHLOCK_H
1N/A#define _SYS_MACHLOCK_H
1N/A
1N/A#pragma ident "%Z%%M% %I% %E% SMI"
1N/A
1N/A#ifdef __cplusplus
1N/Aextern "C" {
1N/A#endif
1N/A
1N/A#ifndef _ASM
1N/A
1N/A#include <sys/types.h>
1N/A
1N/A#ifdef _KERNEL
1N/A
1N/Aextern void lock_set(lock_t *lp);
1N/Aextern int lock_try(lock_t *lp);
1N/Aextern int lock_spin_try(lock_t *lp);
1N/Aextern int ulock_try(lock_t *lp);
1N/Aextern void ulock_clear(lock_t *lp);
1N/Aextern void lock_clear(lock_t *lp);
1N/Aextern void lock_set_spl(lock_t *lp, int new_pil, ushort_t *old_pil);
1N/Aextern void lock_clear_splx(lock_t *lp, int s);
1N/A
1N/A#endif /* _KERNEL */
1N/A
1N/A#define LOCK_HELD_VALUE 0xff
1N/A#define LOCK_INIT_CLEAR(lp) (*(lp) = 0)
1N/A#define LOCK_INIT_HELD(lp) (*(lp) = LOCK_HELD_VALUE)
1N/A#define LOCK_HELD(lp) (*(volatile lock_t *)(lp) != 0)
1N/A
1N/Atypedef lock_t disp_lock_t; /* dispatcher lock type */
1N/A
1N/A/*
1N/A * SPIN_LOCK() macro indicates whether lock is implemented as a spin lock or
1N/A * an adaptive mutex, depending on what interrupt levels use it.
1N/A */
1N/A#define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
1N/A
1N/A/*
1N/A * Macro to control loops which spin on a lock and then check state
1N/A * periodically. Its passed an integer, and returns a boolean value
1N/A * that if true indicates its a good time to get the scheduler lock and
1N/A * check the state of the current owner of the lock.
1N/A */
1N/A#define LOCK_SAMPLE_INTERVAL(i) (((i) & 0xff) == 0)
1N/A
1N/A/*
1N/A * Extern for CLOCK_LOCK.
1N/A */
1N/Aextern volatile int hres_lock;
1N/A
1N/A#endif /* _ASM */
1N/A
1N/A/*
1N/A * The definitions of the symbolic interrupt levels:
1N/A *
1N/A * CLOCK_LEVEL => The level at which one must be to block the clock.
1N/A *
1N/A * LOCK_LEVEL => The highest level at which one may block (and thus the
1N/A * highest level at which one may acquire adaptive locks)
1N/A * Also the highest level at which one may be preempted.
1N/A *
1N/A * DISP_LEVEL => The level at which one must be to perform dispatcher
1N/A * operations.
1N/A *
1N/A * The constraints on the platform:
1N/A *
1N/A * - CLOCK_LEVEL must be less than or equal to LOCK_LEVEL
1N/A * - LOCK_LEVEL must be less than DISP_LEVEL
1N/A * - DISP_LEVEL should be as close to LOCK_LEVEL as possible
1N/A *
1N/A * Note that LOCK_LEVEL and CLOCK_LEVEL have historically always been equal;
1N/A * changing this relationship is probably possible but not advised.
1N/A *
1N/A */
1N/A#define CLOCK_LEVEL 10
1N/A#define LOCK_LEVEL 10
1N/A#define DISP_LEVEL (LOCK_LEVEL + 1)
1N/A
1N/A#define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL)
1N/A
1N/A#define PIL_MAX 15
1N/A
1N/A/*
1N/A * The mutex and semaphore code depends on being able to represent a lock
1N/A * plus owner in a single 32-bit word. Thus the owner must contain at most
1N/A * 24 significant bits. At present only threads, mutexes and semaphores
1N/A * must be aware of this vile constraint. Different ISAs may handle this
1N/A * differently depending on their capabilities (e.g. compare-and-swap)
1N/A * and limitations (e.g. constraints on alignment and/or KERNELBASE).
1N/A */
1N/A#define PTR24_LSB 5 /* lower bits all zero */
1N/A#define PTR24_MSB (PTR24_LSB + 24) /* upper bits all one */
1N/A#define PTR24_ALIGN 32 /* minimum alignment (1 << lsb) */
1N/A#define PTR24_BASE 0xe0000000 /* minimum ptr value (-1 >> (32-msb)) */
1N/A
1N/A#ifdef __cplusplus
1N/A}
1N/A#endif
1N/A
1N/A#endif /* _SYS_MACHLOCK_H */
1N/A