pcieb_sparc.c revision 837c1ac4e72b7d86278cca88b1075af557f7d161
2d08521bd15501c8370ba2153b9cca4f094979d0Garrett D'Amore * CDDL HEADER START
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * The contents of this file are subject to the terms of the
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * Common Development and Distribution License (the "License").
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * You may not use this file except in compliance with the License.
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * or http://www.opensolaris.org/os/licensing.
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * See the License for the specific language governing permissions
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * and limitations under the License.
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * If applicable, add the following below this CDDL HEADER, with the
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * fields enclosed by brackets "[]" replaced with your own identifying
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * information: Portions Copyright [yyyy] [name of copyright owner]
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * CDDL HEADER END
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * Use is subject to license terms.
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore/* SPARC specific code used by the pcieb driver */
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore/*LINTLIBRARY*/
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore/* PLX specific functions */
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amorestatic void plx_ro_disable(pcieb_devstate_t *pcieb);
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amorestatic void pcieb_print_plx_seeprom_crc_data(pcieb_devstate_t *pcieb_p);
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore#endif /* PRINT_PLX_SEEPROM_CRC */
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore#endif /* PX_PLX */
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amorepcieb_plat_peekpoke(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop,
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore return (ddi_ctlops(dip, rdip, ctlop, arg, result));
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amorepcieb_set_prot_scan(dev_info_t *dip, ddi_acc_impl_t *hdlp)
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amorepcieb_plat_attach_workaround(dev_info_t *dip)
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amorepcieb_plat_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore if ((intr_op == DDI_INTROP_SUPPORTED_TYPES) ||
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * If the interrupt-map property is defined at this
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * node, it will have performed the interrupt
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * translation as part of the property, so no
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * rotation needs to be done.
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * Use the devices reg property to determine its
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * PCI bus number and device number.
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS,
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore "reg", (caddr_t)&pci_rp, ®len) != DDI_SUCCESS)
eda71b4a8fb1d0b34d0f08c47b43af49428d24c3Garrett D'Amore d = (pcie_ari_is_enabled(dip) == PCIE_ARI_FORW_ENABLED) ? 0 :
bc09504ff1ed70f84c9713b732281f14a9ef49b2Gordon Ross /* spin the interrupt */
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore if ((intr >= PCI_INTA) && (intr <= PCI_INTD))
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1);
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore cmn_err(CE_WARN, "%s%d: %s: PCI intr=%x out of range",
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore /* Pass up the request to our parent. */
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore return (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result));
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amorepcieb_plat_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle)
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore if ((PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_HOTPLUG, &cap_ptr)) !=
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * Disable PM on PLX. For PLX Transitioning one port on this switch to
2d08521bd15501c8370ba2153b9cca4f094979d0Garrett D'Amore * low power causes links on other ports on the same station to die.
2d08521bd15501c8370ba2153b9cca4f094979d0Garrett D'Amore * Due to PLX erratum #34, we can't allow the downstream device go to
4297a3b0d0a35d80f86fff155e288e885a100e6dGarrett D'Amore * non-D0 state.
return (B_TRUE);
return (DDI_SUCCESS);
#ifdef PX_PLX
int ce_mask = 0;
#ifdef PRINT_PLX_SEEPROM_CRC
return (DDI_SUCCESS);
if (!pxb_tlp_count) {
goto done;
goto done;
done:
return (result);
char *offset;
char *port_offset;
if (val != 0)
goto fail;
goto fix;
goto update;
goto fail;
goto fail;
fix:
goto fail;
goto done;
goto port12;
goto done;
goto done;
done:
fail:
#ifdef PRINT_PLX_SEEPROM_CRC
int nregs;
#ifdef PLX_HOT_RESET_DISABLE
ddi_regs_map_free(&h);