hat_sfmmu.h revision d3d50737e566cade9a08d73d2af95105ac7cd960
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
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*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* VM - Hardware Address Translation management.
*
* This file describes the contents of the sun-reference-mmu(sfmmu)-
* specific hat data structures and the sfmmu-specific hat procedures.
*/
#ifndef _VM_HAT_SFMMU_H
#define _VM_HAT_SFMMU_H
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASM
#endif /* _ASM */
#ifdef _KERNEL
#include <vm/mach_sfmmu.h>
/*
* Don't alter these without considering changes to ism_map_t.
*/
#define DEFAULT_ISM_PAGESIZE MMU_PAGESIZE4M
#define DEFAULT_ISM_PAGESZC TTE4M
#ifndef _ASM
#include <sys/machparam.h>
/*
* SFMMU attributes for hat_memload/hat_devload
*/
/*
* sfmmu flags for hat_memload/hat_devload
*/
/*
* sfmmu internal flag to hat_pageunload that spares locked mappings
*/
#define SFMMU_KERNEL_RELOC 0x8000
/*
* mode for sfmmu_chgattr
*/
#define SFMMU_SETATTR 0x0
#define SFMMU_CLRATTR 0x1
#define SFMMU_CHGATTR 0x2
/*
* sfmmu specific flags for page_t
*/
#ifdef VAC
#endif
#ifdef VAC
#endif
#ifdef VAC
#endif
/*
* All shared memory segments attached with the SHM_SHARE_MMU flag (ISM)
* will be constrained to a 4M, 32M or 256M alignment. Also since every newly-
* created ISM segment is created out of a new address space at base va
* of 0 we don't need to store it.
*/
/*
* Pad locks out to cache sub-block boundaries to prevent
* false sharing, so several processes don't contend for
* the same line if they aren't using the same lock. Since
* this is a typedef we also have a bit of freedom in
* changing lock implementations later if we decide it
* is necessary.
*/
typedef struct hat_lock {
} hatlock_t;
/*
* All segments mapped with ISM are guaranteed to be 4M, 32M or 256M aligned.
* Also size is guaranteed to be in 4M, 32M or 256M chunks.
* ism_seg consists of the following members:
* [XX..22] base address of ism segment. XX is 63 or 31 depending whether
* caddr_t is 64 bits or 32 bits.
* [21..0] size of segment.
*
* NOTE: Don't alter this structure without changing defines above and
* the tsb_miss and protection handlers.
*/
typedef struct ism_map {
} ism_map_t;
/*
* ISM mapping entry. Used to link all hat's sharing a ism_hat.
* Same function as the p_mapping list for a page.
*/
typedef struct ism_ment {
} ism_ment_t;
/*
* ISM segment block. One will be hung off the sfmmu structure if a
* a process uses ISM. More will be linked using ismblk_next if more
* than ISM_MAP_SLOTS segments are attached to this proc.
*
* All modifications to fields in this structure will be protected
* by the hat mutex. In order to avoid grabbing this lock in low level
* routines (tsb miss/protection handlers and vatopfn) while not
* introducing any race conditions with hat_unshare, we will set
* CTX_ISM_BUSY bit in the ctx struct. Any mmu traps that occur
* for this ctx while this bit is set will be handled in sfmmu_tsb_excption
* where it will synchronize behind the hat mutex.
*/
typedef struct ism_blk {
} ism_blk_t;
/*
* TSB access information. All fields are protected by the process's
* hat lock.
*/
struct tsb_info {
};
/*
* Values for "tsb_ttesz_mask" bitmask.
*/
/*
* Values for "tsb_flags" field.
*/
#define TSB_RELOC_FLAG 0x1
#define TSB_FLUSH_NEEDED 0x2
#define TSB_SWAPPED 0x4
#define TSB_SHAREDCTX 0x8
#endif /* !_ASM */
/*
* Data structures for shared hmeblk support.
*/
/*
* the impact on ism_map_t, TSB miss area, hblk tag and region id type in
* sf_region structure.
* Initially, shared hmes will only be used for the main text segment
* therefore this value will be set to 64, it will be increased when shared
* libraries are included.
*/
#define SFMMU_MAX_HME_REGIONS (64)
#define SFMMU_PRIVATE 0
#define SFMMU_SHARED 1
#define HMEBLK_ENDPA 1
#ifndef _ASM
#define SFMMU_MAX_ISM_REGIONS (64)
#define SFMMU_MAX_REGION_BUCKETS (128)
#define SFMMU_MAX_SRD_BUCKETS (2048)
typedef struct sf_hmeregion_map {
typedef struct sf_ismregion_map {
typedef union sf_region_map_u {
struct _h_rmap_s {
} h_rmap_s;
#define SF_RGNMAP_ZERO(map) { \
int _i; \
} \
}
/*
* Returns 1 if map1 and map2 are equal.
*/
int _i; \
break; \
} \
if (_i < SFMMU_RGNMAP_WORDS) \
rval = 0; \
else \
rval = 1; \
}
/*
* Tests whether map2 is a subset of map1, returns 1 if
* this assertion is true.
*/
int _i; \
break; \
} \
} \
if (_i < SFMMU_RGNMAP_WORDS) \
rval = 0; \
else \
rval = 1; \
}
#define SF_SCD_INCR_REF(scdp) { \
}
if (!atomic_add_32_nv( \
} \
}
/*
* A sfmmup link in the link list of sfmmups that share the same region.
*/
typedef struct sf_rgn_link {
/*
* rgn_flags values.
*/
#define SFMMU_REGION_HME 0x1
#define SFMMU_REGION_ISM 0x2
#define SFMMU_REGION_FREE 0x8
#define SFMMU_REGION_TYPE_MASK (0x3)
/*
* sf_region defines a text or (D)ISM segment which map
* the same underlying physical object.
*/
typedef struct sf_region {
void *rgn_obj; /* the underlying object id */
int rgn_refcnt; /* # of hats sharing the region */
/* callback function for hat_unload_callback */
/* A link list of processes attached to this region */
} sf_region_t;
/* srd */
typedef struct sf_shared_region_domain {
/* hme region table */
/* ism region table */
/* hash chain linking srds */
struct sf_shared_region_domain *srd_hash;
/* pointer to the next free hme region */
/* pointer to the next free ism region */
/* id of next ism region created */
/* id of next hme region created */
int srd_refcnt; /* # of procs in the srd */
/* hash of regions associated with the same executable */
} sf_srd_t;
typedef struct sf_srd_bucket {
/*
* The value of SFMMU_L1_HMERLINKS and SFMMU_L2_HMERLINKS will be increased
* to 16 when the use of shared hmes for shared libraries is enabled.
*/
#define SFMMU_L1_HMERLINKS (8)
#define SFMMU_L2_HMERLINKS (8)
#define SFMMU_L1_HMERLINKS_SHIFT (3)
#define SFMMU_L1_HMERLINKS_SIZE \
(SFMMU_L1_HMERLINKS * sizeof (sf_rgn_link_t *))
#define SFMMU_L2_HMERLINKS_SIZE \
(SFMMU_L2_HMERLINKS * sizeof (sf_rgn_link_t))
#endif
/*
* This macro grabs hat lock and allocates level 2 hat chain
* associated with a shme rgn. In the majority of cases, the macro
* is called with alloc = 0, and lock = 0.
* A pointer to the level 2 sf_rgn_link_t structure is returned in the lnkp
* parameter.
*/
{ \
} else { \
} \
} else if (alloc) { \
} \
}
/*
* Per cpu pending freelist of hmeblks.
*/
typedef struct cpu_hme_pend {
/*
* The default value of the threshold for the per cpu pending queues of hmeblks.
* The queues are flushed if either the number of hmeblks on the queue is above
* the threshold, or one second has elapsed since the last flush.
*/
#define CPU_HME_PEND_THRESH 1000
/*
* Per-MMU context domain kstats.
*
* TSB Miss Exceptions
* Number of times a TSB miss exception is handled in an MMU. See
* sfmmu_tsbmiss_exception() for more details.
* TSB Raise Exception
* Number of times the CPUs within an MMU are cross-called
* to invalidate either a specific process context (when the process
* switches MMU contexts) or the context of any process that is
* running on those CPUs (as part of the MMU context wrap-around).
* Wrap Around
* The number of times a wrap-around of MMU context happens.
*/
typedef enum mmu_ctx_stat_types {
MMU_CTX_TSB_EXCEPTIONS, /* TSB miss exceptions handled */
MMU_CTX_TSB_RAISE_EXCEPTION, /* ctx invalidation cross calls */
MMU_CTX_WRAP_AROUND, /* wraparounds */
/*
* Per-MMU context domain structure. This is instantiated the first time a CPU
* belonging to the MMU context domain is configured into the system, at boot
* time or at DR time.
*
* mmu_gnum
* The current generation number for the context IDs on this MMU context
* domain. It is protected by mmu_lock.
* mmu_cnum
* The current cnum to be allocated on this MMU context domain. It
* is protected via CAS.
* mmu_nctxs
* The max number of context IDs supported on every CPU in this
* MMU context domain. It is 8K except for Rock where it is 64K.
* This is needed here in case the system supports mixed type of
* processors/MMUs. It also helps to make ctx switch code access
* fewer cache lines i.e. no need to retrieve it from some global nctxs.
* mmu_lock
* The mutex spin lock used to serialize context ID wrap around
* mmu_idx
* The index for this MMU context domain structure in the global array
* mmu_ctxdoms.
* mmu_ncpus
* The actual number of CPUs that have been configured in this
* MMU context domain. This also acts as a reference count for the
* structure. When the last CPU in an MMU context domain is unconfigured,
* the structure is freed. It is protected by mmu_lock.
* mmu_cpuset
* The CPU set of configured CPUs for this MMU context domain. Used
* to cross-call all the CPUs in the MMU context domain to invalidate
* context IDs during a wraparound operation. It is protected by mmu_lock.
*/
typedef struct mmu_ctx {
} mmu_ctx_t;
#define mmu_tsb_exceptions \
#define mmu_tsb_raise_exception \
#define mmu_wrap_around \
extern uint_t max_mmu_ctxdoms;
extern mmu_ctx_t **mmu_ctxs_tbl;
extern void sfmmu_cpu_init(cpu_t *);
extern void sfmmu_cpu_cleanup(cpu_t *);
/*
* The following structure is used to get MMU context domain information for
* a CPU from the platform.
*
* mmu_idx
* The MMU context domain index within the global array mmu_ctxs
* mmu_nctxs
* The number of context IDs supported in the MMU context domain
* (64K for Rock)
*/
typedef struct mmu_ctx_info {
#pragma weak plat_cpuid_to_mmu_ctx_info
/*
* Each address space has an array of sfmmu_ctx_t structures, one structure
* per MMU context domain.
*
* cnum
* The context ID allocated for an address space on an MMU context domain
* gnum
* The generation number for the context ID in the MMU context domain.
*
* This structure needs to be a power-of-two in size.
*/
typedef struct sfmmu_ctx {
} sfmmu_ctx_t;
/*
* The platform dependent hat structure.
* tte counts should be protected by cas.
* cpuset is protected by cas.
*
* ttecnt accounting for mappings which do not use shared hme is carried out
* during pagefault handling. In the shared hme case, only the first process
* to access a mapping generates a pagefault, subsequent processes simply
* find the shared hme entry during trap handling and therefore there is no
* corresponding event to initiate ttecnt accounting. Currently, as shared
* hmes are only used for text segments, when joining a region we assume the
* worst case and add the the number of ttes required to map the entire region
* to the ttecnt corresponding to the region pagesize. However, if the region
* has a 4M pagesize, and memory is low, the allocation of 4M pages may fail
* then 8K pages will be allocated instead and the first TSB which stores 8K
* mappings will potentially be undersized. To compensate for the potential
* underaccounting in this case we always add 1/4 of the region size to the 8K
* ttecnt.
*
* Note that sfmmu_xhat_provider MUST be the first element.
*/
struct hat {
void *sfmmu_xhat_provider; /* NULL for CPU hat */
/* per pgsz private ttecnt + shme rgns ttecnt for rgns not in SCD */
/* shme rgns ttecnt for rgns in SCD */
/* est. ism ttes that are NOT in a SCD */
/* ttecnt for isms that are in a SCD */
/* inflate tsb0 to allow for large page alloc failure in region */
union _h_un {
} h_un;
#ifdef sun4v
struct hv_tsb_block sfmmu_hvblock;
#endif
/*
* sfmmu_ctxs is a variable length array of max_mmu_ctxdoms # of
* elements. max_mmu_ctxdoms is determined at run-time.
* sfmmu_ctxs[1] is just the fist element of an array, it always
* has to be the last field to ensure that the memory allocated
* for sfmmu_ctxs is consecutive with the memory of the rest of
* the hat data structure.
*/
};
#define SF_RGNMAP_ISNULL(sfmmup) \
#define SF_HMERGNMAP_ISNULL(sfmmup) \
struct sf_scd {
/* per pgsz ttecnt for shme rgns in SCD */
/*
* Link used to add an scd to the sfmmu_iment list.
*/
};
extern int disable_shctx;
extern int shctx_on;
/*
* bit mask for managing vac conflicts on large pages.
* bit 1 is for uncache flag.
* bits 2 through min(num of cache colors + 1,31) are
* for cache colors that have already been flushed.
*/
#ifdef VAC
#else
#define CACHE_NUM_COLOR 1
#endif
/*
* Flags passed to sfmmu_page_cache to flush page from vac or not.
*/
#define CACHE_FLUSH 0
#define CACHE_NO_FLUSH 1
/*
* Flags passed to sfmmu_tlbcache_demap
*/
#define FLUSH_NECESSARY_CPUS 0
#define FLUSH_ALL_CPUS 1
#ifdef DEBUG
/*
* For debugging purpose only. Maybe removed later.
*/
struct ctx_trace {
};
#define CTX_TRC_STEAL 0x1
#define CTX_TRC_FREE 0x0
#define TRSIZE 0x400
mutex_enter(mutex); \
num_ctx_stolen += (type); \
#else
#endif /* DEBUG */
#endif /* !_ASM */
/*
* Macros for sfmmup->sfmmu_flags access. The macros that change the flags
* ASSERT() that we're holding the HAT lock before changing the flags;
* however callers that read the flags may do so without acquiring the lock
* in a fast path, and then recheck the flag after acquiring the lock in
* a slow path.
*/
(flags))
/*
* sfmmu tte HAT flags, must fit in 8 bits
*/
#define HAT_CHKCTX1_FLAG 0x1
/*
* sfmmu HAT flags, 16 bits at the moment.
*/
#define HAT_4MTEXT_FLAG 0x01
#define HAT_32M_ISM 0x02
#define HAT_256M_ISM 0x04
#define SFMMU_LGPGS_INUSE(sfmmup) \
/*
* Starting with context 0, the first NUM_LOCKED_CTXS contexts
* are locked so that sfmmu_getctx can't steal any of these
* contexts. At the time this software was being developed, the
* only context that needs to be locked is context 0 (the kernel
* context), and context 1 (reserved for stolen context). So this constant
* was originally defined to be 2.
*
* For sun4v only, USER_CONTEXT_TYPE represents any user context. Many
* routines only care whether the context is kernel, invalid or user.
*/
#define NUM_LOCKED_CTXS 2
#define INVALID_CONTEXT 1
#ifdef sun4v
#define USER_CONTEXT_TYPE NUM_LOCKED_CTXS
#endif
/*
* Get the location in the 4MB base TSB of the tsbe for this fault.
* Assumes that the second TSB only contains 4M mappings.
*
* In:
* tagacc = tag access register (not clobbered)
* tsbe = 2nd TSB base register
* tmp1, tmp2 = scratch registers
* Out:
* tsbe = pointer to the tsbe in the 2nd TSB
*/
/*
* Get the location in the 3rd TSB of the tsbe for this fault.
* The 3rd TSB corresponds to the shared context, and is used
* for 8K - 512k pages.
*
* In:
* tagacc = tag access register (not clobbered)
* tsbe, tmp1, tmp2 = scratch registers
* Out:
* tsbe = pointer to the tsbe in the 3rd TSB
*/
/*
* Copy the sfmmu_region_map or scd_region_map to the tsbmiss
* shmermap or scd_shmermap, from sfmmu_load_mmustate.
*/
/* BEGIN CSTYLED */ \
label: ;\
/* END CSTYLED */
/*
* If there is no scd, then zero the tsbmiss scd_shmermap,
* from sfmmu_load_mmustate.
*/
/* BEGIN CSTYLED */ \
label: ;\
/* END CSTYLED */
/*
* Set hmemisc to 1 if the shared hme is also part of an scd.
* In:
* tsbarea = tsbmiss area (not clobbered)
* hmeblkpa = hmeblkpa + hmentoff + SFHME_TTE (not clobbered)
* hmentoff = hmentoff + SFHME_TTE = tte offset(clobbered)
* Out:
* use_shctx = 1 if shme is in scd and 0 otherwise
*/
/* BEGIN CSTYLED */ \
/* END CSTYLED */
/*
* Synthesize a TSB base register contents for a process.
*
* In:
* tsbinfo = TSB info pointer (ro)
* tsbreg, tmp1 = scratch registers
* Out:
* tsbreg = value to program into TSB base register
*/
/*
* Load TSB base register to TSBMISS area for privte contexts.
* This register contains utsb_pabase in bits 63:13, and TSB size
* code in bits 2:0.
*
* For private context
* In:
* tsbreg = value to load (ro)
* regnum = constant or register
* tmp1 = scratch register
* Out:
* Specified scratchpad register updated
*
*/
/*
* Get TSB base register from the scratchpad for private contexts
*
* In:
* regnum = constant or register
* tsbreg = scratch
* Out:
* tsbreg = tsbreg from the specified scratchpad register
*/
/*
* Load TSB base register to TSBMISS area for shared contexts.
* This register contains utsb_pabase in bits 63:13, and TSB size
* code in bits 2:0.
*
* In:
* tsbmiss = pointer to tsbmiss area
* tsbmissoffset = offset to right tsb pointer
* tsbreg = value to load (ro)
* Out:
* Specified tsbmiss area updated
*
*/
/*
* Get TSB base register from the scratchpad for
* shared contexts
*
* In:
* tsbmiss = pointer to tsbmiss area
* tsbmissoffset = offset to right tsb pointer
* tsbreg = scratch
* Out:
* tsbreg = tsbreg from the specified scratchpad register
*/
#endif /* defined(sun4v) || defined(UTSB_PHYS) */
#ifndef _ASM
/*
* Kernel page relocation stuff.
*/
struct sfmmu_callback {
int key;
int capture_cpus;
};
extern int sfmmu_max_cb_id;
extern struct sfmmu_callback *sfmmu_cb_table;
extern int hat_kpr_enabled;
struct pa_hment;
/*
* RFE: With multihat gone we gain back an int. We could use this to
* keep ref bits on a per cpu basis to eliminate xcalls.
*/
struct sf_hment {
union {
} sf_hment_un;
};
struct pa_hment {
void *pvt; /* handler's private data */
};
/*
* hmeblk_tag structure
* structure used to obtain a match on a hme_blk. Currently consists of
* the address of the sfmmu struct (or hatid), the base page address of the
* hme_blk, and the rehash count. The rehash count is actually only 2 bits
* and has the following meaning:
* 1 = 8k or 64k hash sequence.
* 2 = 512k hash sequence.
* 3 = 4M hash sequence.
* We require this count because we don't want to get a false hit on a 512K or
* 4M rehash with a base address corresponding to a 8k or 64k hmeblk.
* Note: The ordering and size of the hmeblk_tag members are implictly known
* by the tsb miss handlers written in assembly. Do not change this structure
* without checking those routines. See HTAG_SFMMUPSZ define.
*/
/*
* In private hmeblks hblk_rid field must be SFMMU_INVALID_RID.
*/
typedef union {
struct {
void *hblk_id;
} hblk_tag_un;
} hmeblk_tag;
#endif /* !_ASM */
#define HTAG_REHASH_SHIFT 10
#define HTAG_RID_MASK HTAG_MAX_RID
/* used for tagging all per sfmmu (i.e. non SRD) private hmeblks */
#define SFMMU_INVALID_SHMERID HTAG_MAX_RID
#endif
/* ISM regions */
#define SFMMU_INVALID_ISMRID 0xff
#endif
/*
* this macro must only be used for comparing tags in shared hmeblks.
*/
~HTAG_RID_MASK) | \
#define HME_REHASH(sfmmup) \
/* needs to be multiple of 2 */
#ifndef _ASM
#ifdef HBLK_TRACE
#define HBLK_LOCK 1
#define HBLK_UNLOCK 0
#define HBLK_STACK_DEPTH 6
#define HBLK_AUDIT_CACHE_SIZE 16
#define HBLK_LOCK_PATTERN 0xaaaaaaaa
#define HBLK_UNLOCK_PATTERN 0xbbbbbbbb
struct hblk_lockcnt_audit {
int flag; /* lock or unlock */
int depth;
};
#endif /* HBLK_TRACE */
/*
* Hment block structure.
* The hme_blk is the node data structure which the hash structure
* mantains. An hme_blk can have 2 different sizes depending on the
* number of hments it implicitly contains. When dealing with 64K, 512K,
* or 4M hments there is one hment per hme_blk. When dealing with
* 8k hments we allocate an hme_blk plus an additional 7 hments to
* give us a total of 8 (NHMENTS) hments that can be referenced through a
* hme_blk.
*
* The hmeblk structure contains 2 tte reference counters used to determine if
* it is ok to free up the hmeblk. Both counters have to be zero in order
* to be able to free up hmeblk. They are protected by cas.
* hblk_hmecnt is the number of hments present on pp mapping lists.
* hblk_vcnt reflects number of valid ttes in hmeblk.
*
* The hmeblk now also has per tte lock cnts. This is required because
* the counts can be high and there are not enough bits in the tte. When
* physio is fixed to not lock the translations we should be able to move
* the lock cnt back to the tte. See bug id 1198554.
*
* Note that xhat_hme_blk's layout follows this structure: hme_blk_misc
* and sf_hment are at the same offsets in both structures. Whenever
* hme_blk is changed, xhat_hme_blk may need to be updated as well.
*/
struct hme_blk_misc {
};
struct hme_blk {
/* protected by hash lock */
/* protected by hash lock */
struct hme_blk_misc hblk_misc;
union {
struct {
} hblk_counts;
} hblk_un;
#ifdef HBLK_TRACE
#endif /* HBLK_AUDIT */
};
#define MAX_HBLK_LCKCNT 0xFFFFFFFF
#ifdef HBLK_TRACE
{ \
int audit_index; \
\
(HBLK_AUDIT_CACHE_SIZE - 1)); \
\
if (flag) \
else \
\
HBLK_STACK_DEPTH); \
}
#else
#endif /* HBLK_TRACE */
/*
* A maximum number of user hmeblks is defined in order to place an upper
* limit on how much nucleus memory is required and to avoid overflowing the
* tsbmiss uhashsz and khashsz data areas. The number below corresponds to
* the number of buckets required, for an average hash chain length of 4 on
* a 16TB machine.
*/
/*
* The minimum number of kernel hash buckets.
*/
#define MIN_KHME_BUCKETS 0x800
/*
* The number of hash buckets must be a power of 2. If the initial calculated
* value is less than USER_BUCKETS_THRESHOLD we round up to the next greater
* power of 2, otherwise we round down to avoid huge over allocations.
*/
#define MAX_NUCUHME_BUCKETS 0x4000
#define MAX_NUCKHME_BUCKETS 0x2000
/*
* There are 2 locks in the hmehash bucket. The hmehash_mutex is
* a regular mutex used to make sure operations on a hash link are only
* done by one thread. Any operation which comes into the hat with
* a <vaddr, as> will grab the hmehash_mutex. Normally one would expect
* the tsb miss handlers to grab the hash lock to make sure the hash list
* is consistent while we traverse it. Unfortunately this can lead to
* deadlocks or recursive mutex enters since it is possible for
* To solve this problem we have added the hmehash_listlock. This lock
* is only grabbed by the tsb miss handlers, vatopfn, and while
* guarantee we won't take a tlb miss while holding this lock.
*/
struct hmehash_bucket {
};
#endif /* !_ASM */
#define SFMMU_PGCNT_MASK 0x3f
#define SFMMU_PGCNT_SHIFT 6
#define INVALID_MMU_ID -1
#define SFMMU_MMU_GNUM_RSHIFT 16
/*
* The tsb miss handlers written in assembly know that sfmmup
* is a 64 bit ptr.
*
* The bspage and re-hash part is 64 bits, with the sfmmup being another 64
* bits.
*/
#define HTAG_SFMMUPSZ 0 /* Not really used for LP64 */
#define HTAG_BSPAGE_SHIFT 13
/*
* Assembly routines need to be able to get to ttesz
*/
#define HBLK_SZMASK 0x7
#ifndef _ASM
/*
* Returns the number of bytes that an hmeblk spans given its tte size
*/
#define HMEBLK_SPAN(ttesz) \
#define get_hblk_base(hmeblkp) \
#define get_hblk_endaddr(hmeblkp) \
get_hblk_span(hmeblkp))))
#define HME8BLK_SZ (sizeof (struct hme_blk) + \
#define HME1BLK_SZ (sizeof (struct hme_blk))
/*
* Hme_blk hash structure
* Active mappings are kept in a hash structure of hme_blks. The hash
* function is based on (ctx, vaddr) The size of the hash table size is a
* power of 2 such that the average hash chain lenth is HMENT_HASHAVELEN.
* The hash actually consists of 2 separate hashes. One hash is for the user
* address space and the other hash is for the kernel address space.
* The number of buckets are calculated at boot time and stored in the global
* variables "uhmehash_num" and "khmehash_num". By making the hash table size
* a power of 2 we can use a simply & function to derive an index instead of
* a divide.
*
* HME_HASH_FUNCTION(hatid, vaddr, shift) returns a pointer to a hme_hash
* bucket.
* An hme hash bucket contains a pointer to an hme_blk and the mutex that
* protects the link list.
* Spitfire supports 4 page sizes. 8k and 64K pages only need one hash.
* 512K pages need 2 hashes and 4M pages need 3 hashes.
* The 'shift' parameter controls how many bits the vaddr will be shifted in
* the hash function. It is calculated in the HME_HASH_SHIFT(ttesz) function
* and it varies depending on the page size as follows:
* 8k pages: HBLK_RANGE_SHIFT
* 64k pages: MMU_PAGESHIFT64K
* 512K pages: MMU_PAGESHIFT512K
* 4M pages: MMU_PAGESHIFT4M
* An assembly version of the hash function exists in sfmmu_ktsb_miss(). All
* changes should be reflected in both versions. This function and the TSB
* miss handlers are the only places which know about the two hashes.
*
* HBLK_RANGE_SHIFT controls range of virtual addresses that will fall
* into the same bucket for a particular process. It is currently set to
* be equivalent to 64K range or one hme_blk.
*
* The hme_blks in the hash are protected by a per hash bucket mutex
* known as SFMMU_HASH_LOCK.
* You need to acquire this lock before traversing the hash bucket link
* modifying an hme_blk. A possible optimization is to replace these
* this is a win or not.
*
* The HME_HASH_TABLE_SEARCH will search the hash table for the
* hme_blk that contains the hment that corresponds to the passed
* ctx and vaddr. It assumed the SFMMU_HASH_LOCK is held.
*/
#endif /* ! _ASM */
#define UHMEHASH_SZ uhmehash_num
#define KHMEHASH_SZ khmehash_num
#define HMENT_HASHAVELEN 4
#define HBLK_MIN_TTESZ 1
#define HBLK_MIN_BYTES MMU_PAGESIZE64K
#define HBLK_MIN_SHIFT MMU_PAGESHIFT64K
#define MAX_HASHCNT 5
#define DEFAULT_MAX_HASHCNT 3
#ifndef _ASM
#define HME_HASH_SHIFT(ttesz) \
#define HME_HASH_REHASH(ttesz) \
UHMEHASH_SZ) ]): \
KHMEHASH_SZ) ]))
/*
* This macro will traverse a hmeblk hash link list looking for an hme_blk
* that owns the specified vaddr and hatid. If if doesn't find one , hmeblkp
* will be set to NULL, otherwise it will point to the correct hme_blk.
* This macro also cleans empty hblks.
*/
{ \
\
while (hblkp) { \
/* found hme_blk */ \
break; \
} \
listp, 0); \
} else { \
} \
} \
}
{ \
\
}
/*
* This macro will traverse a hmeblk hash link list looking for an hme_blk
* that owns the specified vaddr and hatid. If if doesn't find one , hmeblkp
* will be set to NULL, otherwise it will point to the correct hme_blk.
* It doesn't remove empty hblks.
*/
/* found hme_blk */ \
break; \
} \
}
#define SFMMU_HASH_LOCK(hmebp) \
#define SFMMU_HASH_UNLOCK(hmebp) \
#define SFMMU_HASH_LOCK_TRYENTER(hmebp) \
#define SFMMU_HASH_LOCK_ISHELD(hmebp) \
#define SFMMU_XCALL_STATS(sfmmup) \
{ \
} else { \
} \
}
(void *)((sfmmup)->sfmmu_srdp))
/*
* We use the sfmmu data structure to keep the per as page coloring info.
*/
typedef struct {
char h8[HME8BLK_SZ];
} hblk8_t;
typedef struct {
char h1[HME1BLK_SZ];
} hblk1_t;
typedef struct {
typedef struct {
/*
* This struct is used for accumlating information about a range
* of pages that are unloading so that a single xcall can flush
* the entire range from remote tlbs. A function that must demap
* a range of virtual addresses declares one of these structures
* and initializes using DEMP_RANGE_INIT(). It then passes a pointer to this
* struct to the appropriate sfmmu_hblk_* level function which does
* all the bookkeeping using the other macros. When the function has
* finished the virtual address range, it needs to call DEMAP_RANGE_FLUSH()
* macro to take care of any remaining unflushed mappings.
*
* The maximum range this struct can represent is the number of bits
* in the dmr_bitvec field times the pagesize in dmr_pgsz. Currently, only
* MMU_PAGESIZE pages are supported.
*
* Since there are now cases where it's no longer necessary to do
* flushes (e.g. when the process isn't runnable because it's swapping
* out or exiting) we allow these macros to take a NULL dmr input and do
* nothing in that case.
*/
typedef struct {
(dmrp)->dmr_bitvec = 0; \
}
}
#define DEMAP_RANGE_FLUSH(dmrp) \
if ((dmrp)->dmr_bitvec != 0) \
}
if ((dmrp)->dmr_bitvec == 0) { \
} \
}
#define DEMAP_RANGE_NEXTPG(dmrp) \
} else { \
} \
}
/*
* TSB related structures
*
* The TSB is made up of tte entries. Both the tag and data are present
* in the TSB. The TSB locking is managed as follows:
* A software bit in the tsb tag is used to indicate that entry is locked.
* If a cpu servicing a tsb miss reads a locked entry the tag compare will
* fail forcing the cpu to go to the hat hash for the translation.
* The cpu who holds the lock can then modify the data side, and the tag side.
* The last write should be to the word containing the lock bit which will
* clear the lock and allow the tsb entry to be read. It is assumed that all
* cpus reading the tsb will do so with atomic 128-bit loads. An atomic 128
* bit load is required to prevent the following from happening:
*
* cpu 0 cpu 1 comments
*
* ldx tag tag unlocked
* ldstub lock set lock
* stx data
* stx tag unlock
* ldx tag incorrect tte!!!
*
* The software also maintains a bit in the tag to indicate an invalid
* tsb entry. The purpose of this bit is to allow the tsb invalidate code
* to invalidate a tsb entry with a single cas. See code for details.
*/
union tsb_tag {
struct {
} tagbits;
struct tsb_tagints {
} tagints;
};
struct tsbe {
};
/*
* A per cpu struct is kept that duplicates some info
* used by the tl>0 tsb miss handlers plus it provides
* a scratch area. Its purpose is to minimize cache misses
* in the tsb miss handler and is 128 bytes (2 e$ lines).
*
* There should be one allocated per cpu in nucleus memory
* and should be aligned on an ecache line boundary.
*/
struct tsbmiss {
struct hmehash_bucket *khashstart;
struct hmehash_bucket *uhashstart;
/*
* scratch[0] -> TSB_TAGACC
* scratch[1] -> TSBMISS_HMEBP
* scratch[2] -> TSBMISS_HATID
*/
};
/*
* A per cpu struct is kept for the use within the tl>0 kpm tsb
* miss handler. Some members are duplicates of common data or
* the physical addresses of common data. A few members are also
* written by the tl>0 kpm tsb miss handler. Its purpose is to
* minimize cache misses in the kpm tsb miss handler and occupies
* one ecache line. There should be one allocated per cpu in
* nucleus memory and it should be aligned on an ecache line
* boundary. It is not merged w/ struct tsbmiss since there is
* not much to share and the tsbmiss pathes are different, so
* (DEBUG || SFMMU_STAT_GATHER) where the dtlb_misses counter
* of struct tsbmiss is used on every dtlb miss.
*/
struct kpmtsbm {
};
extern size_t tsb_slab_size;
extern uint_t tsb_slab_shift;
extern size_t tsb_slab_mask;
#endif /* !_ASM */
/*
* Flags for TL kpm tsbmiss handler
*/
/*
* The TSB
* All TSB sizes supported by the hardware are now supported (8K - 1M).
* For kernel TSBs we may go beyond the hardware supported sizes and support
* larger TSBs via software.
* All TTE sizes are supported in the TSB; the manner in which this is
* done is cpu dependent.
*/
#ifdef sun4v
#else /* sun4u */
#endif /* sun4v */
#define TSB_8K_SZCODE 0 /* 512 entries */
#define TSB_START_SIZE 9
/*
* sun4u platforms
* ---------------
* We now support two user TSBs with one TSB base register.
* Hence the TSB base register is split up as follows:
*
* When only one TSB present:
* [63 62..42 41..13 12..4 3..0]
* ^ ^ ^ ^ ^
* | | | | |
* | | | | |_ TSB size code
* | | | |
* | | | |_ Reserved 0
* | | |
* | | |_ TSB VA[41..13]
* | |
* | |_ VA hole (Spitfire), zeros (Cheetah and beyond)
* |
* |_ 0
*
* When second TSB present:
* [63 62..42 41..33 32..29 28..22 21..13 12..4 3..0]
* ^ ^ ^ ^ ^ ^ ^ ^
* | | | | | | | |
* | | | | | | | |_ First TSB size code
* | | | | | | |
* | | | | | | |_ Reserved 0
* | | | | | |
* | | | | | |_ First TSB's VA[21..13]
* | | | | |
* | | | | |_ Reserved for future use
* | | | |
* | | | |_ Second TSB's size code
* | | |
* | | |_ Second TSB's VA[21..13]
* | |
* | |_ VA hole (Spitfire) / ones (Cheetah and beyond)
* |
* |_ 1
*
* Note that since we store 21..13 of each TSB's VA, TSBs and their slabs
* may be up to 4M in size. For now, only hardware supported TSB sizes
* are supported, though the slabs are usually 4M in size.
*
* sun4u platforms that define UTSB_PHYS use physical addressing to access
* the user TSBs at TL>0. The first user TSB base is in the MMU I/D TSB Base
* registers. The second TSB base uses a dedicated scratchpad register which
* requires a definition of SCRATCHPAD_UTSBREG2 in mach_sfmmu.h. The layout for
* both registers is equivalent to sun4v below, except the TSB PA range is
* [46..13] for sun4u.
*
* sun4v platforms
* ---------------
* On sun4v platforms, we use two dedicated scratchpad registers as pseudo
* hardware TSB base registers to hold up to two different user TSBs.
*
* Each register contains TSB's physical base and size code information
* as follows:
*
* [63..56 55..13 12..4 3..0]
* ^ ^ ^ ^
* | | | |
* | | | |_ TSB size code
* | | |
* | | |_ Reserved 0
* | |
* | |_ TSB PA[55..13]
* |
* |
* |
* |_ 0 for valid TSB
*
* Absence of a user TSB (primarily the second user TSB) is indicated by
* storing a negative value in the TSB base register. This allows us to
* check for presence of a user TSB by simply checking bit# 63.
*/
/* sectsb va -> bits 21:13 */
/* after clearing upper bits */
#define BIGKTSB_SZ_MASK 0xf
#define TSB_SOFTSZ_MASK BIGKTSB_SZ_MASK
/*
* sw bits used on tsb_tag - bit masks used only in assembly
* use only a sethi for these fields.
*/
#ifdef _ASM
/*
* Marker to indicate that this instruction will be hot patched at runtime
* to some other value.
* This value must be zero since it fills in the imm bits of the target
* instructions to be patched
*/
#define RUNTIME_PATCH (0)
/*
* V9 defines nop instruction as the following, which we use
* at runtime to nullify some instructions we don't want to
* execute in the trap handlers on certain platforms.
*/
#define MAKE_NOP_INSTR(reg) \
/*
* This macro constructs a SPARC V9 "jmpl <source reg>, %g0"
* instruction, with the source register specified by the jump_reg_number.
* The jmp opcode [24:19] = 11 1000 and source register is bits [18:14].
* The instruction is returned in reg. The macro is used to patch in a jmpl
* instruction at runtime.
*/
/*
* Macro to get hat per-MMU cnum on this CPU.
* sfmmu - In, pass in "sfmmup" from the caller.
* cnum - Out, return 'cnum' to the caller
* scr - scratch
*/
/*
* Macro to get hat gnum & cnum assocaited with sfmmu_ctx[mmuid] entry
* entry - In, pass in (&sfmmu_ctxs[mmuid] - SFMMU_CTXS) from the caller.
* gnum - Out, return sfmmu gnum
* cnum - Out, return sfmmu cnum
* reg - scratch
*/
/*
* Macro to get this CPU's tsbmiss area.
*/
/*
* Macro to set kernel context + page size codes in DMMU primary context
* register. It is only necessary for sun4u because sun4v does not need
* page size codes
*/
#ifdef sun4v
#else
/*CSTYLED*/ \
/*CSTYLED*/ \
label1:; \
/*CSTYLED*/ \
label2:; \
/*CSTYLED*/ \
label3:;
#endif
/*
* Macro to setup arguments with kernel sfmmup context + page size before
* calling sfmmu_setctx_sec()
*/
#ifdef sun4v
#else
#endif
/*CSTYLED*/ \
nop; \
\
/*CSTYLED*/ \
nop; \
\
/*CSTYLED*/ \
/* \
* The caller must have disabled interrupts. \
* If interrupts are not disabled, panic \
*/ \
/*CSTYLED*/ \
nop; \
\
/*CSTYLED*/ \
nop; \
\
/*CSTYLED*/ \
#endif /* _ASM */
#ifndef _ASM
#ifdef VAC
/*
* Page coloring
* The p_vcolor field of the page struct (1 byte) is used to store the
* virtual page color. This provides for 255 colors. The value zero is
* used to mean the page has no color - never been mapped or somehow
* purified.
*/
/*
* As mentioned p_vcolor == 0 means there is no color for this page.
* But PP_SET_VCOLOR(pp, color) expects 'color' to be real color minus
* one so we define this constant.
*/
#define NO_VCOLOR (-1)
#define addr_to_vcolor(addr) \
#else /* VAC */
#define addr_to_vcolor(addr) (0)
#endif /* VAC */
/*
* The field p_index in the psm page structure is for large pages support.
* P_index is a bit-vector of the different mapping sizes that a given page
* is part of. An hme structure for a large mapping is only added in the
* group leader page (first page). All pages covered by a given large mapping
* have the corrosponding mapping bit set in their p_index field. This allows
* us to only store an explicit hme structure in the leading page which
* simplifies the mapping link list management. Furthermore, it provides us
* a fast mechanism for determining the largest mapping a page is part of. For
* exmaple, a page with a 64K and a 4M mappings has a p_index value of 0x0A.
*
* Implementation note: even though the first bit in p_index is reserved
* for 8K mappings, it is NOT USED by the code and SHOULD NOT be set.
* In addition, the upper four bits of the p_index field are used by the
* code as temporaries
*/
/*
* Defines for psm page struct fields and large page support
*/
#define SFMMU_INDEX_SHIFT 6
/* Return the mapping index */
/*
* These macros rely on the following property:
* All pages constituting a large page are covered by a virtually
* contiguous set of page_t's.
*/
/* Return the leader for this mapping size */
/* Return the root page for this page based on p_szc */
/* Need function to test the page mappping which takes p_index into account */
/*
* Don't call this macro with sz equal to zero. 8K mappings SHOULD NOT
* set p_index field.
*/
/*
* prototypes for hat assembly routines. Some of these are
* known to machine dependent VM code.
*/
extern struct tsbe *
extern void sfmmu_load_mmustate(sfmmu_t *);
#ifndef sun4v
#endif /* sun4v */
extern uint_t sfmmu_disable_intrs(void);
extern void sfmmu_enable_intrs(uint_t);
/*
* functions exported to machine dependent VM code
*/
extern void sfmmu_patch_ktsb(void);
#ifndef UTSB_PHYS
extern void sfmmu_patch_utsb(void);
#endif /* UTSB_PHYS */
#ifdef DEBUG
extern void sfmmu_check_kpfn(pfn_t);
#else
#endif /* DEBUG */
extern void sfmmu_init_tsbs(void);
extern int sfmmu_getctx_pri(void);
extern int sfmmu_getctx_sec(void);
extern void sfmmu_setctx_sec(uint_t);
extern void sfmmu_init_ktsbinfo(void);
extern int sfmmu_setup_4lp(void);
extern void sfmmu_patch_mmu_asi(int);
extern void sfmmu_cache_flushall(void);
extern void hat_kern_setup(void);
extern int sfmmu_get_ppvcolor(struct page *);
extern int sfmmu_get_addrvcolor(caddr_t);
extern int sfmmu_hat_lock_held(sfmmu_t *);
/*
* Functions exported to xhat_sfmmu.c
*/
extern void sfmmu_mlist_exit(kmutex_t *);
extern int sfmmu_mlist_held(struct page *);
/*
* MMU-specific functions optionally imported from the CPU module
*/
#pragma weak mmu_init_scd
#pragma weak mmu_large_pages_disabled
#pragma weak mmu_set_ctx_page_sizes
#pragma weak mmu_check_page_sizes
extern void mmu_init_scd(sf_scd_t *);
extern void mmu_set_ctx_page_sizes(sfmmu_t *);
extern uint64_t ktsb_pbase;
extern int ktsb_sz;
extern int ktsb_szcode;
extern caddr_t ktsb4m_base;
extern uint64_t ktsb4m_pbase;
extern int ktsb4m_sz;
extern int ktsb4m_szcode;
extern uint64_t kpm_tsbbase;
extern int kpm_tsbsz;
extern int ktsb_phys;
extern int enable_bigktsb;
#ifndef sun4v
extern int utsb_dtlb_ttenum;
extern int utsb4m_dtlb_ttenum;
#endif /* sun4v */
extern int uhmehash_num;
extern int khmehash_num;
extern struct hmehash_bucket *uhme_hash;
extern struct hmehash_bucket *khme_hash;
extern uint_t mml_table_sz;
extern uint_t hblk_alloc_dynamic;
#ifndef sun4v
extern int dtlb_resv_ttenum;
extern caddr_t utsb_vabase;
extern caddr_t utsb4m_vabase;
#endif /* sun4v */
extern vmem_t *kmem_tsb_default_arena[];
extern int tsb_lgrp_affinity;
extern uint_t disable_large_pages;
extern uint_t disable_ism_large_pages;
extern uint_t disable_auto_data_large_pages;
extern uint_t disable_auto_text_large_pages;
/* kpm externals */
extern void sfmmu_kpm_patch_tlbm(void);
extern void sfmmu_kpm_patch_tsbm(void);
extern void sfmmu_patch_shctx(void);
extern void sfmmu_kpm_unload_tsb(caddr_t, int);
extern void sfmmu_kpm_tsbmtl(short *, uint_t *, int);
extern struct memseg *memseg_hash[];
extern uint64_t memseg_phash[];
extern kpm_hlk_t *kpmp_table;
extern kpm_shlk_t *kpmp_stable;
extern uint_t kpmp_table_sz;
extern uint_t kpmp_stable_sz;
extern uchar_t kpmp_shift;
#define IS_KPM_ALIAS_RANGE(vaddr) \
#endif /* !_ASM */
/* sfmmu_kpm_tsbmtl flags */
#define KPMTSBM_STOP 0
#define KPMTSBM_START 1
/*
* For kpm_smallpages, the state about how a kpm page is mapped and whether
* it is ready to go is indicated by the two 4-bit fields defined in the
* kpm_spage structure as follows:
* kp_mapped_flag bit[0:3] - the page is mapped cacheable or not
* kp_mapped_flag bit[4:7] - the mapping is ready to go or not
* If the bit KPM_MAPPED_GO is on, it indicates that the assembly tsb miss
* handler can drop the mapping in regardless of the caching state of the
* mapping. Otherwise, we will have C handler resolve the VAC conflict no
* matter the page is currently mapped cacheable or non-cacheable.
*/
#define KPM_MAPPED_MASK 0xf
/* Physical memseg address NULL marker */
#define MSEG_NULLPTR_PA -1
/*
* Memseg hash defines for kpm trap level tsbmiss handler.
* Must be in sync w/ page.h .
*/
#define SFMMU_MEM_HASH_SHIFT 0x9
#define SFMMU_N_MEM_SLOTS 0x200
#define SFMMU_MEM_HASH_ENTRY_SHIFT 3
#ifndef _ASM
#if (SFMMU_MEM_HASH_SHIFT != MEM_HASH_SHIFT)
#endif
#if (SFMMU_N_MEM_SLOTS != N_MEM_SLOTS)
#endif
/* Physical memseg address NULL marker */
#define SFMMU_MEMSEG_NULLPTR_PA -1
/*
* Check KCONTEXT to be zero, asm parts depend on that assumption.
*/
#if (KCONTEXT != 0)
#endif
#endif /* !_ASM */
#endif /* _KERNEL */
#ifndef _ASM
/*
* ctx, hmeblk, mlistlock and other stats for sfmmu
*/
struct sfmmu_global_stat {
int sf_tsb_exceptions; /* # of tsb exceptions */
int sf_tsb_raise_exception; /* # tsb exc. w/o TLB flush */
int sf_pagefaults; /* # of pagefaults */
int sf_uhash_searches; /* # of user hash searches */
int sf_uhash_links; /* # of user hash links */
int sf_khash_searches; /* # of kernel hash searches */
int sf_khash_links; /* # of kernel hash links */
int sf_swapout; /* # times hat swapped out */
int sf_tsb_alloc; /* # TSB allocations */
int sf_tsb_allocfail; /* # times TSB alloc fail */
int sf_tsb_sectsb_create; /* # times second TSB added */
int sf_scd_1sttsb_alloc; /* # SCD 1st TSB allocations */
int sf_scd_2ndtsb_alloc; /* # SCD 2nd TSB allocations */
int sf_scd_1sttsb_allocfail; /* # SCD 1st TSB alloc fail */
int sf_scd_2ndtsb_allocfail; /* # SCD 2nd TSB alloc fail */
int sf_tteload8k; /* calls to sfmmu_tteload */
int sf_tteload64k; /* calls to sfmmu_tteload */
int sf_tteload512k; /* calls to sfmmu_tteload */
int sf_tteload4m; /* calls to sfmmu_tteload */
int sf_tteload32m; /* calls to sfmmu_tteload */
int sf_tteload256m; /* calls to sfmmu_tteload */
int sf_tsb_load8k; /* # times loaded 8K tsbent */
int sf_tsb_load4m; /* # times loaded 4M tsbent */
int sf_hblk_hit; /* found hblk during tteload */
int sf_hblk8_ncreate; /* static hblk8's created */
int sf_hblk8_nalloc; /* static hblk8's allocated */
int sf_hblk1_ncreate; /* static hblk1's created */
int sf_hblk1_nalloc; /* static hblk1's allocated */
int sf_hblk_slab_cnt; /* sfmmu8_cache slab creates */
int sf_hblk_reserve_cnt; /* hblk_reserve usage */
int sf_hblk_recurse_cnt; /* hblk_reserve owner reqs */
int sf_hblk_reserve_hit; /* hblk_reserve hash hits */
int sf_get_free_success; /* reserve list allocs */
int sf_get_free_throttle; /* fails due to throttling */
int sf_get_free_fail; /* fails due to empty list */
int sf_put_free_success; /* reserve list frees */
int sf_put_free_fail; /* fails due to full list */
int sf_pgcolor_conflict; /* VAC conflict resolution */
int sf_uncache_conflict; /* VAC conflict resolution */
int sf_unload_conflict; /* VAC unload resolution */
int sf_ism_uncache; /* VAC conflict resolution */
int sf_ism_recache; /* VAC conflict resolution */
int sf_recache; /* VAC conflict resolution */
int sf_steal_count; /* # of hblks stolen */
int sf_pagesync; /* # of pagesyncs */
int sf_clrwrt; /* # of clear write perms */
int sf_pagesync_invalid; /* pagesync with inv tte */
int sf_kernel_xcalls; /* # of kernel cross calls */
int sf_user_xcalls; /* # of user cross calls */
int sf_tsb_grow; /* # of user tsb grows */
int sf_tsb_shrink; /* # of user tsb shrinks */
int sf_tsb_resize_failures; /* # of user tsb resize */
int sf_tsb_reloc; /* # of user tsb relocations */
int sf_user_vtop; /* # of user vatopfn calls */
int sf_ctx_inv; /* #times invalidate MMU ctx */
int sf_tlb_reprog_pgsz; /* # times switch TLB pgsz */
int sf_region_remap_demap; /* # times shme remap demap */
int sf_create_scd; /* # times SCD is created */
int sf_join_scd; /* # process joined scd */
int sf_leave_scd; /* # process left scd */
int sf_destroy_scd; /* # times SCD is destroyed */
};
struct sfmmu_tsbsize_stat {
int sf_tsbsz_8k;
int sf_tsbsz_16k;
int sf_tsbsz_32k;
int sf_tsbsz_64k;
int sf_tsbsz_128k;
int sf_tsbsz_256k;
int sf_tsbsz_512k;
int sf_tsbsz_1m;
int sf_tsbsz_2m;
int sf_tsbsz_4m;
int sf_tsbsz_8m;
int sf_tsbsz_16m;
int sf_tsbsz_32m;
int sf_tsbsz_64m;
int sf_tsbsz_128m;
int sf_tsbsz_256m;
};
struct sfmmu_percpu_stat {
int sf_itlb_misses; /* # of itlb misses */
int sf_dtlb_misses; /* # of dtlb misses */
int sf_utsb_misses; /* # of user tsb misses */
int sf_ktsb_misses; /* # of kernel tsb misses */
int sf_tsb_hits; /* # of tsb hits */
int sf_umod_faults; /* # of mod (prot viol) flts */
int sf_kmod_faults; /* # of mod (prot viol) flts */
};
#endif /* !_ASM */
#ifdef __cplusplus
}
#endif
#endif /* _VM_HAT_SFMMU_H */