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20c794b39650d115e17a15983b6b82e46238cf45gavinm * Common Development and Distribution License (the "License").
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e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Use is subject to license terms.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Constants for the Memory Check Architecture as implemented on generic x86
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiextern "C" {
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Architectural MSRs from the IA-32 Software Developer's Manual - IA32_MSR_*
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCG_CAP_COUNT(cap) ((cap) & MCG_CAP_COUNT_MASK)
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((cap) & MCG_CAP_EXT_CNT_MASK) >> MCG_CAP_EXT_CNT_SHIFT)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * There are as many error detector "banks" as indicated by
20c794b39650d115e17a15983b6b82e46238cf45gavinm * IA32_MSR_MCG_CAP.COUNT. Each bank has a minimum of 3 associated
20c794b39650d115e17a15983b6b82e46238cf45gavinm * registers (MCi_CTL, MCi_STATUS, and MCi_ADDR) and some banks
20c794b39650d115e17a15983b6b82e46238cf45gavinm * may implement a fourth (MCi_MISC) which should only be read
20c794b39650d115e17a15983b6b82e46238cf45gavinm * when MCi_STATUS.MISCV indicates that it exists and has valid data.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * The first bank features at MSR offsets 0x400 to 0x403, the next at
20c794b39650d115e17a15983b6b82e46238cf45gavinm * 0x404 to 0x407, and so on. Current processors implement up to 6
20c794b39650d115e17a15983b6b82e46238cf45gavinm * banks (sixth one at 0x414 to 0x417).
20c794b39650d115e17a15983b6b82e46238cf45gavinm * It is, sadly, not the case that the i'th set of 4 registers starting
20c794b39650d115e17a15983b6b82e46238cf45gavinm * at 0x400 corresponds to MCi_{CTL,STATUS,ADDR,MISC} - for some Intel
20c794b39650d115e17a15983b6b82e46238cf45gavinm * processors, for example, the order is 0/1/2/4/3. Nonetheless, we can
20c794b39650d115e17a15983b6b82e46238cf45gavinm * still iterate through the banks and read all telemetry - there'll just
20c794b39650d115e17a15983b6b82e46238cf45gavinm * be some potential confusion as to which processor unit a bank is
20c794b39650d115e17a15983b6b82e46238cf45gavinm * associated with. Error reports should seek to disambiguate.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * IA32_MSR_MC(i, which) calculates the MSR address for th i'th bank
20c794b39650d115e17a15983b6b82e46238cf45gavinm * of registers (not for MCi_*, as above) and one of CTL, STATUS, ADDR, MISC
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define _IA32_MSR_MC0_CTL 0x400ULL /* first/base reg */
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define _IA32_MSR_OFFSET_CTL 0x0 /* offset within a bank */
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define _IA32_MSR_OFFSET_STATUS 0x1 /* offset within a bank */
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define _IA32_MSR_OFFSET_ADDR 0x2 /* offset within a bank */
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define _IA32_MSR_OFFSET_MISC 0x3 /* offset within a bank */
728f047ccdb8a96a1aecc448cb87706241a08c94Adrian Frost#define _IA32_MSR_MC0_CTL2 0x280ULL /* first MCi_CTL2 reg */
20c794b39650d115e17a15983b6b82e46238cf45gavinm (_IA32_MSR_MC0_CTL + (i) * 4 + _IA32_MSR_OFFSET_##which)
728f047ccdb8a96a1aecc448cb87706241a08c94Adrian Frost#define IA32_MSR_MC_CTL2(i) (_IA32_MSR_MC0_CTL2 + (i))
20c794b39650d115e17a15983b6b82e46238cf45gavinm * IA32_MSR_MCG_CAP.MCG_EXT_P indicates that a processor implements
20c794b39650d115e17a15983b6b82e46238cf45gavinm * a set of extended machine-check registers starting at MSR 0x180;
20c794b39650d115e17a15983b6b82e46238cf45gavinm * when that is set, IA32_MSR_MCG_CAP.MCG_EXT_CNT indicates how
20c794b39650d115e17a15983b6b82e46238cf45gavinm * many of these extended registers (addresses 0x180, 0x181, ...)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * are present. Which registers are present depends on whether support
20c794b39650d115e17a15983b6b82e46238cf45gavinm * for 64-bit architecture is present.
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define _IA32_MCG_RAX 0x180ULL /* first/base extended reg */
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Lower 32 bits of MCi_STATUS
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Upper 32 bits of MCi_STATUS
20c794b39650d115e17a15983b6b82e46238cf45gavinm * If IA32_MCG_CAP.MCG_TES_P is set then <54:53>
20c794b39650d115e17a15983b6b82e46238cf45gavinm * and <56:55> are architectural.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * If IA32_MCG_CAP.MCG_TES_P is clear then <56:53>
20c794b39650d115e17a15983b6b82e46238cf45gavinm * are model-specific.
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_errcode _mcis_hilo._mcis_lo._errcode
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_mserrcode _mcis_hilo._mcis_lo._ms_errcode
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_pcc _mcis_hilo._mcis_hi._mcis_hi_tes_np._pcc
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_addrv _mcis_hilo._mcis_hi._mcis_hi_tes_np._addrv
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_miscv _mcis_hilo._mcis_hi._mcis_hi_tes_np._miscv
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_en _mcis_hilo._mcis_hi._mcis_hi_tes_np._en
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_uc _mcis_hilo._mcis_hi._mcis_hi_tes_np._uc
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_over _mcis_hilo._mcis_hi._mcis_hi_tes_np._over
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_val _mcis_hilo._mcis_hi._mcis_hi_tes_np._val
20c794b39650d115e17a15983b6b82e46238cf45gavinm * The consumer must check for TES_P before using these.
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define mcistatus_tbes _mcis_hilo._mcis_hi._mcis_hi_tes_p._tbes
20c794b39650d115e17a15983b6b82e46238cf45gavinm#endif /* _BIT_FIELDS_LTOH */
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MSR_MC_STATUS_RESERVED_MASK 0x0180000000000000ULL
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost#define MSR_MC_STATUS_CEC_MASK 0x001fffc000000000ULL
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MSR_MC_STATUS_MCAERR_MASK 0x000000000000ffffULL
728f047ccdb8a96a1aecc448cb87706241a08c94Adrian Frost#define MSR_MC_CTL2_THRESHOLD_MASK 0x0000000000007fffULL
728f047ccdb8a96a1aecc448cb87706241a08c94Adrian Frost#define MSR_MC_CTL2_THRESHOLD_OVERFLOW 0x0000000000004000ULL
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Macros to extract error code and model-specific error code.
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCAX86_ERRCODE(stat) ((stat) & MSR_MC_STATUS_MCAERR_MASK)
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((stat) & MSR_MC_STATUS_MSERR_MASK) >> MSR_MC_STATUS_MSERR_SHIFT)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Macro to extract threshold based error state (if MCG_CAP.TES_P)
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((stat) & MSR_MC_STATUS_TBES_MASK) >> MSR_MC_STATUS_TBES_SHIFT)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Bit definitions for the architectural error code.
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((code) & MCAX86_ERRCODE_TT_MASK) >> MCAX86_ERRCODE_TT_SHIFT)
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((code) & MCAX86_ERRCODE_RRRR_MASK) >> MCAX86_ERRCODE_RRRR_SHIFT)
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((code) & MCAX86_ERRCODE_PP_MASK) >> MCAX86_ERRCODE_PP_SHIFT)
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((code) & MCAX86_ERRCODE_II_MASK) >> MCAX86_ERRCODE_II_SHIFT)
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((code) & MCAX86_ERRCODE_T_MASK) >> MCAX86_ERRCODE_T_SHIFT)
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost (((code) & MCAX86_ERRCODE_MMM_MASK) >> MCAX86_ERRCODE_MMM_SHIFT)
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost (((code) & MCAX86_ERRCODE_CCCC_MASK) >> MCAX86_ERRCODE_CCCC_SHIFT)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Simple error encoding. MASKON are bits that must be set for a match
20c794b39650d115e17a15983b6b82e46238cf45gavinm * at the same time bits indicated by MASKOFF are clear.
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost#define MCAX86_SIMPLE_INTERNAL_PARITY_MASKON 0x0005
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost#define MCAX86_SIMPLE_INTERNAL_PARITY_MASKOFF 0xfffa
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON 0x0400
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKOFF 0xf800
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCAX86_SIMPLE_INTERNAL_UNCLASS_VALUE_MASK 0x03ff
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Macros to make an internal unclassified error code, and to test if
20c794b39650d115e17a15983b6b82e46238cf45gavinm * a given code is internal unclassified.
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCAX86_ERRCODE_ISSIMPLE_INTERNAL_UNCLASS(code) \
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((code) & MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON) == \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((code) & MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKOFF) == 0 && \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((code) & MCAX86_SIMPLE_INTERNAL_UNCLASS_VALUE_MASK) != 0)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Is the given error code a simple error encoding?
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost (code) <= MCAX86_SIMPLE_INTERNAL_PARITY_MASKON || \
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Compound error encoding. We always ignore the 'F' bit (which indicates
20c794b39650d115e17a15983b6b82e46238cf45gavinm * "correction report filtering") in classifying the error type.
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCAX86_COMPOUND_GENERIC_MEMHIER_MASKOFF 0xeff0
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON 0x0800
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCAX86_COMPOUND_BUS_INTERCONNECT_MASKOFF 0xe000
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost#define MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKON 0x0080
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost#define MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKOFF 0xff00
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Macros to make compound error codes and to test for each type.
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((code) & MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON) == \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((code) & MCAX86_COMPOUND_GENERIC_MEMHIER_MASKOFF) == 0)
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((tt) << MCAX86_ERRCODE_TT_SHIFT & MCAX86_ERRCODE_TT_MASK) | \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((rrrr) << MCAX86_ERRCODE_RRRR_SHIFT & MCAX86_ERRCODE_RRRR_MASK) | \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((tt) << MCAX86_ERRCODE_TT_SHIFT & MCAX86_ERRCODE_TT_MASK) | \
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define MCAX86_MKERRCODE_BUS_INTERCONNECT(pp, t, rrrr, ii, ll) \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((pp) << MCAX86_ERRCODE_PP_SHIFT & MCAX86_ERRCODE_PP_MASK) | \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((t) << MCAX86_ERRCODE_T_SHIFT & MCAX86_ERRCODE_T_MASK) | \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((rrrr) << MCAX86_ERRCODE_RRRR_SHIFT & MCAX86_ERRCODE_RRRR_MASK) | \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((ii) << MCAX86_ERRCODE_II_SHIFT & MCAX86_ERRCODE_II_MASK) | \
20c794b39650d115e17a15983b6b82e46238cf45gavinm (((code) & MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON) == \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((code) & MCAX86_COMPOUND_BUS_INTERCONNECT_MASKOFF) == 0)
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost#define MCAX86_MKERRCODE_MEMORY_CONTROLLER (mmm, cccc) \
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost ((mmm) << MCAX86_ERRCODE_MMM_SHIFT & MCAX86_ERRCODE_MMM_MASK) | \
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost ((cccc) << MCAX86_ERRCODE_CCCC_SHIFT & MCAX86_ERRCODE_CCCC_MASK))
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost#define MCAX86_ERRCODE_ISMEMORY_CONTROLLER(code) \
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost (((code) & MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKON) == \
e3d60c9bd991a9826cbfa63b10595d44e123b9c4Adrian Frost ((code) & MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKOFF) == 0)
20c794b39650d115e17a15983b6b82e46238cf45gavinm (!MCAX86_ERRCODE_ISSIMPLE(code) && !MCAX86_ERRCODE_ISCOMPOUND(code))
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#endif /* _SYS_MCA_X86_H */