dnet.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2004 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_DNET_H
#define _SYS_DNET_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/* debug flags */
#define DNETTRACE 0x01
#define DNETERRS 0x02
#define DNETRECV 0x04
#define DNETDDI 0x08
#define DNETSEND 0x10
#define DNETINT 0x20
#define DNETSENSE 0x40
#define DNETREGCFG 0x80
#ifdef DEBUG
#define DNETDEBUG 1
#endif
/* Misc */
#define DNETIDNUM 0 /* DNET Id; zero works */
/* board state */
#define DNET_IDLE 0
#define DNET_WAITRCV 1
#define DNET_XMTBUSY 2
#define DNET_ERROR 3
#define SUCCESS 0
#define FAILURE 1
#define DEC_VENDOR_ID 0x1011
#define DEVICE_ID_21040 0x0002
#define DEVICE_ID_21041 0x0014
#define DEVICE_ID_21140 0x0009
/* Apparently, the 21143 and 142 are distinguished by revision ID */
#define DEVICE_ID_21142 0x0019
#define DEVICE_ID_21143 0x0019
#define COGENT_EM100 0x12
#define COGENT_QUARTET400 0x13
#define COGENT_EM110TX 0x14
#define VENDOR_ID_OFFSET 32
#define ASANTE_ETHER 0x000094
#define COGENT_ETHER 0x000092
#define ADAPTEC_ETHER 0x0000d1
#define ZNYX_ETHER 0x00c095
#define COGENT_SROM_ID 0x7c
#define COGENT_ANA6911A_C 0x2a
#define COGENT_ANA6911AC_C 0x2b
#define GLD_TX_OK 0 /* return code for GLD Tx ok */
#ifndef GLD_INTR_WAIT
/* Temporary until this makes it into the build environment's gld.h */
#endif
#ifndef REALMODE
#else /* REALMODE */
#endif /* REALMODE */
#define SROM_SIZE 128
#define PRIORITY_LEVEL 5
#define HASH_POLY 0x04C11DB6
#define HASH_CRC 0xFFFFFFFFU
#define DNET_10MBPS 10
/* User defined PCI config space registers */
#define PCI_DNET_CONF_CFDD 0x40
/* CSR Description */
#define BUS_MODE_REG 0x00
#define TX_POLL_REG 0x08
#define RX_POLL_REG 0x10
#define RX_BASE_ADDR_REG 0x18
#define TX_BASE_ADDR_REG 0x20
#define STATUS_REG 0x28
#define OPN_MODE_REG 0x30
#define INT_MASK_REG 0x38
#define MISSED_FRAME_REG 0x40
#define ETHER_ROM_REG 0x48
/* Helpful defines for register access */
/* Bit descriptions of CSR registers */
/* BUS_MODE_REG, CSR0 */
#define SW_RESET 0x01UL
#define BURST_SIZE 0x2000UL
/* TX_POLL_REG, CSR1 */
#define TX_POLL_DEMAND 0x01
/* RX_POLL_REG, CSR2 */
#define RX_POLL_DEMAND 0x01
/* STATUS_REG, CSR5 */
#define TX_INTR 0x01UL
#define TX_STOPPED 0x02UL
#define TX_BUFFER_UNAVAILABLE 0x04UL
#define TX_JABBER_TIMEOUT 0x08UL
#define TX_UNDERFLOW 0x20UL
#define RX_INTR 0x40UL
#define RX_UNAVAIL_INTR 0x80UL
#define RX_STOP_INTR 0x0100UL
#define LINK_INTR 0x1000UL
#define SYS_ERR 0x2000UL
#define ABNORMAL_INTR_SUMM 0x8000UL
#define NORMAL_INTR_SUMM 0x10000UL
#define RECEIVE_PROCESS_STATE 0xe0000UL
#define SYS_ERR_BITS 0x3800000UL
#define PARITY_ERROR 0x00000000UL
#define MASTER_ABORT 0x00800000UL
#define TARGET_ABORT 0x01000000UL
/* OPN_REG , CSR6 */
#define HASH_FILTERING (1UL<<0)
/* INT_MASK_REG , CSR7 */
#define TX_INTERRUPT_MASK 0x01UL
#define TX_STOPPED_MASK 0x02UL
#define TX_BUFFER_UNAVAIL_MASK 0x04UL
#define TX_JABBER_MASK 0x08UL
#define TX_UNDERFLOW_MASK 0x20UL
#define RX_INTERRUPT_MASK 0x40UL
#define RX_UNAVAIL_MASK 0x80UL
#define RX_STOP_MASK 0x00100UL
#define GPTIMER_INTR 0x800UL
#define LINK_INTR_MASK 0x01000UL
#define SYSTEM_ERROR_MASK 0x02000UL
#define ABNORMAL_INTR_MASK 0x08000UL
#define NORMAL_INTR_MASK 0x10000UL
/* MISSED_FRAME_REG, CSR8 */
#define MISSED_FRAME_MASK 0x0ffffUL
#define OVERFLOW_COUNTER_MASK 0xffe0000UL
/* Serial ROM Register CSR9 */
#define SROM_MAX_CYCLES 5UL
#define SEL_CHIP 0x01UL
#define SEL_CLK 0x02UL
#define DATA_IN 0x04UL
#define DATA_OUT 0x08UL
#define HIGH_ADDRESS_BIT 0x20UL
#define SEL_ROM 0x800UL
#define READ_OP 0x4000UL
#define MII_PHY_ADDR_ALIGN 23
#define MII_REG_ADDR_ALIGN 18
#define MII_WRITE_DATA_POSITION 17
#define MII_DATA_IN_POSITION 19
/* GPR Timer reg, CSR11 */
/* SIA Connectivity reg, CSR13 (040, 041, 142) */
#define AUTO_CONFIG 0x05UL
#define BNC_CONFIG 0x0DUL
#define SIA_CONNECT_MASK 0xFFFF0000UL
#define SIA_TXRX_MASK 0xFFFFFFFFUL
#define SIA_GENERAL_MASK 0xFFFF0000UL
#define SIA_TXRX_MASK_TP 0xFFFFFFFFUL
#define SIA_GENRL_MASK_TP 0x00UL
#define SIA_CONN_MASK_AUI 0xEF09UL
#define SIA_TXRX_MASK_AUI 0x0000F73DUL
#define SIA_GENRL_MASK_AUI 0x0000000EUL
#define CSR15_C
#define MEDIA_TP 0
#define MEDIA_BNC 1
#define MEDIA_AUI 2
#define MEDIA_SYM_SCR 3
#define MEDIA_TP_FD 4
#define MEDIA_SYM_SCR_FD 5
#define MEDIA_100T4 6
#define MEDIA_100FX 7
#define MEDIA_100FX_FD 8
#define MEDIA_MII 9
/* CSR15 */
#define MEDIA_CAP_100T4 0x8000UL
#define MEDIA_CAP_100FDX 0x4000UL
#define MEDIA_CAP_100HDX 0x2000UL
#define MEDIA_CAP_10FDX 0x1000UL
#define MEDIA_CAP_10HDX 0x800UL
/*
* In GPR and reset sequences in the ROM this is used to decide wheather the
* CWE bit should be set when writing to the GPR. However, the CWE bit is
* different on the 143 and 140, so we pick a bit where we can safely store
* this information in the ROM structure before writing it out to the GPR
* register itself
*/
/* command block bit flags from SROM */
#define CMD_PS (1<<0)
#define CMD_MEDIABIT_MASK 0xE
#define MAX_SEQ 8
#define MAX_ADAPTERS 8
#define MAX_MEDIA 8
struct dnetinstance;
typedef void (*timercb_t)(struct dnetinstance *);
typedef struct _media_block_t {
int type;
int gprseqlen;
int rstseqlen;
int media_code;
unsigned int hassia:1;
union {
struct {
int phy_num;
} mii;
struct {
} sia;
} un;
typedef struct leaf_format {
int block_count;
int is_static;
} LEAF_FORMAT;
typedef struct srom_format {
int init_from_srom;
/* elements used to store Version 1,3 and proprietary formats */
} SROM_FORMAT;
#define SROM_VERSION 18
#define SROM_ADAPTER_CNT 19
#define SROM_NETADDR 20
#define SROM_LEAF_OFFSET 26
#define SROM_MBZ 6
#define SROM_MBZ2 15
#define SROM_MBZ3 17
#define MEDIA_CODE_MASK 0x3F
#define EXT_BIT 0x40
struct dnetinstance {
int io_reg; /* mapped register */
int board_type; /* board type: 21040 or 21140 */
int full_duplex;
int bnc_indicator; /* Flag for BNC connector */
int secondary; /* SROM read as all zero */
int leaf;
int vendor_21140;
int vendor_revision;
int promisc;
int need_saddr;
int max_tx_desc; /* max xmit descriptors */
#ifndef REALMODE
char multicast_cnt[MCASTBUF_SIZE];
int max_rx_desc; /* max recv descriptors */
int pgmask;
int pgshft;
int nxmit_desc; /* #of xmit descriptors */
int nrecv_desc; /* #of recv descriptors */
/* used for xmit */
int need_gld_sched;
#endif
int tx_current_desc; /* Current Tx descriptor */
int rx_current_desc; /* Current descriptor of Rx */
int transmitted_desc; /* Descriptor count xmitted */
int free_desc; /* Descriptors available */
int mii_speed;
int mii_duplex;
int phyaddr;
struct {
int _10mb;
int _100mb;
int _10mb_fd;
int _100mb_fd;
} v1_phy_media;
int disable_scrambler;
int overrun_workaround;
int interrupts_disabled;
int mii_up;
struct hackintr_inf *hackintr_inf;
struct {
} timer;
};
/*
* Macro to convert Virtual to physical address
*/
#define DNET_KVTOP(vaddr) \
#pragma pack(1)
#ifndef REALMODE
#else
#endif
/*
* Receive descriptor description
*/
struct rx_desc_type {
struct {
volatile uint32_t
overflow : 01,
crc : 01,
dribbling : 01,
mii_err : 01,
rcv_watchdog : 01,
frame_type : 01,
collision : 01,
frame2long : 01,
last_desc : 01,
first_desc : 01,
multi_frame : 01,
runt_frame : 01,
u_data_type : 02,
desc_err : 01,
err_summary : 01,
frame_len : 14,
filter_fail : 01,
own : 01;
} desc0;
struct {
volatile uint32_t
buffer_size1 : 11,
buffer_size2 : 11,
not_used : 02,
chaining : 01,
end_of_ring : 01,
rsvd1 : 06;
} desc1;
};
/*
* Receive descriptor description
*/
struct tx_desc_type {
struct {
volatile uint32_t
deferred : 1,
underflow : 1,
link_fail : 1,
collision_count : 4,
heartbeat_fail : 1,
excess_collision : 1,
late_collision : 1,
no_carrier : 1,
carrier_loss : 1,
rsvd1 : 2,
tx_jabber_to : 1,
err_summary : 1,
rsvd : 15,
own : 1;
} desc0;
struct {
volatile uint32_t
buffer_size1 : 11,
buffer_size2 : 11,
filter_type0 : 1,
disable_padding : 1,
chaining : 1,
end_of_ring : 1,
crc_disable : 1,
setup_packet : 1,
filter_type1 : 1,
first_desc : 1,
last_desc : 1,
int_on_comp : 1;
} desc1;
};
#define DNET_END_OF_RING 0x2000000
#pragma pack()
#ifdef __cplusplus
}
#endif
#endif /* _SYS_DNET_H */