controlregs.h revision ae115bc77f6fcde83175c75b4206dc2e50747966
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_CONTROLREGS_H
#define _SYS_CONTROLREGS_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifndef _ASM
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file describes the x86 architecture control registers which
* are part of the privileged architecture.
*
* Many of these definitions are shared between IA-32-style and
* AMD64-style processors.
*/
/* CR0 Register */
/* XX64 eliminate these compatibility defines */
#define FMT_CR0 \
"\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe"
/*
* Set the FPU-related control bits to explain to the processor that
* we're managing FPU state:
* - set monitor coprocessor (allow TS bit to control FPU)
* - set numeric exception (disable IGNNE# mechanism)
* - set task switch (#nm on first fp instruction)
* - clear emulate math bit (cause we're not emulating!)
*/
#define CR0_ENABLE_FPU_FLAGS(cr) \
/*
* Set the FPU-related control bits to explain to the processor that
* we're -not- managing FPU state:
* - set emulate (all fp instructions cause #nm)
*/
#define CR0_DISABLE_FPU_FLAGS(cr) \
/* CR3 Register */
#define FMT_CR3 "\20\5pcd\4pwt"
/* CR4 Register */
/* 0x0800 reserved */
/* 0x1000 reserved */
#define CR4_VMXE 0x2000
#define CR4_SMXE 0x4000
#define FMT_CR4 \
"\20\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge" \
"\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
/*
* Enable the SSE-related control bits to explain to the processor that
* we're managing XMM state and exceptions
*/
#define CR4_ENABLE_SSE_FLAGS(cr) \
/*
* Disable the SSE-related control bits to explain to the processor
* that we're NOT managing XMM state
*/
#define CR4_DISABLE_SSE_FLAGS(cr) \
/* Intel's SYSENTER configuration registers */
/* AMD's EFER register */
#define FMT_AMD_EFER \
"\20\17ffxsr\15svme\14nxe\13lma\11lme\1sce"
/* AMD's SYSCFG register */
#define FMT_AMD_SYSCFG \
"\20\26tom2\25mvdm\24mfdm\23mfde"
/* AMD's FS.base and GS.base MSRs */
/* AMD's configuration MSRs, weakly documented in the revision guide */
#define MSR_AMD_DC_CFG 0xc0011022
/* AMD's HWCR MSR */
#define MSR_AMD_HWCR 0xc0010015
/* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
#define MSR_AMD_NB_CFG 0xc001001f
#define MSR_BU_CFG 0xc0011023
/* AMD */
#define MSR_AMD_PATCHLEVEL 0x8b
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_CONTROLREGS_H */