controlregs.h revision 799823bbed51a695d01e13511bbb1369980bb714
199767f8919635c4928607450d9e0abb932109ceToomas Soome * CDDL HEADER START
199767f8919635c4928607450d9e0abb932109ceToomas Soome * The contents of this file are subject to the terms of the
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Common Development and Distribution License (the "License").
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199767f8919635c4928607450d9e0abb932109ceToomas Soome * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
199767f8919635c4928607450d9e0abb932109ceToomas Soome * See the License for the specific language governing permissions
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199767f8919635c4928607450d9e0abb932109ceToomas Soome * When distributing Covered Code, include this CDDL HEADER in each
199767f8919635c4928607450d9e0abb932109ceToomas Soome * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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199767f8919635c4928607450d9e0abb932109ceToomas Soome * CDDL HEADER END
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Copyright 2015, Joyent, Inc.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * This file describes the x86 architecture control registers which
199767f8919635c4928607450d9e0abb932109ceToomas Soome * are part of the privileged architecture.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Many of these definitions are shared between IA-32-style and
199767f8919635c4928607450d9e0abb932109ceToomas Soome * AMD64-style processors.
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* CR0 Register */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR0_NW 0x20000000 /* not writethrough */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR0_MP 0x00000002 /* monitor coprocessor */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR0_PE 0x00000001 /* protection enabled */
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* XX64 eliminate these compatibility defines */
199767f8919635c4928607450d9e0abb932109ceToomas Soome "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe"
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Set the FPU-related control bits to explain to the processor that
199767f8919635c4928607450d9e0abb932109ceToomas Soome * we're managing FPU state:
199767f8919635c4928607450d9e0abb932109ceToomas Soome * - set monitor coprocessor (allow TS bit to control FPU)
199767f8919635c4928607450d9e0abb932109ceToomas Soome * - set numeric exception (disable IGNNE# mechanism)
199767f8919635c4928607450d9e0abb932109ceToomas Soome * - set task switch (#nm on first fp instruction)
199767f8919635c4928607450d9e0abb932109ceToomas Soome * - clear emulate math bit (cause we're not emulating!)
199767f8919635c4928607450d9e0abb932109ceToomas Soome (((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM)
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Set the FPU-related control bits to explain to the processor that
199767f8919635c4928607450d9e0abb932109ceToomas Soome * we're -not- managing FPU state:
199767f8919635c4928607450d9e0abb932109ceToomas Soome * - set emulate (all fp instructions cause #nm)
199767f8919635c4928607450d9e0abb932109ceToomas Soome * - clear monitor coprocessor (so fwait/wait doesn't #nm)
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* CR3 Register */
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* CR4 Register */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_VME 0x0001 /* virtual-8086 mode extensions */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_PVI 0x0002 /* protected-mode virtual interrupts */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_DE 0x0008 /* debugging extensions */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_PSE 0x0010 /* page size extensions */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_PAE 0x0020 /* physical address extension */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_MCE 0x0040 /* machine check enable */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_PCE 0x0100 /* perf-monitoring counter enable */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* 0x0800 reserved */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* 0x1000 reserved */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_OSXSAVE 0x40000 /* OS xsave/xrestore support */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define CR4_SMEP 0x100000 /* NX for user pages in kernel */
199767f8919635c4928607450d9e0abb932109ceToomas Soome "\20\25smep\23osxsav\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge" \
199767f8919635c4928607450d9e0abb932109ceToomas Soome "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Enable the SSE-related control bits to explain to the processor that
199767f8919635c4928607450d9e0abb932109ceToomas Soome * we're managing XMM state and exceptions
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Disable the SSE-related control bits to explain to the processor
199767f8919635c4928607450d9e0abb932109ceToomas Soome * that we're NOT managing XMM state
199767f8919635c4928607450d9e0abb932109ceToomas Soome ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT))
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* Intel's SYSENTER configuration registers */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* Intel's microcode registers */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_INTC_UCODE_WRITE 0x79 /* microcode write */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_INTC_UCODE_REV 0x8b /* microcode revision */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define INTC_UCODE_REV_SHIFT 32 /* Bits 63:32 */
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* Intel's platform identification */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define INTC_PLATFORM_ID_SHIFT 50 /* Bit 52:50 */
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* AMD's EFER register */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_EFER_FFXSR 0x4000 /* fast fxsave/fxrstor */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_EFER_NXE 0x0800 /* no-execute enable */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_EFER_LMA 0x0400 /* long mode active (read-only) */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_EFER_LME 0x0100 /* long mode enable */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_EFER_SCE 0x0001 /* system call extensions */
199767f8919635c4928607450d9e0abb932109ceToomas Soome "\20\17ffxsr\15svme\14nxe\13lma\11lme\1sce"
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* AMD's SYSCFG register */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */
199767f8919635c4928607450d9e0abb932109ceToomas Soome "\20\26tom2\25mvdm\24mfdm\23mfde"
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* AMD's syscall/sysret MSRs */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* AMD's FS.base and GS.base MSRs */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define MSR_AMD_TSCAUX 0xc0000103 /* %ecx value on rdtscp insn */
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* AMD's configuration MSRs, weakly documented in the revision guide */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3)
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10)
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* AMD's HWCR MSR */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20)
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* AMD's osvw MSRs */
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Enable PCI Extended Configuration Space (ECS) on Greyhound
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AMD_GH_NB_CFG_EN_ECS (UINT64_C(1) << 46)
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* AMD microcode patch loader */
199767f8919635c4928607450d9e0abb932109ceToomas Soome#endif /* !_SYS_CONTROLREGS_H */