controlregs.h revision 2201b2775f8b4401fc93f5257f9b621395159f2c
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c1c61f44e88f4c8c155272ee56d868043146096asb * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo * Use is subject to license terms.
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo#pragma ident "%Z%%M% %I% %E% SMI"
678453a8ed49104d8adad58f3ba591bdc39883e8speerextern "C" {
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo * This file describes the x86 architecture control registers which
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo * are part of the privileged architecture.
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo * Many of these definitions are shared between IA-32-style and
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo * AMD64-style processors.
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo/* CR0 Register */
678453a8ed49104d8adad58f3ba591bdc39883e8speer/* XX64 eliminate these compatibility defines */
678453a8ed49104d8adad58f3ba591bdc39883e8speer "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe"
678453a8ed49104d8adad58f3ba591bdc39883e8speer/* CR3 Register */
678453a8ed49104d8adad58f3ba591bdc39883e8speer/* CR4 Register */
678453a8ed49104d8adad58f3ba591bdc39883e8speer#define CR4_VME 0x0001 /* virtual-8086 mode extensions */
678453a8ed49104d8adad58f3ba591bdc39883e8speer#define CR4_PVI 0x0002 /* protected-mode virtual interrupts */
678453a8ed49104d8adad58f3ba591bdc39883e8speer#define CR4_PAE 0x0020 /* physical address extension */
c1c61f44e88f4c8c155272ee56d868043146096asb#define CR4_PCE 0x0100 /* perf-monitoring counter enable */
c1c61f44e88f4c8c155272ee56d868043146096asb#define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */
678453a8ed49104d8adad58f3ba591bdc39883e8speer "\20\13xmme\12fxsr\11pce\10pge\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
678453a8ed49104d8adad58f3ba591bdc39883e8speer/* Intel's SYSENTER configuration registers */
678453a8ed49104d8adad58f3ba591bdc39883e8speer#define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo/* AMD's EFER register */
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo#define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */
c1c61f44e88f4c8c155272ee56d868043146096asb#define AMD_EFER_LMA 0x400 /* long mode active (read-only) */
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo#define AMD_EFER_SCE 0x001 /* system call extensions */
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo "\20\14nxe\13lma\11lme\1sce"
678453a8ed49104d8adad58f3ba591bdc39883e8speer/* AMD's SYSCFG register */
678453a8ed49104d8adad58f3ba591bdc39883e8speer#define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */
1ae0874509b6811fdde1dfd46f0d93fd09867a3fheppo#define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */
c1c61f44e88f4c8c155272ee56d868043146096asb "\20\26tom2\25mvdm\24mfdm\23mfde"
844e62a3ec8c8ff5175bb35d1c38446e060730f6raghuram/* AMD's syscall/sysret MSRs */
c1c61f44e88f4c8c155272ee56d868043146096asb#define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */
c1c61f44e88f4c8c155272ee56d868043146096asb#define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */
c1c61f44e88f4c8c155272ee56d868043146096asb#define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */
678453a8ed49104d8adad58f3ba591bdc39883e8speer#define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */
678453a8ed49104d8adad58f3ba591bdc39883e8speer/* AMD's FS.base and GS.base MSRs */
678453a8ed49104d8adad58f3ba591bdc39883e8speer#define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */
678453a8ed49104d8adad58f3ba591bdc39883e8speer#define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */
678453a8ed49104d8adad58f3ba591bdc39883e8speer#define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */
844e62a3ec8c8ff5175bb35d1c38446e060730f6raghuram/* AMD's configuration MSRs, weakly documented in the revision guide */
844e62a3ec8c8ff5175bb35d1c38446e060730f6raghuram#define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3)
844e62a3ec8c8ff5175bb35d1c38446e060730f6raghuram#define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10)
844e62a3ec8c8ff5175bb35d1c38446e060730f6raghuram/* AMD's HWCR MSR */
844e62a3ec8c8ff5175bb35d1c38446e060730f6raghuram#define AMD_HWCR_FFDIS 0x40 /* set to disable TLB Flush Filter */
844e62a3ec8c8ff5175bb35d1c38446e060730f6raghuram/* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
844e62a3ec8c8ff5175bb35d1c38446e060730f6raghuram#define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20)
844e62a3ec8c8ff5175bb35d1c38446e060730f6raghuram#endif /* !_SYS_CONTROLREGS_H */