core_pcbe.c revision ac13ce240ba9273d4f6a0b39f769310a90ab85d3
1N/A * The contents of this file are subject to the terms of the 1N/A * Common Development and Distribution License (the "License"). 1N/A * You may not use this file except in compliance with the License. 1N/A * See the License for the specific language governing permissions 1N/A * and limitations under the License. 1N/A * When distributing Covered Code, include this CDDL HEADER in each 1N/A * If applicable, add the following below this CDDL HEADER, with the 1N/A * fields enclosed by brackets "[]" replaced with your own identifying 1N/A * information: Portions Copyright [yyyy] [name of copyright owner] 1N/A * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 1N/A * This file contains preset event names from the Performance Application 1N/A * Programming Interface v3.5 which included the following notice: 1N/A * Copyright (c) 2005,6 1N/A * Innovative Computing Labs 1N/A * Computer Science Department, 1N/A * University of Tennessee, 1N/A * All Rights Reserved. 1N/A * Redistribution and use in source and binary forms, with or without 1N/A * modification, are permitted provided that the following conditions are met: 1N/A * * Redistributions of source code must retain the above copyright notice, 1N/A * this list of conditions and the following disclaimer. 1N/A * * Redistributions in binary form must reproduce the above copyright 1N/A * notice, this list of conditions and the following disclaimer in the 1N/A * documentation and/or other materials provided with the distribution. 1N/A * * Neither the name of the University of Tennessee nor the names of its 1N/A * contributors may be used to endorse or promote products derived from 1N/A * this software without specific prior written permission. 1N/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1N/A * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1N/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1N/A * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 1N/A * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 1N/A * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 1N/A * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 1N/A * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 1N/A * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 1N/A * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 1N/A * POSSIBILITY OF SUCH DAMAGE. 1N/A * This open source software license conforms to the BSD License template. 1N/A * Performance Counter Back-End for Intel processors supporting Architectural 1N/A * Performance Monitoring. 1N/A * Processor Event Select register fields 1N/A#
define CORE_USR (
1ULL <<
16)
/* Count while not in ring 0 */ 1N/A#
define CORE_OS (
1ULL <<
17)
/* Count while in ring 0 */ 1N/A#
define CORE_PC (
1ULL <<
19)
/* Enable pin control */ 1N/A#
define CORE_INT (
1ULL <<
20)
/* Enable interrupt on overflow */ 1N/A#
define CORE_ANYTHR (
1ULL <<
21)
/* Count event for any thread on core */ 1N/A * Fixed-function counter attributes 1N/A * Number of bits for specifying each FFC's attributes in the control register 1N/A * CondChgd and OvfBuffer fields of global status and overflow control registers 1N/A * Only the lower 32-bits can be written to in the general-purpose 1N/A * counters. The higher bits are extended from bit 31; all ones if 1N/A * bit 31 is one and all zeros otherwise. 1N/A * The fixed-function counters do not have this restriction. * Counting an event for all cores or all bus agents requires cpc_cpu privileges {
"PAPI_tot_ins",
0xc0,
0x00 },
/* inst_retired.any_p */ {
"PAPI_br_msp",
0xc5,
0x00 },
/* br_inst_retired.mispred */ {
"PAPI_br_ntk",
0xc4,
0x03 },
/* br_inst_retired.pred_not_taken|pred_taken */ {
"PAPI_br_prc",
0xc4,
0x05 },
/* br_inst_retired.pred_not_taken|pred_taken */ {
"PAPI_hw_int",
0xc8,
0x00 },
/* hw_int_rvc */ {
"PAPI_tot_iis",
0xaa,
0x01 },
/* macro_insts.decoded */ {
"PAPI_l1_dca",
0x43,
0x01 },
/* l1d_all_ref */ {
"PAPI_l1_icm",
0x81,
0x00 },
/* l1i_misses */ {
"PAPI_l1_icr",
0x80,
0x00 },
/* l1i_reads */ {
"PAPI_l1_tcw",
0x41,
0x0f },
/* l1d_cache_st.mesi */ {
"PAPI_l2_stm",
0x2a,
0x41 },
/* l2_st.self.i_state */ {
"PAPI_l2_tca",
0x2e,
0x4f },
/* l2_rqsts.self.demand.mesi */ {
"PAPI_l2_tch",
0x2e,
0x4e },
/* l2_rqsts.mes */ {
"PAPI_l2_tcm",
0x2e,
0x41 },
/* l2_rqsts.self.demand.i_state */ {
"PAPI_l2_tcw",
0x2a,
0x4f },
/* l2_st.self.mesi */ {
"PAPI_ld_ins",
0xc0,
0x01 },
/* inst_retired.loads */ {
"PAPI_lst_ins",
0xc0,
0x03 },
/* inst_retired.loads|stores */ {
"PAPI_tlb_dm",
0x08,
0x01 },
/* dtlb_misses.any */ {
"PAPI_tlb_im",
0x82,
0x12 },
/* itlb.small_miss|large_miss */ {
"PAPI_tlb_tl",
0x0c,
0x03 },
/* page_walks */ {
"PAPI_l1_dcm",
0xcb,
0x01 },
/* mem_load_retired.l1d_miss */ * The events listed in the following table can be counted on all * general-purpose counters on processors that are of Penryn and Merom Family /* Alphabetical order of event name */ {
"baclears",
0x0,
0xe6 },
{
"bogus_br",
0x0,
0xe4 },
{
"br_bac_missp_exec",
0x0,
0x8a },
{
"br_call_exec",
0x0,
0x92 },
{
"br_call_missp_exec",
0x0,
0x93 },
{
"br_cnd_exec",
0x0,
0x8b },
{
"br_cnd_missp_exec",
0x0,
0x8c },
{
"br_ind_call_exec",
0x0,
0x94 },
{
"br_ind_exec",
0x0,
0x8d },
{
"br_ind_missp_exec",
0x0,
0x8e },
{
"br_inst_decoded",
0x0,
0xe0 },
{
"br_inst_exec",
0x0,
0x88 },
{
"br_inst_retired",
0x0,
0xc4 },
{
"br_inst_retired_mispred",
0x0,
0xc5 },
{
"br_missp_exec",
0x0,
0x89 },
{
"br_ret_bac_missp_exec",
0x0,
0x91 },
{
"br_ret_exec",
0x0,
0x8f },
{
"br_ret_missp_exec",
0x0,
0x90 },
{
"br_tkn_bubble_1",
0x0,
0x97 },
{
"br_tkn_bubble_2",
0x0,
0x98 },
{
"cpu_clk_unhalted",
0x0,
0x3c },
{
"cycles_int",
0x0,
0xc6 },
{
"cycles_l1i_mem_stalled",
0x0,
0x86 },
{
"dtlb_misses",
0x0,
0x08 },
{
"eist_trans",
0x0,
0x3a },
{
"fp_mmx_trans",
0x0,
0xcc },
{
"hw_int_rcv",
0x0,
0xc8 },
{
"ild_stall",
0x0,
0x87 },
{
"inst_queue",
0x0,
0x83 },
{
"inst_retired",
0x0,
0xc0 },
{
"itlb_miss_retired",
0x0,
0xc9 },
{
"l1d_all_ref",
0x0,
0x43 },
{
"l1d_cache_ld",
0x0,
0x40 },
{
"l1d_cache_lock",
0x0,
0x42 },
{
"l1d_cache_st",
0x0,
0x41 },
{
"l1d_m_evict",
0x0,
0x47 },
{
"l1d_m_repl",
0x0,
0x46 },
{
"l1d_pend_miss",
0x0,
0x48 },
{
"l1d_prefetch",
0x0,
0x4e },
{
"l1d_repl",
0x0,
0x45 },
{
"l1d_split",
0x0,
0x49 },
{
"l1i_misses",
0x0,
0x81 },
{
"l1i_reads",
0x0,
0x80 },
{
"load_block",
0x0,
0x03 },
{
"load_hit_pre",
0x0,
0x4c },
{
"machine_nukes",
0x0,
0xc3 },
{
"macro_insts",
0x0,
0xaa },
{
"memory_disambiguation",
0x0,
0x09 },
{
"misalign_mem_ref",
0x0,
0x05 },
{
"page_walks",
0x0,
0x0c },
{
"pref_rqsts_dn",
0x0,
0xf8 },
{
"pref_rqsts_up",
0x0,
0xf0 },
{
"rat_stalls",
0x0,
0xd2 },
{
"resource_stalls",
0x0,
0xdc },
{
"rs_uops_dispatched",
0x0,
0xa0 },
{
"seg_reg_renames",
0x0,
0xd5 },
{
"seg_rename_stalls",
0x0,
0xd4 },
{
"segment_reg_loads",
0x0,
0x06 },
{
"simd_assist",
0x0,
0xcd },
{
"simd_comp_inst_retired",
0x0,
0xca },
{
"simd_inst_retired",
0x0,
0xc7 },
{
"simd_instr_retired",
0x0,
0xce },
{
"simd_sat_instr_retired",
0x0,
0xcf },
{
"simd_sat_uop_exec",
0x0,
0xb1 },
{
"simd_uop_type_exec",
0x0,
0xb3 },
{
"simd_uops_exec",
0x0,
0xb0 },
{
"sse_pre_exec",
0x0,
0x07 },
{
"sse_pre_miss",
0x0,
0x4b },
{
"store_block",
0x0,
0x04 },
{
"thermal_trip",
0x0,
0x3b },
{
"uops_retired",
0x0,
0xc2 },
{
"x87_ops_retired",
0x0,
0xc1 },
* If any of the pic specific events require privileges, make sure to add a * check in configure_gpc() to find whether an event hard-coded as a number by * the user has any privilege requirements /* Alphabetical order of event name */ {
"cycles_div_busy",
0x0,
0x14 },
{
"fp_comp_ops_exe",
0x0,
0x10 },
{
"idle_during_div",
0x0,
0x18 },
{
"mem_load_retired",
0x0,
0xcb },
{
"rs_uops_dispatched_port",
0x0,
0xa1 },
/* Alphabetical order of event name */ {
"delayed_bypass",
0x0,
0x19 },
{
"fp_assist",
0x0,
0x11 },
/* FFC entries must be in order */ "See Appendix A of the \"Intel 64 and IA-32 Architectures Software" \
" Developer's Manual Volume 3B: System Programming Guide, Part 2\"" \
" Order Number: 253669-026US, Februrary 2008";
/* Used to describe which counters support an event */ #
define C_ALL 0xFFFFFFFFFFFFFFFF/* Architectural events */ {
0xc0,
0x00,
C_ALL,
"inst_retired.any_p" }, \
{
0x3c,
0x01,
C_ALL,
"cpu_clk_unhalted.ref_p" }, \
{
0x2e,
0x4f,
C_ALL,
"longest_lat_cache.reference" }, \
{
0x2e,
0x41,
C_ALL,
"longest_lat_cache.miss" }, \
{
0xc4,
0x00,
C_ALL,
"br_inst_retired.all_branches" }, \
{
0xc5,
0x00,
C_ALL,
"br_misp_retired.all_branches" }
"PAPI_tot_ins",
/* inst_retired.any_p */ "",
/* cpu_clk_unhalted.ref_p */ "",
/* longest_lat_cache.reference */ "",
/* longest_lat_cache.miss */ "",
/* br_inst_retired.all_branches */ "",
/* br_misp_retired.all_branches */ {
0x1d,
0x01,
C0|
C1|
C2|
C3,
"PAPI_hw_int" },
/* hw_int.rcx */ \
{
0x17,
0x01,
C0|
C1|
C2|
C3,
"PAPI_tot_iis" },
/* inst_queue_writes */ \
{
0x43,
0x01,
C0|
C1,
"PAPI_l1_dca" },
/* l1d_all_ref.any */ \
{
0x24,
0x03,
C0|
C1|
C2|
C3,
"PAPI_l1_dcm" },
/* l2_rqsts. loads and rfos */ \
{
0x40,
0x0f,
C0|
C1|
C2|
C3,
"PAPI_l1_dcr" },
/* l1d_cache_ld.mesi */ \
{
0x41,
0x0f,
C0|
C1|
C2|
C3,
"PAPI_l1_dcw" },
/* l1d_cache_st.mesi */ \
{
0x80,
0x03,
C0|
C1|
C2|
C3,
"PAPI_l1_ica" },
/* l1i.reads */ \
{
0x80,
0x02,
C0|
C1|
C2|
C3,
"PAPI_l1_icm" },
/* l1i.misses */ \
{
0x80,
0x03,
C0|
C1|
C2|
C3,
"PAPI_l1_icr" },
/* l1i.reads */ \
{
0x24,
0x33,
C0|
C1|
C2|
C3,
"PAPI_l1_ldm" },
/* l2_rqsts. loads and ifetches */\
{
0x24,
0xff,
C0|
C1|
C2|
C3,
"PAPI_l1_tcm" },
/* l2_rqsts.references */ \
{
0x24,
0x02,
C0|
C1|
C2|
C3,
"PAPI_l2_ldm" },
/* l2_rqsts.ld_miss */ \
{
0x24,
0x08,
C0|
C1|
C2|
C3,
"PAPI_l2_stm" },
/* l2_rqsts.rfo_miss */ \
{
0x24,
0x3f,
C0|
C1|
C2|
C3,
"PAPI_l2_tca" }, \
/* l2_rqsts. loads, rfos and ifetches */ \
{
0x24,
0x15,
C0|
C1|
C2|
C3,
"PAPI_l2_tch" }, \
/* l2_rqsts. ld_hit, rfo_hit and ifetch_hit */ \
{
0x24,
0x2a,
C0|
C1|
C2|
C3,
"PAPI_l2_tcm" }, \
/* l2_rqsts. ld_miss, rfo_miss and ifetch_miss */ \
{
0x24,
0x33,
C0|
C1|
C2|
C3,
"PAPI_l2_tcr" },
/* l2_rqsts. loads and ifetches */\
{
0x24,
0x0c,
C0|
C1|
C2|
C3,
"PAPI_l2_tcw" },
/* l2_rqsts.rfos */ \
{
0x2e,
0x4f,
C0|
C1|
C2|
C3,
"PAPI_l3_tca" },
/* l3_lat_cache.reference */ \
{
0x2e,
0x41,
C0|
C1|
C2|
C3,
"PAPI_l3_tcm" },
/* l3_lat_cache.misses */ \
{
0x0b,
0x01,
C0|
C1|
C2|
C3,
"PAPI_ld_ins" },
/* mem_inst_retired.loads */ \
{
0x0b,
0x03,
C0|
C1|
C2|
C3,
"PAPI_lst_ins" }, \
/* mem_inst_retired.loads and stores */ \
{
0x26,
0xf0,
C0|
C1|
C2|
C3,
"PAPI_prf_dm" },
/* l2_data_rqsts.prefetch.mesi */ \
{
0x49,
0x01,
C0|
C1|
C2|
C3,
"PAPI_tlb_dm" },
/* dtlb_misses.any */ \
{
0x85,
0x01,
C0|
C1|
C2|
C3,
"PAPI_tlb_im" }
/* itlb_misses.any */{
0x80,
0x02,
C0|
C1|
C2|
C3,
"l1i.misses" }, \
{
0x80,
0x03,
C0|
C1|
C2|
C3,
"l1i.reads" }, \
{
0x87,
0x0F,
C0|
C1|
C2|
C3,
"ild_stall.any" }, \
{
0x87,
0x04,
C0|
C1|
C2|
C3,
"ild_stall.iq_full" }, \
{
0x87,
0x01,
C0|
C1|
C2|
C3,
"ild_stall.lcp" }, \
{
0x87,
0x02,
C0|
C1|
C2|
C3,
"ild_stall.mru" }, \
{
0x87,
0x08,
C0|
C1|
C2|
C3,
"ild_stall.regen" }, \
{
0xE6,
0x02,
C0|
C1|
C2|
C3,
"baclear.bad_target" }, \
{
0xE8,
0x01,
C0|
C1|
C2|
C3,
"bpu_clears.early" }, \
{
0xE8,
0x02,
C0|
C1|
C2|
C3,
"bpu_clears.late" }, \
{
0xE5,
0x01,
C0|
C1|
C2|
C3,
"bpu_missed_call_ret" }, \
{
0xE0,
0x01,
C0|
C1|
C2|
C3,
"br_inst_decoded" }, \
{
0x88,
0x7F,
C0|
C1|
C2|
C3,
"br_inst_exec.any" }, \
{
0x88,
0x02,
C0|
C1|
C2|
C3,
"br_inst_exec.direct" }, \
{
0x88,
0x10,
C0|
C1|
C2|
C3,
"br_inst_exec.direct_near_call" }, \
{
0x88,
0x20,
C0|
C1|
C2|
C3,
"br_inst_exec.indirect_near_call" }, \
{
0x88,
0x04,
C0|
C1|
C2|
C3,
"br_inst_exec.indirect_non_call" }, \
{
0x88,
0x30,
C0|
C1|
C2|
C3,
"br_inst_exec.near_calls" }, \
{
0x88,
0x07,
C0|
C1|
C2|
C3,
"br_inst_exec.non_calls" }, \
{
0x88,
0x08,
C0|
C1|
C2|
C3,
"br_inst_exec.return_near" }, \
{
0x89,
0x7F,
C0|
C1|
C2|
C3,
"br_misp_exec.any" }, \
{
0x89,
0x02,
C0|
C1|
C2|
C3,
"br_misp_exec.direct" }, \
{
0x89,
0x10,
C0|
C1|
C2|
C3,
"br_misp_exec.direct_near_call" }, \
{
0x89,
0x20,
C0|
C1|
C2|
C3,
"br_misp_exec.indirect_near_call" }, \
{
0x89,
0x04,
C0|
C1|
C2|
C3,
"br_misp_exec.indirect_non_call" }, \
{
0x89,
0x30,
C0|
C1|
C2|
C3,
"br_misp_exec.near_calls" }, \
{
0x89,
0x07,
C0|
C1|
C2|
C3,
"br_misp_exec.non_calls" }, \
{
0x89,
0x08,
C0|
C1|
C2|
C3,
"br_misp_exec.return_near" }, \
{
0x17,
0x01,
C0|
C1|
C2|
C3,
"inst_queue_writes" }, \
{
0x1E,
0x01,
C0|
C1|
C2|
C3,
"inst_queue_write_cycles" }, \
{
0xA7,
0x01,
C0|
C1|
C2|
C3,
"baclear_force_iq" }, \
{
0xD0,
0x01,
C0|
C1|
C2|
C3,
"macro_insts.decoded" }, \
{
0xA6,
0x01,
C0|
C1|
C2|
C3,
"macro_insts.fusions_decoded" }, \
{
0x19,
0x01,
C0|
C1|
C2|
C3,
"two_uop_insts_decoded" }, \
{
0x18,
0x01,
C0|
C1|
C2|
C3,
"inst_decoded.dec0" }, \
{
0xD1,
0x04,
C0|
C1|
C2|
C3,
"uops_decoded.esp_folding" }, \
{
0xD1,
0x08,
C0|
C1|
C2|
C3,
"uops_decoded.esp_sync" }, \
{
0xD1,
0x02,
C0|
C1|
C2|
C3,
"uops_decoded.ms" }, \
{
0x20,
0x01,
C0|
C1|
C2|
C3,
"lsd_overflow" }, \
{
0x0E,
0x01,
C0|
C1|
C2|
C3,
"uops_issued.any" }, \
{
0x0E,
0x02,
C0|
C1|
C2|
C3,
"uops_issued.fused" }, \
{
0xA2,
0x20,
C0|
C1|
C2|
C3,
"resource_stalls.fpcw" }, \
{
0xA2,
0x02,
C0|
C1|
C2|
C3,
"resource_stalls.load" }, \
{
0xA2,
0x40,
C0|
C1|
C2|
C3,
"resource_stalls.mxcsr" }, \
{
0xA2,
0x04,
C0|
C1|
C2|
C3,
"resource_stalls.rs_full" }, \
{
0xA2,
0x01,
C0|
C1|
C2|
C3,
"resource_stalls.any" }, \
{
0xD2,
0x01,
C0|
C1|
C2|
C3,
"rat_stalls.flags" }, \
{
0xD2,
0x02,
C0|
C1|
C2|
C3,
"rat_stalls.registers" }, \
{
0xD2,
0x04,
C0|
C1|
C2|
C3,
"rat_stalls.rob_read_port" }, \
{
0xD2,
0x0F,
C0|
C1|
C2|
C3,
"rat_stalls.any" }, \
{
0xD4,
0x01,
C0|
C1|
C2|
C3,
"seg_rename_stalls" }, \
{
0xD5,
0x01,
C0|
C1|
C2|
C3,
"es_reg_renames" }, \
{
0x10,
0x02,
C0|
C1|
C2|
C3,
"fp_comp_ops_exe.mmx" }, \
{
0x10,
0x01,
C0|
C1|
C2|
C3,
"fp_comp_ops_exe.x87" }, \
{
0x14,
0x02,
C0|
C1|
C2|
C3,
"arith.mul" }, \
{
0x12,
0x04,
C0|
C1|
C2|
C3,
"simd_int_128.pack" }, \
{
0x12,
0x20,
C0|
C1|
C2|
C3,
"simd_int_128.packed_arith" }, \
{
0x12,
0x10,
C0|
C1|
C2|
C3,
"simd_int_128.packed_logical" }, \
{
0x12,
0x01,
C0|
C1|
C2|
C3,
"simd_int_128.packed_mpy" }, \
{
0x12,
0x02,
C0|
C1|
C2|
C3,
"simd_int_128.packed_shift" }, \
{
0x12,
0x08,
C0|
C1|
C2|
C3,
"simd_int_128.unpack" }, \
{
0xFD,
0x04,
C0|
C1|
C2|
C3,
"simd_int_64.pack" }, \
{
0xFD,
0x20,
C0|
C1|
C2|
C3,
"simd_int_64.packed_arith" }, \
{
0xFD,
0x10,
C0|
C1|
C2|
C3,
"simd_int_64.packed_logical" }, \
{
0xFD,
0x01,
C0|
C1|
C2|
C3,
"simd_int_64.packed_mpy" }, \
{
0xFD,
0x02,
C0|
C1|
C2|
C3,
"simd_int_64.packed_shift" }, \
{
0xFD,
0x08,
C0|
C1|
C2|
C3,
"simd_int_64.unpack" }, \
{
0xB1,
0x01,
C0|
C1|
C2|
C3,
"uops_executed.port0" }, \
{
0xB1,
0x02,
C0|
C1|
C2|
C3,
"uops_executed.port1" }, \
{
0x40,
0x04,
C0|
C1,
"l1d_cache_ld.e_state" }, \
{
0x40,
0x01,
C0|
C1,
"l1d_cache_ld.i_state" }, \
{
0x40,
0x08,
C0|
C1,
"l1d_cache_ld.m_state" }, \
{
0x40,
0x0F,
C0|
C1,
"l1d_cache_ld.mesi" }, \
{
0x41,
0x04,
C0|
C1,
"l1d_cache_st.e_state" }, \
{
0x41,
0x08,
C0|
C1,
"l1d_cache_st.m_state" }, \
{
0x41,
0x0F,
C0|
C1,
"l1d_cache_st.mesi" }, \
{
0x42,
0x04,
C0|
C1,
"l1d_cache_lock.e_state" }, \
{
0x42,
0x08,
C0|
C1,
"l1d_cache_lock.m_state" }, \
{
0x43,
0x01,
C0|
C1,
"l1d_all_ref.any" }, \
{
0x4B,
0x01,
C0|
C1,
"mmx2_mem_exec.nta" }, \
{
0x4C,
0x01,
C0|
C1,
"load_hit_pre" }, \
{
0x4E,
0x02,
C0|
C1,
"l1d_prefetch.miss" }, \
{
0x4E,
0x01,
C0|
C1,
"l1d_prefetch.requests" }, \
{
0x51,
0x04,
C0|
C1,
"l1d.m_evict" }, \
{
0x51,
0x02,
C0|
C1,
"l1d.m_repl" }, \
{
0x51,
0x08,
C0|
C1,
"l1d.m_snoop_evict" }, \
{
0x51,
0x01,
C0|
C1,
"l1d.repl" }, \
{
0x52,
0x01,
C0|
C1,
"l1d_cache_prefetch_lock_fb_hit" }, \
{
0x53,
0x01,
C0|
C1,
"l1d_cache_lock_fb_hit" }, \
{
0x63,
0x02,
C0|
C1,
"cache_lock_cycles.l1d" }, \
{
0x63,
0x01,
C0|
C1,
"cache_lock_cycles.l1d_l2" }, \
{
0x06,
0x04,
C0|
C1|
C2|
C3,
"store_blocks.at_ret" }, \
{
0x06,
0x08,
C0|
C1|
C2|
C3,
"store_blocks.l1d_block" }, \
{
0x06,
0x01,
C0|
C1|
C2|
C3,
"store_blocks.not_sta" }, \
{
0x13,
0x07,
C0|
C1|
C2|
C3,
"load_dispatch.any" }, \
{
0x13,
0x04,
C0|
C1|
C2|
C3,
"load_dispatch.mob" }, \
{
0x13,
0x01,
C0|
C1|
C2|
C3,
"load_dispatch.rs" }, \
{
0x13,
0x02,
C0|
C1|
C2|
C3,
"load_dispatch.rs_delayed" }, \
{
0x08,
0x01,
C0|
C1|
C2|
C3,
"dtlb_load_misses.any" }, \
{
0x08,
0x20,
C0|
C1|
C2|
C3,
"dtlb_load_misses.pde_miss" }, \
{
0x08,
0x02,
C0|
C1|
C2|
C3,
"dtlb_load_misses.walk_completed" }, \
{
0x49,
0x01,
C0|
C1|
C2|
C3,
"dtlb_misses.any" }, \
{
0x49,
0x02,
C0|
C1|
C2|
C3,
"dtlb_misses.walk_completed" }, \
{
0x4F,
0x02,
C0|
C1|
C2|
C3,
"ept.epde_miss" }, \
{
0x4F,
0x08,
C0|
C1|
C2|
C3,
"ept.epdpe_miss" }, \
{
0x85,
0x01,
C0|
C1|
C2|
C3,
"itlb_misses.any" }, \
{
0x85,
0x02,
C0|
C1|
C2|
C3,
"itlb_misses.walk_completed" }, \
{
0x24,
0xAA,
C0|
C1|
C2|
C3,
"l2_rqsts.miss" }, \
{
0x24,
0xFF,
C0|
C1|
C2|
C3,
"l2_rqsts.references" }, \
{
0x24,
0x10,
C0|
C1|
C2|
C3,
"l2_rqsts.ifetch_hit" }, \
{
0x24,
0x20,
C0|
C1|
C2|
C3,
"l2_rqsts.ifetch_miss" }, \
{
0x24,
0x30,
C0|
C1|
C2|
C3,
"l2_rqsts.ifetches" }, \
{
0x24,
0x01,
C0|
C1|
C2|
C3,
"l2_rqsts.ld_hit" }, \
{
0x24,
0x02,
C0|
C1|
C2|
C3,
"l2_rqsts.ld_miss" }, \
{
0x24,
0x03,
C0|
C1|
C2|
C3,
"l2_rqsts.loads" }, \
{
0x24,
0x40,
C0|
C1|
C2|
C3,
"l2_rqsts.prefetch_hit" }, \
{
0x24,
0x80,
C0|
C1|
C2|
C3,
"l2_rqsts.prefetch_miss" }, \
{
0x24,
0xC0,
C0|
C1|
C2|
C3,
"l2_rqsts.prefetches" }, \
{
0x24,
0x04,
C0|
C1|
C2|
C3,
"l2_rqsts.rfo_hit" }, \
{
0x24,
0x08,
C0|
C1|
C2|
C3,
"l2_rqsts.rfo_miss" }, \
{
0x24,
0x0C,
C0|
C1|
C2|
C3,
"l2_rqsts.rfos" }, \
{
0x26,
0xFF,
C0|
C1|
C2|
C3,
"l2_data_rqsts.any" }, \
{
0x26,
0x04,
C0|
C1|
C2|
C3,
"l2_data_rqsts.demand.e_state" }, \
{
0x26,
0x01,
C0|
C1|
C2|
C3,
"l2_data_rqsts.demand.i_state" }, \
{
0x26,
0x08,
C0|
C1|
C2|
C3,
"l2_data_rqsts.demand.m_state" }, \
{
0x26,
0x0F,
C0|
C1|
C2|
C3,
"l2_data_rqsts.demand.mesi" }, \
{
0x26,
0x40,
C0|
C1|
C2|
C3,
"l2_data_rqsts.prefetch.e_state" }, \
{
0x26,
0x10,
C0|
C1|
C2|
C3,
"l2_data_rqsts.prefetch.i_state" }, \
{
0x26,
0x80,
C0|
C1|
C2|
C3,
"l2_data_rqsts.prefetch.m_state" }, \
{
0x26,
0xF0,
C0|
C1|
C2|
C3,
"l2_data_rqsts.prefetch.mesi" }, \
{
0x27,
0x40,
C0|
C1|
C2|
C3,
"l2_write.lock.e_state" }, \
{
0x27,
0x10,
C0|
C1|
C2|
C3,
"l2_write.lock.i_state" }, \
{
0x27,
0x01,
C0|
C1|
C2|
C3,
"l2_write.rfo.i_state" }, \
{
0x27,
0x08,
C0|
C1|
C2|
C3,
"l2_write.rfo.m_state" }, \
{
0x27,
0x0F,
C0|
C1|
C2|
C3,
"l2_write.rfo.mesi" }, \
{
0x28,
0x04,
C0|
C1|
C2|
C3,
"l1d_wb_l2.e_state" }, \
{
0x28,
0x01,
C0|
C1|
C2|
C3,
"l1d_wb_l2.i_state" }, \
{
0x28,
0x08,
C0|
C1|
C2|
C3,
"l1d_wb_l2.m_state" }, \
{
0xF0,
0x80,
C0|
C1|
C2|
C3,
"l2_transactions.any" }, \
{
0xF0,
0x20,
C0|
C1|
C2|
C3,
"l2_transactions.fill" }, \
{
0xF0,
0x04,
C0|
C1|
C2|
C3,
"l2_transactions.ifetch" }, \
{
0xF0,
0x10,
C0|
C1|
C2|
C3,
"l2_transactions.l1d_wb" }, \
{
0xF0,
0x01,
C0|
C1|
C2|
C3,
"l2_transactions.load" }, \
{
0xF0,
0x08,
C0|
C1|
C2|
C3,
"l2_transactions.prefetch" }, \
{
0xF0,
0x02,
C0|
C1|
C2|
C3,
"l2_transactions.rfo" }, \
{
0xF0,
0x40,
C0|
C1|
C2|
C3,
"l2_transactions.wb" }, \
{
0xF1,
0x07,
C0|
C1|
C2|
C3,
"l2_lines_in.any" }, \
{
0xF1,
0x04,
C0|
C1|
C2|
C3,
"l2_lines_in.e_state" }, \
{
0xF2,
0x0F,
C0|
C1|
C2|
C3,
"l2_lines_out.any" }, \
{
0xF2,
0x01,
C0|
C1|
C2|
C3,
"l2_lines_out.demand_clean" }, \
{
0xF2,
0x02,
C0|
C1|
C2|
C3,
"l2_lines_out.demand_dirty" }, \
{
0xF2,
0x04,
C0|
C1|
C2|
C3,
"l2_lines_out.prefetch_clean" }, \
{
0x6C,
0x01,
C0|
C1|
C2|
C3,
"io_transactions" }, \
{
0xB0,
0x80,
C0|
C1|
C2|
C3,
"offcore_requests.any" }, \
{
0xB0,
0x10,
C0|
C1|
C2|
C3,
"offcore_requests.any.rfo" }, \
{
0xB0,
0x40,
C0|
C1|
C2|
C3,
"offcore_requests.l1d_writeback" }, \
{
0x0B,
0x01,
C0|
C1|
C2|
C3,
"mem_inst_retired.loads" }, \
{
0xC0,
0x04,
C0|
C1|
C2|
C3,
"inst_retired.mmx" }, \
{
0xC0,
0x02,
C0|
C1|
C2|
C3,
"inst_retired.x87" }, \
{
0xC7,
0x04,
C0|
C1|
C2|
C3,
"ssex_uops_retired.packed_double" }, \
{
0xC7,
0x01,
C0|
C1|
C2|
C3,
"ssex_uops_retired.packed_single" }, \
{
0xC7,
0x10,
C0|
C1|
C2|
C3,
"ssex_uops_retired.vector_integer" }, \
{
0xC2,
0x01,
C0|
C1|
C2|
C3,
"uops_retired.any" }, \
{
0xC2,
0x04,
C0|
C1|
C2|
C3,
"uops_retired.macro_fused" }, \
{
0xC8,
0x20,
C0|
C1|
C2|
C3,
"itlb_miss_retired" }, \
{
0xCB,
0x80,
C0|
C1|
C2|
C3,
"mem_load_retired.dtlb_miss" }, \
{
0xCB,
0x01,
C0|
C1|
C2|
C3,
"mem_load_retired.l1d_hit" }, \
{
0xCB,
0x02,
C0|
C1|
C2|
C3,
"mem_load_retired.l2_hit" }, \
{
0xCB,
0x10,
C0|
C1|
C2|
C3,
"mem_load_retired.llc_miss" }, \
{
0xCB,
0x04,
C0|
C1|
C2|
C3,
"mem_load_retired.llc_unshared_hit" }, \
{
0xCB,
0x08,
C0|
C1|
C2|
C3,
"mem_load_retired.other_core_l2_hit_hitm" }, \
{
0x0F,
0x02,
C0|
C1|
C2|
C3,
"mem_uncore_retired.other_core_l2_hitm" }, \
{
0x0F,
0x08,
C0|
C1|
C2|
C3,
"mem_uncore_retired.remote_cache_local_home_hit" },\
{
0x0F,
0x10,
C0|
C1|
C2|
C3,
"mem_uncore_retired.remote_dram" }, \
{
0x0F,
0x20,
C0|
C1|
C2|
C3,
"mem_uncore_retired.local_dram" }, \
{
0x0C,
0x01,
C0|
C1|
C2|
C3,
"mem_store_retired.dtlb_miss" }, \
{
0xC4,
0x02,
C0|
C1|
C2|
C3,
"br_inst_retired.near_call" }, \
{
0xC5,
0x02,
C0|
C1|
C2|
C3,
"br_misp_retired.near_call" }, \
{
0xDB,
0x01,
C0|
C1|
C2|
C3,
"uop_unfusion" }, \
{
0xF7,
0x01,
C0|
C1|
C2|
C3,
"fp_assist.all" }, \
{
0xF7,
0x04,
C0|
C1|
C2|
C3,
"fp_assist.input" }, \
{
0xF7,
0x02,
C0|
C1|
C2|
C3,
"fp_assist.output" }, \
{
0xCC,
0x03,
C0|
C1|
C2|
C3,
"fp_mmx_trans.any" }, \
{
0xc4,
0x00,
C0|
C1,
"PAPI_br_ins" },
/* br_inst_retired.any */ \
{
0xc5,
0x00,
C0|
C1,
"PAPI_br_msp" },
/* br_inst_retired.mispred */ \
{
0xc4,
0x03,
C0|
C1,
"PAPI_br_ntk" }, \
/* br_inst_retired.pred_not_taken|mispred_not_taken */ \
{
0xc4,
0x05,
C0|
C1,
"PAPI_br_prc" }, \
/* br_inst_retired.pred_not_taken|pred_taken */ \
{
0xc8,
0x00,
C0|
C1,
"PAPI_hw_int" },
/* hw_int_rcv */ \
{
0xaa,
0x03,
C0|
C1,
"PAPI_tot_iis" },
/* macro_insts.all_decoded */ \
{
0x40,
0x23,
C0|
C1,
"PAPI_l1_dca" },
/* l1d_cache.l1|st */ \
{
0x2a,
0x41,
C0|
C1,
"PAPI_l2_stm" },
/* l2_st.self.i_state */ \
{
0x2e,
0x4f,
C0|
C1,
"PAPI_l2_tca" },
/* longest_lat_cache.reference */ \
{
0x2e,
0x4e,
C0|
C1,
"PAPI_l2_tch" },
/* l2_rqsts.mes */ \
{
0x2e,
0x41,
C0|
C1,
"PAPI_l2_tcm" },
/* longest_lat_cache.miss */ \
{
0x2a,
0x4f,
C0|
C1,
"PAPI_l2_tcw" },
/* l2_st.self.mesi */ \
{
0x08,
0x07,
C0|
C1,
"PAPI_tlb_dm" },
/* data_tlb_misses.dtlb.miss */ \
{
0x82,
0x02,
C0|
C1,
"PAPI_tlb_im" }
/* itlb.misses */ {
0x2,
0x81,
C0|
C1,
"store_forwards.good" }, \
{
0x6,
0x0,
C0|
C1,
"segment_reg_loads.any" }, \
{
0x7,
0x1,
C0|
C1,
"prefetch.prefetcht0" }, \
{
0x7,
0x8,
C0|
C1,
"prefetch.prefetchnta" }, \
{
0x8,
0x7,
C0|
C1,
"data_tlb_misses.dtlb_miss" }, \
{
0x8,
0x5,
C0|
C1,
"data_tlb_misses.dtlb_miss_ld" }, \
{
0x8,
0x9,
C0|
C1,
"data_tlb_misses.l0_dtlb_miss_ld" }, \
{
0x8,
0x6,
C0|
C1,
"data_tlb_misses.dtlb_miss_st" }, \
{
0x10,
0x81,
C0|
C1,
"x87_comp_ops_exe.any.ar" }, \
{
0x11,
0x1,
C0|
C1,
"fp_assist" }, \
{
0x11,
0x81,
C0|
C1,
"fp_assist.ar" }, \
{
0x12,
0x81,
C0|
C1,
"mul.ar" }, \
{
0x13,
0x81,
C0|
C1,
"div.ar" }, \
{
0x14,
0x1,
C0|
C1,
"cycles_div_busy" }, \
{
0x21,
0x0,
C0|
C1,
"l2_ads" }, \
{
0x22,
0x0,
C0|
C1,
"l2_dbus_busy" }, \
{
0x24,
0x0,
C0|
C1,
"l2_lines_in" }, \
{
0x25,
0x0,
C0|
C1,
"l2_m_lines_in" }, \
{
0x26,
0x0,
C0|
C1,
"l2_lines_out" }, \
{
0x27,
0x0,
C0|
C1,
"l2_m_lines_out" }, \
{
0x28,
0x0,
C0|
C1,
"l2_ifetch" }, \
{
0x29,
0x0,
C0|
C1,
"l2_ld" }, \
{
0x2A,
0x0,
C0|
C1,
"l2_st" }, \
{
0x2B,
0x0,
C0|
C1,
"l2_lock" }, \
{
0x2E,
0x0,
C0|
C1,
"l2_rqsts" }, \
{
0x30,
0x0,
C0|
C1,
"l2_reject_bus_q" }, \
{
0x32,
0x0,
C0|
C1,
"l2_no_req" }, \
{
0x3A,
0x0,
C0|
C1,
"eist_trans" }, \
{
0x3B,
0xC0,
C0|
C1,
"thermal_trip" }, \
{
0x3C,
0x1,
C0|
C1,
"cpu_clk_unhalted.bus" }, \
{
0x3C,
0x2,
C0|
C1,
"cpu_clk_unhalted.no_other" }, \
{
0x40,
0x21,
C0|
C1,
"l1d_cache.ld" }, \
{
0x60,
0x0,
C0|
C1,
"bus_request_outstanding" }, \
{
0x61,
0x0,
C0|
C1,
"bus_bnr_drv" }, \
{
0x62,
0x0,
C0|
C1,
"bus_drdy_clocks" }, \
{
0x63,
0x0,
C0|
C1,
"bus_lock_clocks" }, \
{
0x64,
0x0,
C0|
C1,
"bus_data_rcv" }, \
{
0x65,
0x0,
C0|
C1,
"bus_trans_brd" }, \
{
0x66,
0x0,
C0|
C1,
"bus_trans_rfo" }, \
{
0x67,
0x0,
C0|
C1,
"bus_trans_wb" }, \
{
0x68,
0x0,
C0|
C1,
"bus_trans_ifetch" }, \
{
0x69,
0x0,
C0|
C1,
"bus_trans_inval" }, \
{
0x6A,
0x0,
C0|
C1,
"bus_trans_pwr" }, \
{
0x6B,
0x0,
C0|
C1,
"bus_trans_p" }, \
{
0x6C,
0x0,
C0|
C1,
"bus_trans_io" }, \
{
0x6D,
0x0,
C0|
C1,
"bus_trans_def" }, \
{
0x6E,
0x0,
C0|
C1,
"bus_trans_burst" }, \
{
0x6F,
0x0,
C0|
C1,
"bus_trans_mem" }, \
{
0x70,
0x0,
C0|
C1,
"bus_trans_any" }, \
{
0x77,
0x0,
C0|
C1,
"ext_snoop" }, \
{
0x7A,
0x0,
C0|
C1,
"bus_hit_drv" }, \
{
0x7B,
0x0,
C0|
C1,
"bus_hitm_drv" }, \
{
0x7D,
0x0,
C0|
C1,
"busq_empty" }, \
{
0x7E,
0x0,
C0|
C1,
"snoop_stall_drv" }, \
{
0x7F,
0x0,
C0|
C1,
"bus_io_wait" }, \
{
0x80,
0x3,
C0|
C1,
"icache.accesses" }, \
{
0x80,
0x2,
C0|
C1,
"icache.misses" }, \
{
0x82,
0x4,
C0|
C1,
"itlb.flush" }, \
{
0x82,
0x2,
C0|
C1,
"itlb.misses" }, \
{
0xAA,
0x3,
C0|
C1,
"macro_insts.all_decoded" }, \
{
0xB0,
0x80,
C0|
C1,
"simd_uops_exec.ar" }, \
{
0xB1,
0x80,
C0|
C1,
"simd_sat_uop_exec.ar" }, \
{
0xB3,
0x81,
C0|
C1,
"simd_uop_type_exec.mul.ar" }, \
{
0xB3,
0x84,
C0|
C1,
"simd_uop_type_exec.pack.ar" }, \
{
0xB3,
0x88,
C0|
C1,
"simd_uop_type_exec.unpack.ar" }, \
{
0xB3,
0x90,
C0|
C1,
"simd_uop_type_exec.logical.ar" }, \
{
0xB3,
0xA0,
C0|
C1,
"simd_uop_type_exec.arithmetic.ar" }, \
{
0xC2,
0x10,
C0|
C1,
"uops_retired.any" }, \
{
0xC4,
0x0,
C0|
C1,
"br_inst_retired.any" }, \
{
0xC4,
0x1,
C0|
C1,
"br_inst_retired.pred_not_taken" }, \
{
0xC4,
0x2,
C0|
C1,
"br_inst_retired.mispred_not_taken" }, \
{
0xC4,
0x4,
C0|
C1,
"br_inst_retired.pred_taken" }, \
{
0xC4,
0x8,
C0|
C1,
"br_inst_retired.mispred_taken" }, \
{
0xC4,
0xA,
C0|
C1,
"br_inst_retired.mispred" }, \
{
0xC4,
0xF,
C0|
C1,
"br_inst_retired.any1" }, \
{
0xC7,
0x1,
C0|
C1,
"simd_inst_retired.packed_single" }, \
{
0xC7,
0x4,
C0|
C1,
"simd_inst_retired.packed_double" }, \
{
0xC7,
0x10,
C0|
C1,
"simd_inst_retired.vector" }, \
{
0xC7,
0x1F,
C0|
C1,
"simd_inst_retired.any" }, \
{
0xC8,
0x00,
C0|
C1,
"hw_int_rcv" }, \
{
0xCA,
0x1,
C0|
C1,
"simd_comp_inst_retired.packed_single" }, \
{
0xCA,
0x4,
C0|
C1,
"simd_comp_inst_retired.packed_double" }, \
{
0xCB,
0x1,
C0|
C1,
"mem_load_retired.l2_hit" }, \
{
0xCB,
0x2,
C0|
C1,
"mem_load_retired.l2_miss" }, \
{
0xCB,
0x4,
C0|
C1,
"mem_load_retired.dtlb_miss" }, \
{
0xCD,
0x0,
C0|
C1,
"simd_assist" }, \
{
0xCE,
0x0,
C0|
C1,
"simd_instr_retired" }, \
{
0xCF,
0x0,
C0|
C1,
"simd_sat_instr_retired" }, \
{
0xE0,
0x1,
C0|
C1,
"br_inst_decoded" }, \
{
0xE4,
0x1,
C0|
C1,
"bogus_br" }, \
{
0xE6,
0x1,
C0|
C1,
"baclears.any" }
* Initialize string containing list of supported general-purpose counter * events for processors of Penryn and Merom Family /* Calculate space needed to save all the common event names */ /* Obtain Basic CPUID information */ /* No Architectural Performance Monitoring Leaf returned by CPUID */ /* Obtain the Architectural Performance Monitoring Leaf */ * Fixed-Function Counters (FFC) * All Family 6 Model 15 and Model 23 processors have fixed-function * counters. These counters were made Architectural with * Family 6 Model 15 Stepping 9. * Some processors have an errata (AW34) where * versionid is reported as 2 when actually 1. * In this case, fixed-function counters are * model-specific as in Version 1. /* Set HTT-specific names of architectural & FFC events */ * The system seems to have more fixed-function counters than * what this PCBE is able to handle correctly. Default to the * maximum number of fixed-function counters that this driver * General Purpose Counters (GPC) /* Too wide for the overflow bitmap */ /* Check if this ffc has a generic name */ /* GPC events for Family 6 Models 15, 23 and 29 only */ "Core Microarchitecture");
"Intel Arch PerfMon v%d on Family %d Model %d",
* To handle the case where a new performance monitoring setup is run * Process architectural and non-architectural events using GPC /* Calculate space required for the architectural gpc events */ /* Non-architectural events list */ * Determine length of all supported event names * (architectural + non-architectural) /* Allocate memory for this pics list */ * Create the list of all supported events * (architectural + non-architectural) /* Remove trailing comma */ return (
"edge,inv,umask,cmask,anythr");
return (
"edge,pc,inv,umask,cmask");
/* Search architectural events */ /* Search non-architectural events */ /* Is it an event that a GPC can track? */ /* Check if the event can be counted in the fixed-function counters */ * Bits beyond bit-31 in the general-purpose counters can only * be written to by extension of bit 31. We cannot preset * these bits to any value other than all 1s or all 0s. /* Event specified as raw event code */ /* Not a generic event */ * Check if this is a case where the event was * specified directly by its event number * instead of its name string. * Search the event table to find out if the * event specified has an privilege * requirements. Currently none of the * pic-specific counters have any privilege * requirements. Hence only the table * cmn_gpc_events_core_uarch is searched. for (i = 0; i <
nattrs; i++) {
/* Clear out the default umask */ /* Use the user provided umask */ for (i = 0; i <
nattrs; i++) {
/* All fixed-function counters have the same control register */ * If we've been handed an existing configuration, we need only preset /* Allow RDPMC at any ring level */ /* Allow RDPMC only at ring 0 */ /* Clear any overflow indicators before programming the counters */ * General-purpose counter registers have write * restrictions where only the lower 32-bits can be * written to. The rest of the relevant bits are * written to by extension from bit 31 (all ZEROS if * bit-31 is ZERO and all ONE if bit-31 is ONE). This * makes it possible to write to the counter register * only values that have all ONEs or all ZEROs in the * Straighforward case where the higher bits * are all ZEROs or all ONEs. * The high order bits are not all the same. * We save what is currently in the registers * and do not write to it. When we want to do * a read from this register later (in * core_pcbe_sample()), we subtract the value * we save here to get the actual event count. * NOTE: As a result, we will not get overflow * interrupts as expected. * Unlike the general-purpose counters, all relevant * bits of fixed-function counters can be written to. * Collect the control bits for all the * fixed-function counters and write it at one shot /* Enable all the counters */ /* Disable all the counters together */ /* Counter overflowed since our last sample */ "Core Performance Counters",