core_pcbe.c revision 820c9f58018f61ff5e4d61e758c34cdc6d6aa3e4
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Performance Counter Back-End for Intel Family 6 Models 15 and 23
*/
#include <sys/cpc_impl.h>
#include <sys/cpc_pcbe.h>
#include <sys/inttypes.h>
#include <sys/x86_archext.h>
#include <sys/archsystm.h>
#include <sys/privregs.h>
static int core_pcbe_init(void);
static uint_t core_pcbe_ncounters(void);
static const char *core_pcbe_impl_name(void);
static const char *core_pcbe_cpuref(void);
static char *core_pcbe_list_attrs(void);
static uint64_t core_pcbe_overflow_bitmap(void);
void *token);
static void core_pcbe_program(void *token);
static void core_pcbe_allstop(void);
static void core_pcbe_sample(void *token);
static void core_pcbe_free(void *config);
#define FALSE 0
#define TRUE 1
/* Architectural Performance Counter versioning */
#define APC_V1 1
#define APC_V2 2
/* Counter Type */
#define CORE_GPC 0 /* General-Purpose Counter (GPC) */
/* MSR Addresses */
/*
* Processor Event Select register fields
*/
#define CORE_UMASK_SHIFT 8
#define CORE_UMASK_MASK 0xffu
#define CORE_CMASK_SHIFT 24
#define CORE_CMASK_MASK 0xffu
/*
* Fixed-function counter attributes
*/
/*
* Number of bits for specifying each FFC's attributes in the control register
*/
#define CORE_FFC_ATTR_SIZE 4
/*
* CondChgd and OvfBuffer fields of global status and overflow control registers
*/
#define ALL_STOPPED 0ULL
/*
* Only the lower 32-bits can be written to in the general-purpose
* counters. The higher bits are extended from bit 31; all ones if
* bit 31 is one and all zeros otherwise.
*
* The fixed-function counters do not have this restriction.
*/
typedef struct core_pcbe_config {
PCBE_VER_1, /* pcbe_ver */
core_pcbe_ncounters, /* pcbe_ncounters */
core_pcbe_impl_name, /* pcbe_impl_name */
core_pcbe_cpuref, /* pcbe_cpuref */
core_pcbe_list_events, /* pcbe_list_events */
core_pcbe_list_attrs, /* pcbe_list_attrs */
core_pcbe_event_coverage, /* pcbe_event_coverage */
core_pcbe_overflow_bitmap, /* pcbe_overflow_bitmap */
core_pcbe_configure, /* pcbe_configure */
core_pcbe_program, /* pcbe_program */
core_pcbe_allstop, /* pcbe_allstop */
core_pcbe_sample, /* pcbe_sample */
core_pcbe_free /* pcbe_free */
};
struct nametable {
const char *name;
};
#define NT_END 0xFF
/*
* Counting an event for all cores or all bus agents requires cpc_cpu privileges
*/
static const struct nametable common_gpc_events[] = {
/* Alphabetical order of event name */
{ "baclears", 0x0, 0xe6 },
{ "bogus_br", 0x0, 0xe4 },
{ "br_bac_missp_exec", 0x0, 0x8a },
{ "br_call_exec", 0x0, 0x92 },
{ "br_call_missp_exec", 0x0, 0x93 },
{ "br_cnd_exec", 0x0, 0x8b },
{ "br_cnd_missp_exec", 0x0, 0x8c },
{ "br_ind_call_exec", 0x0, 0x94 },
{ "br_ind_exec", 0x0, 0x8d },
{ "br_ind_missp_exec", 0x0, 0x8e },
{ "br_inst_decoded", 0x0, 0xe0 },
{ "br_inst_exec", 0x0, 0x88 },
{ "br_inst_retired", 0x0, 0xc4 },
{ "br_inst_retired_mispred", 0x0, 0xc5 },
{ "br_missp_exec", 0x0, 0x89 },
{ "br_ret_bac_missp_exec", 0x0, 0x91 },
{ "br_ret_exec", 0x0, 0x8f },
{ "br_ret_missp_exec", 0x0, 0x90 },
{ "br_tkn_bubble_1", 0x0, 0x97 },
{ "br_tkn_bubble_2", 0x0, 0x98 },
{ "cpu_clk_unhalted", 0x0, 0x3c },
{ "cycles_int", 0x0, 0xc6 },
{ "cycles_l1i_mem_stalled", 0x0, 0x86 },
{ "dtlb_misses", 0x0, 0x08 },
{ "eist_trans", 0x0, 0x3a },
{ "esp", 0x0, 0xab },
{ "fp_mmx_trans", 0x0, 0xcc },
{ "hw_int_rcv", 0x0, 0xc8 },
{ "ild_stall", 0x0, 0x87 },
{ "inst_queue", 0x0, 0x83 },
{ "inst_retired", 0x0, 0xc0 },
{ "itlb", 0x0, 0x82 },
{ "itlb_miss_retired", 0x0, 0xc9 },
{ "l1d_all_ref", 0x0, 0x43 },
{ "l1d_cache_ld", 0x0, 0x40 },
{ "l1d_cache_lock", 0x0, 0x42 },
{ "l1d_cache_st", 0x0, 0x41 },
{ "l1d_m_evict", 0x0, 0x47 },
{ "l1d_m_repl", 0x0, 0x46 },
{ "l1d_pend_miss", 0x0, 0x48 },
{ "l1d_prefetch", 0x0, 0x4e },
{ "l1d_repl", 0x0, 0x45 },
{ "l1d_split", 0x0, 0x49 },
{ "l1i_misses", 0x0, 0x81 },
{ "l1i_reads", 0x0, 0x80 },
{ "load_block", 0x0, 0x03 },
{ "load_hit_pre", 0x0, 0x4c },
{ "machine_nukes", 0x0, 0xc3 },
{ "macro_insts", 0x0, 0xaa },
{ "memory_disambiguation", 0x0, 0x09 },
{ "page_walks", 0x0, 0x0c },
{ "pref_rqsts_dn", 0x0, 0xf8 },
{ "pref_rqsts_up", 0x0, 0xf0 },
{ "rat_stalls", 0x0, 0xd2 },
{ "resource_stalls", 0x0, 0xdc },
{ "rs_uops_dispatched", 0x0, 0xa0 },
{ "seg_reg_renames", 0x0, 0xd5 },
{ "seg_rename_stalls", 0x0, 0xd4 },
{ "segment_reg_loads", 0x0, 0x06 },
{ "simd_assist", 0x0, 0xcd },
{ "simd_comp_inst_retired", 0x0, 0xca },
{ "simd_inst_retired", 0x0, 0xc7 },
{ "simd_instr_retired", 0x0, 0xce },
{ "simd_sat_instr_retired", 0x0, 0xcf },
{ "simd_sat_uop_exec", 0x0, 0xb1 },
{ "simd_uop_type_exec", 0x0, 0xb3 },
{ "simd_uops_exec", 0x0, 0xb0 },
{ "sse_pre_exec", 0x0, 0x07 },
{ "sse_pre_miss", 0x0, 0x4b },
{ "store_block", 0x0, 0x04 },
{ "thermal_trip", 0x0, 0x3b },
{ "uops_retired", 0x0, 0xc2 },
{ "x87_ops_retired", 0x0, 0xc1 },
};
/*
* If any of the pic specific events require privileges, make sure to add a
* check in configure_gpc() to find whether an event hard-coded as a number by
* the user has any privilege requirements
*/
static const struct nametable pic0_events[] = {
/* Alphabetical order of event name */
{ "cycles_div_busy", 0x0, 0x14 },
{ "fp_comp_ops_exe", 0x0, 0x10 },
{ "idle_during_div", 0x0, 0x18 },
{ "mem_load_retired", 0x0, 0xcb },
{ "rs_uops_dispatched_port", 0x0, 0xa1 },
};
static const struct nametable pic1_events[] = {
/* Alphabetical order of event name */
{ "delayed_bypass", 0x0, 0x19 },
{ "div", 0x0, 0x13 },
{ "fp_assist", 0x0, 0x11 },
{ "mul", 0x0, 0x12 },
};
static char **gpc_names;
char *ffc_names[] = {
"instr_retired.any",
"cpu_clk_unhalted.core",
"cpu_clk_unhalted.ref",
};
static uint64_t control_ffc;
static uint64_t control_gpc;
static uint64_t control_mask;
static const char *core_impl_name = "Core Microarchitecture";
static const char *core_cpuref =
"See Appendix A of the \"Intel 64 and IA-32 Architectures Software" \
" Developer's Manual Volume 3B: System Programming Guide, Part 2\"" \
" Order Number: 253669-026US, Februrary 2008";
static int
core_pcbe_init(void)
{
struct cpuid_regs cp;
const struct nametable *n;
uint64_t i;
const struct nametable *picspecific_events;
return (-1);
/* Obtain the Architectural Performance Monitoring Leaf */
(void) __cpuid_insn(&cp);
/*
* All Family 6 Model 15 and Model 23 processors have fixed-function
* counters. These counters were made Architectural with
* Family 6 Model 9 Stepping 9.
*/
switch (versionid) {
case 0:
return (-1);
case APC_V2:
if (num_ffc == 0) {
/*
* Some processors have an errata (AW34) where
* versionid is reported as 2 when actually 1.
* In this case, fixed-function counters are
* model-specific as in Version 1.
*/
num_ffc = 3;
width_ffc = 40;
}
break;
default:
/*
* For higher versions currently unsupported,
* default to Version 1
*/
num_ffc = 3;
width_ffc = 40;
break;
}
if (num_ffc >= 64)
return (-1);
/*
* The system seems to have more fixed-function counters than
* what this PCBE is able to handle correctly. Default to the
* maximum number of fixed-function counters that this driver
* is aware of.
*/
}
if (num_gpc >= 64)
return (-1);
if (total_pmc > 64) {
/* Too wide for the overflow bitmap */
return (-1);
}
/* General-purpose Counters (GPC) */
if (num_gpc > 0) {
/* Calculate space needed to save all the common event names */
common_size = 0;
}
for (i = 0; i < num_gpc; i++) {
size = 0;
switch (i) {
case 0:
break;
case 1:
break;
default:
break;
}
if (picspecific_events != NULL) {
for (n = picspecific_events;
n++) {
}
}
gpc_names[i] =
gpc_names[i][0] = '\0';
if (picspecific_events != NULL) {
for (n = picspecific_events;
n++) {
}
}
n++) {
}
/*
* Remove trailing comma.
*/
}
}
/*
* Fixed-function Counters (FFC) are already listed individually in
* ffc_names[]
*/
return (0);
}
static uint_t core_pcbe_ncounters()
{
return (total_pmc);
}
static const char *core_pcbe_impl_name(void)
{
return (core_impl_name);
}
static const char *core_pcbe_cpuref(void)
{
return (core_cpuref);
}
{
} else {
}
}
static char *core_pcbe_list_attrs(void)
{
return ("edge,pc,inv,umask,cmask");
}
static const struct nametable *
{
const struct nametable *n;
int compare_result;
compare_result = -1;
if (compare_result <= 0) {
break;
}
}
if (compare_result == 0) {
return (n);
}
return (NULL);
}
static uint64_t
core_pcbe_event_coverage(char *event)
{
int i;
bitmap = 0;
/* Is it an event that a GPC can track? */
bitmap |= 1ULL;
}
/* Check if the event can be counted in the fixed-function counters */
if (num_ffc > 0) {
for (i = 0; i < num_ffc; i++) {
}
}
}
return (bitmap);
}
static uint64_t
{
extern int kcpc_hw_overflow_intr_installed;
(*kcpc_hw_enable_cpc_intr)();
return (overflow_bitmap);
}
static int
{
if (secpolicy_cpc_cpu(crgetcred()) != 0) {
return (CPC_ATTR_REQUIRES_PRIVILEGE);
}
}
return (0);
}
static int
{
const struct nametable *n;
const struct nametable *m;
const struct nametable *picspecific_events;
uint_t i;
long event_num;
if (((preset & BITS_EXTENDED_FROM_31) != 0) &&
((preset & BITS_EXTENDED_FROM_31) !=
/*
* Bits beyond bit-31 in the general-purpose counters can only
* be written to by extension of bit 31. We cannot preset
* these bits to any value other than all 1s or all 0s.
*/
return (CPC_ATTRIBUTE_OUT_OF_RANGE);
}
if (n == NULL) {
switch (picnum) {
case 0:
break;
case 1:
break;
default:
break;
}
if (picspecific_events != NULL) {
if (n == NULL) {
/*
* Check if this is a case where the event was
* specified directly by its event number
* instead of its name string.
*/
0) {
return (CPC_INVALID_EVENT);
}
/*
* Search the event table to find out if the
* event specified has an privilege
* requirements. Currently none of the
* pic-specific counters have any privilege
* requirements. Hence only the
* common_gpc_events table is searched.
*/
for (m = common_gpc_events;
m++) {
break;
}
}
n = &nt_raw;
} else {
n = m;
}
}
}
}
for (i = 0; i < nattrs; i++) {
return (CPC_ATTRIBUTE_OUT_OF_RANGE);
}
return (CPC_ATTRIBUTE_OUT_OF_RANGE);
}
} else {
return (CPC_INVALID_ATTRIBUTE);
}
}
if (flags & CPC_COUNT_USER)
if (flags & CPC_COUNT_SYSTEM)
if (flags & CPC_OVF_NOTIFY_EMT)
if (check_cpc_securitypolicy(&conf, n) != 0) {
return (CPC_ATTR_REQUIRES_PRIVILEGE);
}
return (0);
}
static int
{
return (CPC_INVALID_PICNUM);
}
return (CPC_INVALID_EVENT);
}
if (nattrs != 0) {
return (CPC_INVALID_ATTRIBUTE);
}
/* All fixed-function counters have the same control register */
if (flags & CPC_COUNT_USER)
if (flags & CPC_COUNT_SYSTEM)
if (flags & CPC_OVF_NOTIFY_EMT)
return (0);
}
/*ARGSUSED*/
static int
void *token)
{
int ret;
/*
* If we've been handed an existing configuration, we need only preset
* the counter value.
*/
else /* CORE_FFC */
return (0);
}
return (CPC_INVALID_PICNUM);
}
} else {
}
return (ret);
}
static void
core_pcbe_program(void *token)
{
if (kcpc_allow_nonpriv(token))
/* Allow RDPMC at any ring level */
else
/* Allow RDPMC only at ring 0 */
/* Clear any overflow indicators before programming the counters */
perf_global_ctrl = 0;
perf_fixed_ctr_ctrl = 0;
/*
* General-purpose counter registers have write
* restrictions where only the lower 32-bits can be
* written to. The rest of the relevant bits are
* written to by extension from bit 31 (all ZEROS if
* bit-31 is ZERO and all ONE if bit-31 is ONE). This
* makes it possible to write to the counter register
* only values that have all ONEs or all ZEROs in the
* higher bits.
*/
/*
* Straighforward case where the higher bits
* are all ZEROs or all ONEs.
*/
} else {
/*
* The high order bits are not all the same.
* We save what is currently in the registers
* and do not write to it. When we want to do
* a read from this register later (in
* core_pcbe_sample()), we subtract the value
* we save here to get the actual event count.
*
* NOTE: As a result, we will not get overflow
* interrupts as expected.
*/
}
} else {
/*
* Unlike the general-purpose counters, all relevant
* bits of fixed-function counters can be written to.
*/
/*
* Collect the control bits for all the
* fixed-function counters and write it at one shot
* later in this function
*/
}
cfg = (core_pcbe_config_t *)
}
/* Enable all the counters */
}
static void
core_pcbe_allstop(void)
{
/* Disable all the counters together */
}
static void
core_pcbe_sample(void *token)
{
} else {
}
} else {
/* Counter overflowed since our last sample */
1;
}
cfg =
}
}
static void
core_pcbe_free(void *config)
{
}
static struct modlpcbe core_modlpcbe = {
"Core Performance Counters",
};
static struct modlinkage core_modl = {
};
int
_init(void)
{
if (core_pcbe_init() != 0) {
return (ENOTSUP);
}
return (mod_install(&core_modl));
}
int
_fini(void)
{
return (mod_remove(&core_modl));
}
int
{
}