vmxnet3_defs.h revision ca5345b6a28e9e9bfd0c135121d62c6b35a5390d
/*
* Copyright (C) 2007 VMware, Inc. All rights reserved.
*
* The contents of this file are subject to the terms of the Common
* Development and Distribution License (the "License") version 1.0
* and no later version. You may not use this file except in
* compliance with the License.
*
* You can obtain a copy of the License at
*
* See the License for the specific language governing permissions
* and limitations under the License.
*/
/*
* vmxnet3_defs.h --
*
* Definitions shared by device emulation and guest drivers for
* VMXNET3 NIC
*/
#ifndef _VMXNET3_DEFS_H_
#define _VMXNET3_DEFS_H_
#include <upt1_defs.h>
/* all registers are 32 bit wide */
/* BAR 1 */
/* BAR 0 */
/*
* The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at
* offset 14h) as well as the MSI-X BAR are combined into one PhysMem region:
* <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE-->
* -------------------------------------------------------------------------
* -------------------------------------------------------------------------
* VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h"
*/
#define VMXNET3_PHYSMEM_PAGES 4
#define VMXNET3_REG_ALIGN_MASK 0x7
/* I/O Mapped access to registers */
#define VMXNET3_IO_TYPE_PT 0
#define VMXNET3_IO_TYPE_VD 1
/*
* The Sun Studio compiler complains if enums overflow INT_MAX, so we can only
* use an enum with gcc. We keep this here for the convenience of merging
* from upstream.
*/
#ifdef __GNUC__
typedef enum {
VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
VMXNET3_CMD_FIRST_GET = 0xF00D0000,
} Vmxnet3_Cmd;
#else
#define VMXNET3_CMD_FIRST_SET 0xCAFE0000U
#define VMXNET3_CMD_FIRST_GET 0xF00D0000U
#endif
/* Adaptive Ring Info Flags */
#define VMXNET3_DISABLE_ADAPTIVE_RING 1
#pragma pack(1)
typedef struct Vmxnet3_TxDesc {
#pragma pack()
/* TxDesc.OM values */
#define VMXNET3_OM_NONE 0
#define VMXNET3_OM_CSUM 2
#define VMXNET3_OM_TSO 3
/* fields in TxDesc we access w/o using bit fields */
#define VMXNET3_TXD_EOP_SHIFT 12
#define VMXNET3_TXD_CQ_SHIFT 13
#define VMXNET3_TXD_GEN_SHIFT 14
#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
#define VMXNET3_TXD_GEN_SIZE 1
#define VMXNET3_TXD_EOP_SIZE 1
#define VMXNET3_HDR_COPY_SIZE 128
#pragma pack(1)
typedef struct Vmxnet3_TxDataDesc {
#pragma pack()
#define VMXNET3_TCD_GEN_SHIFT 31
#define VMXNET3_TCD_GEN_SIZE 1
#define VMXNET3_TCD_TXIDX_SHIFT 0
#define VMXNET3_TCD_TXIDX_SIZE 12
#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
#pragma pack(1)
typedef struct Vmxnet3_TxCompDesc {
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_RxDesc {
#pragma pack()
/* values of RXD.BTYPE */
#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
/* fields in RxDesc we access w/o using bit fields */
#define VMXNET3_RXD_BTYPE_SHIFT 14
#define VMXNET3_RXD_GEN_SHIFT 31
#pragma pack(1)
typedef struct Vmxnet3_RxCompDesc {
#pragma pack()
/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
#define VMXNET3_RCD_TUC_SHIFT 16
#define VMXNET3_RCD_IPC_SHIFT 19
/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
#define VMXNET3_RCD_TYPE_SHIFT 56
#define VMXNET3_RCD_GEN_SHIFT 63
#define VMXNET3_RCD_CSUM_OK \
/* value of RxCompDesc.rssType */
#define VMXNET3_RCD_RSS_TYPE_NONE 0
#define VMXNET3_RCD_RSS_TYPE_IPV4 1
#define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
#define VMXNET3_RCD_RSS_TYPE_IPV6 3
#define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
/* a union for accessing all cmd/completion descriptors */
typedef union Vmxnet3_GenericDesc {
#define VMXNET3_INIT_GEN 1
/* Max size of a single tx buffer */
/* # of tx desc needed for a tx buffer size */
#define VMXNET3_TXD_NEEDED(size) \
/* max # of tx descs for a non-tso pkt */
#define VMXNET3_MAX_TXD_PER_PKT 16
/* Max size of a single rx buffer */
/* Minimum size of a type 0 buffer */
#define VMXNET3_MIN_T0_BUF_SIZE 128
#define VMXNET3_MAX_CSUM_OFFSET 1024
/* Ring base address alignment */
#define VMXNET3_RING_BA_ALIGN 512
/* Ring size must be a multiple of 32 */
#define VMXNET3_RING_SIZE_ALIGN 32
/* Max ring size */
#define VMXNET3_TX_RING_MAX_SIZE 4096
#define VMXNET3_TC_RING_MAX_SIZE 4096
#define VMXNET3_RX_RING_MAX_SIZE 4096
#define VMXNET3_RC_RING_MAX_SIZE 8192
/* a list of reasons for queue stop */
/* EOP desc of a pkt */
/* completion */
/* supported */
/* in vmkernel */
/* completion descriptor types */
#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
#define VMXNET3_GOS_BITS_UNK 0 /* unknown */
#define VMXNET3_GOS_BITS_32 1
#define VMXNET3_GOS_BITS_64 2
#define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
#define VMXNET3_GOS_TYPE_LINUX 1
#define VMXNET3_GOS_TYPE_WIN 2
#define VMXNET3_GOS_TYPE_SOLARIS 3
#define VMXNET3_GOS_TYPE_FREEBSD 4
#define VMXNET3_GOS_TYPE_PXE 5
/* All structures in DriverShared are padded to multiples of 8 bytes */
#pragma pack(1)
typedef struct Vmxnet3_GOSInfo {
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_DriverInfo {
#pragma pack()
#define VMXNET3_REV1_MAGIC 0xbabefee1
/*
* QueueDescPA must be 128 bytes aligned. It points to an array of
* Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
* The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
* Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
*/
#define VMXNET3_QUEUE_DESC_ALIGN 128
#pragma pack(1)
typedef struct Vmxnet3_MiscConf {
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_TxQueueConf {
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_RxQueueConf {
#pragma pack()
enum vmxnet3_intr_mask_mode {
VMXNET3_IMM_AUTO = 0,
VMXNET3_IMM_ACTIVE = 1,
VMXNET3_IMM_LAZY = 2
};
enum vmxnet3_intr_type {
VMXNET3_IT_AUTO = 0,
VMXNET3_IT_INTX = 1,
VMXNET3_IT_MSI = 2,
VMXNET3_IT_MSIX = 3
};
#define VMXNET3_MAX_TX_QUEUES 8
#define VMXNET3_MAX_RX_QUEUES 16
/* addition 1 for events */
#define VMXNET3_MAX_INTRS 25
/* value of intrCtrl */
#pragma pack(1)
typedef struct Vmxnet3_IntrConf {
char autoMask;
/* for each intr */
#pragma pack()
/* one bit per VLAN ID, the size is in the units of uint32_t */
#pragma pack(1)
typedef struct Vmxnet3_QueueStatus {
char stopped;
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_TxQueueCtrl {
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_RxQueueCtrl {
char updateRxProd;
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_RxFilterConf {
#pragma pack()
#define VMXNET3_PM_MAX_FILTERS 6
#define VMXNET3_PM_MAX_PATTERN_SIZE 128
/* filters */
#pragma pack(1)
typedef struct Vmxnet3_PM_PktFilter {
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_PMConf {
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_VariableLenConfDesc {
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_DSDevRead {
/* read-only region for device, read by dev in response to a SET cmd */
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_TxQueueDesc {
/* Driver read after a GET command */
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_RxQueueDesc {
/* Driver read after a GET command */
#pragma pack()
#pragma pack(1)
typedef struct Vmxnet3_DriverShared {
/* 64-bit boundaries */
#pragma pack()
#define VMXNET3_ECR_RQERR (1 << 0)
/* flip the gen bit of a ring */
/* only use this if moving the idx won't affect the gen bit */
(idx)++; \
(idx) = 0; \
} \
}
#define VMXNET3_MAX_MTU 9000
#define VMXNET3_MIN_MTU 60
#define VMXNET3_LINK_DOWN 0
#define VMXWIFI_DRIVER_SHARED_LEN 8192
#define VMXNET3_DID_PASSTHRU 0xFFFF
#endif /* _VMXNET3_DEFS_H_ */