508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * O.S : Solaris
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * BY : Erich Chen
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Description: SCSI RAID Device Driver for
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * ARECA RAID Host adapter
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Copyright (C) 2002,2007 Areca Technology Corporation All rights reserved.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Copyright (C) 2002,2007 Erich Chen
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * E-mail: erich@areca.com.tw
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Redistribution and use in source and binary forms, with or without
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * modification, are permitted provided that the following conditions
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 1. Redistributions of source code must retain the above copyright
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * notice, this list of conditions and the following disclaimer.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 2. Redistributions in binary form must reproduce the above copyright
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * notice, this list of conditions and the following disclaimer in the
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * documentation and/or other materials provided with the distribution.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 3. The party using or redistributing the source code and binary forms
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * agrees to the disclaimer below and the terms and conditions set forth
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * SUCH DAMAGE.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * CDDL HEADER START
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * The contents of this file are subject to the terms of the
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Common Development and Distribution License (the "License").
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * You may not use this file except in compliance with the License.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * or http://www.opensolaris.org/os/licensing.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * See the License for the specific language governing permissions
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * and limitations under the License.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * When distributing Covered Code, include this CDDL HEADER in each
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * If applicable, add the following below this CDDL HEADER, with the
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * fields enclosed by brackets "[]" replaced with your own identifying
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * information: Portions Copyright [yyyy] [name of copyright owner]
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * CDDL HEADER END
ed632624009d91d344479bf05ec24b9e0772939bColin Yi * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Use is subject to license terms.
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38 */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MAX_XFER_LEN 0x00200000 /* 2M */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_MAX_DPC 16 /* defer procedure call */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* MAX_OUTSTANDING_CMD+8 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_CCB_EXPIRED_TIME 600 /* 10 min */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ddi_put8(handle, (uint8_t *)(a), (uint8_t)(d))
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ddi_put16(handle, (uint16_t *)(a), (uint16_t)(d))
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ddi_put32(handle, (uint32_t *)(a), (uint32_t)(d))
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ddi_put64(handle, (uint64_t *)(a), (uint64_t)(d))
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore/* NOTE: GETG4ADDRTL(cdbp) is int32_t */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore (cmdlen == 10) ? (uint32_t)GETG1ADDR(cdbp) : \
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore ((uint64_t)GETG4ADDR(cdbp) << 32) | (uint32_t)GETG4ADDRTL(cdbp))
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */
7d14b8f218dc86a431d15e352b4bf15fbb1b3596Robert Mustacchi#define PCI_DEVICE_ID_ARECA_1882 0x1882 /* Device ID */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define dma_addr_hi32(addr) (uint32_t)((addr>>16)>>16)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define dma_addr_lo32(addr) (uint32_t)(addr & 0xffffffff)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * IOCTL CONTROL CODE
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson struct CMD_MESSAGE cmdmessage; /* 28 byte ioctl header */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint8_t messagedatabuffer[MSGDATABUFLEN]; /* 1032 */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* areca gui program does not accept more than 1031 byte */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* IOP message transfer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* error code for StorPortLogError,ScsiPortLogError */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* DeviceType */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* FunctionCode */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define FUNCTION_REQUEST_RETURN_CODE_3F 0x0806
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* ARECA IO CONTROL CODE */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_MESSAGE_REQUEST_RETURN_CODE_3F \
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ARECA_SATA_RAID | FUNCTION_REQUEST_RETURN_CODE_3F
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* ARECA IOCTL ReturnCode */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * SPEC. for Areca HBB adapter
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* ARECA HBB COMMAND for its FIRMWARE */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* window of "instruction flags" from driver to iop */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_DRV2IOP_DOORBELL 0x00020400
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* window of "instruction flags" from iop to driver */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_IOP2DRV_DOORBELL 0x00020408
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* ARECA FLAG LANGUAGE */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl xfer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl xfer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_START_BGRB 0x00060008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl xfer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl xfer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore/* Host Interrupt Mask */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore/* Host Interrupt Status */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * Set when the Utility_A Interrupt bit is set in the Outbound
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * Doorbell Register. It clears by writing a 1 to the
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * Utility_A bit in the Outbound Doorbell Clear Register or
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * through automatic clearing (if enabled).
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * Set if Outbound Doorbell register bits 30:1 have a non-zero
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * value. This bit clears only when Outbound Doorbell bits
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * 30:1 are ALL clear. Only a write to the Outbound Doorbell
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * Clear register clears bits in the Outbound Doorbell
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * Set whenever the Outbound Post List Producer/Consumer
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * Register (FIFO) is not empty. It clears when the Outbound
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * Post List FIFO is empty.
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * This bit indicates a SAS interrupt from a source external to
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore * the PCIe core. This bit is not maskable.
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore/* DoorBell */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* data tunnel buffer between user space program and its firmware */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* iop msgcode_rwbuffer for message command */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* user space data to iop 128bytes */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* iop data to user space 128bytes */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_HBB_BASE0_OFFSET 0x00000010
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_HBB_BASE1_OFFSET 0x00000018
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * structure for holding DMA address data
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define IS_SG64_ADDR 0x01000000 /* bit24 */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* 32bit Scatter-Gather list */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* bit 24 = 0, high 8 bit = flag, low 24 bit = length */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* 64bit Scatter-Gather list */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* bit 24 = 1, high 8 bit = flag, low 24 bit = length */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * FIRMWARE INFO
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * ARECA FIRMWARE SPEC
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Usage of IOP331 adapter
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (All In/Out is in IOP331's view)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 1. Message 0 --> InitThread message and retrun code
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 2. Doorbell is used for RS-232 emulation
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * InDoorBell :
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * bit0 -- data in ready (DRIVER DATA WRITE OK)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * bit1 -- data out has been read
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (DRIVER DATA READ OK)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * outDoorBell:
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * bit0 -- data out ready (IOP331 DATA WRITE OK)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * bit1 -- data in has been read
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (IOP331 DATA READ OK)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 3. Index Memory Usage
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * offset 0xf00 : for RS232 out (request buffer)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * offset 0xe00 : for RS232 in (scratch buffer)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * offset 0xa00 : for inbound message code msgcode_rwbuffer
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (driver send to IOP331)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * offset 0xa00 : for outbound message code msgcode_rwbuffer
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (IOP331 send to driver)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 4. RS-232 emulation
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Currently 128 byte buffer is used:
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 1st uint32_t : Data length (1--124)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Byte 4--127 : Max 124 bytes of data
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * All SCSI Command must be sent through postQ:
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (inbound queue port) Request frame must be 32 bytes aligned
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * # bits 31:27 => flag for post ccb
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * # bits 26:00 => real address (bit 31:27) of post arcmsr_cdb
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * bit31 : 0 : 256 bytes frame
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 1 : 512 bytes frame
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * bit30 : 0 : normal request
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 1 : BIOS request
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * bit29 : reserved
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * bit28 : reserved
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * bit27 : reserved
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * -----------------------------------------------------------------------
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (outbount queue port) Request reply
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * # bits 31:27 => flag for reply
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * # bits 26:00 => real address (bits 31:27) of reply arcmsr_cdb
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * # bit31 : must be 0 (for this type of reply)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * # bit30 : reserved for BIOS handshake
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * # bit29 : reserved
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * # bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 1 : Error, see in AdapStatus/DevStatus/SenseData
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * # bit27 : reserved
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 6. BIOS request
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * All BIOS request is the same with request from PostQ
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Request frame is sent from configuration space
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * offset: 0x78 : Request Frame (bit30 == 1)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * offset: 0x18 : writeonly to generate IRQ to IOP331
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Completion of request:
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (bit30 == 0, bit28==err flag)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 7. Definition of SGL entry (structure)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 8. Message1 Out - Diag Status Code (????)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 9. Message0 message code :
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 0x01 : Get Config ->offset 0xa00
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * : for outbound message code msgcode_rwbuffer
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (IOP331 send to driver)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Signature 0x87974060(4)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Request len 0x00000200(4)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * numbers of queue 0x00000100(4)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * SDRAM Size 0x00000100(4)-->256 MB
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * IDE Channels 0x00000008(4)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * vendor 40 bytes char
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * model 8 bytes char
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * FirmVer 16 bytes char
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Device Map 16 bytes char
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * FirmwareVersion DWORD
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * <== Added for checking of new firmware capability
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 0x02 : Set Config ->offset 0xa00
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * :for inbound message code msgcode_rwbuffer
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (driver send to IOP331)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Signature 0x87974063(4)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * UPPER32 of Request Frame (4)-->Driver Only
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 0x03 : Reset (Abort all queued Command)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 0x04 : Stop Background Activity
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 0x05 : Flush Cache
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 0x06 : Start Background Activity
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (re-start if background is halted)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 0x07 : Check If Host Command Pending
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * (Novell May Need This Function)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 0x08 : Set controller time ->offset 0xa00 (driver to IOP331)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * : for inbound message code msgcode_rwbuffer
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * byte 0 : 0xaa <-- signature
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * byte 1 : 0x55 <-- signature
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * byte 2 : year (04)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * byte 3 : month (1..12)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * byte 4 : date (1..31)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * byte 5 : hour (0..23)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * byte 6 : minute (0..59)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * byte 7 : second (0..59)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* signature of set and get firmware config */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* message code of inbound message register */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* doorbell interrupt generator */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore/* ccb areca ccb flag */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* outbound firmware ok */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore/* dma burst sizes */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define DEFAULT_BURSTSIZE BURST16|BURST8|BURST4|BURST2|BURST1
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#endif /* BURSTSIZE */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint8_t CdbLength; /* set in arcmsr_tran_init_pkt */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* bit 0: 0(256) / 1(512) bytes */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* bit 1: 0(from driver) / 1(from BIOS) */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* bit 2: 0(Data in) / 1(Data out) */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint32_t Context; /* Address of this request */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint32_t DataLength; /* currently unused */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Device Status : the same from SCSI bus if error occur
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * SCSI bus status codes.
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define SCSISTAT_INTERMEDIATE_COND_MET 0x14
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define SCSISTAT_RESERVATION_CONFLICT 0x18
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* Scatter gather address */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES];
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES];
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* ......local_buffer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * offset 0x00020400:00,01,02,03: window of "instruction flags"
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * from driver to iop
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* 04,05,06,07: doorbell mask */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* 08,09,10,11: window of "instruction flags" from iop to driver */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* 12,13,14,15: doorbell mask */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* offset 0x0000fa00: 0..1023: message code read write 1024bytes */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* offset 0x0000fe00:1024...1151: user space data to iop 128bytes */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* 1152...1279: message reserved */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* offset 0x0000ff00:1280...1407: iop data to user space 128bytes */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_unit_status; /* 0000 0003 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t slave_error_attribute; /* 0004 0007 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t slave_error_address; /* 0008 000B */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t posted_outbound_doorbell; /* 000C 000F */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t master_error_attribute; /* 0010 0013 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t master_error_address_low; /* 0014 0017 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t master_error_address_high; /* 0018 001B */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t diagnostic_rw_data; /* 0024 0027 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t diagnostic_rw_address_low; /* 0028 002B */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t diagnostic_rw_address_high; /* 002C 002F */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t outbound_queueport; /* 0044 0047 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t hcb_pci_address_low; /* 0048 004B */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t hcb_pci_address_high; /* 004C 004F */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t iop_inbound_queue_port; /* 0058 005B */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t iop_outbound_queue_port; /* 005C 005F */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t inbound_free_list_index; /* 0060 0063 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t inbound_post_list_index; /* 0064 0067 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t outbound_free_list_index; /* 0068 006B */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t outbound_post_list_index; /* 006C 006F */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t inbound_doorbell_clear; /* 0070 0073 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t i2o_message_unit_control; /* 0074 0077 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t last_used_message_source_address_low; /* 0078 007B */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t last_used_message_source_address_high; /* 007C 007F */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t pull_mode_data_byte_count[4]; /* 0080 008F */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_dest_address_index; /* 0090 0093 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t done_queue_not_empty_int_counter_timer; /* 0094 0097 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t utility_A_int_counter_timer; /* 0098 009B */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t outbound_doorbell_clear; /* 00A0 00A3 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_source_address_index; /* 00A4 00A7 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_done_queue_index; /* 00A8 00AB */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t inbound_queueport_low; /* 00C0 00C3 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t inbound_queueport_high; /* 00C4 00C7 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t outbound_queueport_low; /* 00C8 00CB */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t outbound_queueport_high; /* 00CC 00CF */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t iop_inbound_queue_port_low; /* 00D0 00D3 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t iop_inbound_queue_port_high; /* 00D4 00D7 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t iop_outbound_queue_port_low; /* 00D8 00DB */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t iop_outbound_queue_port_high; /* 00DC 00DF */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_dest_queue_port_low; /* 00E0 00E3 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_dest_queue_port_high; /* 00E4 00E7 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t last_used_message_dest_address_low; /* 00E8 00EB */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t last_used_message_dest_address_high; /* 00EC 00EF */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_done_queue_base_address_low; /* 00F0 00F3 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_done_queue_base_address_high; /* 00F4 00F7 */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_wbuffer[32]; /* 2000 207F */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t message_rbuffer[32]; /* 2100 217F */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint32_t msgcode_rwbuffer[256]; /* 2200 23FF */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Adapter Control Block
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ACB_ADAPTER_TYPE_A 0x00000001 /* hba (Intel) IOP */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb (Marvell) IOP */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc (Lsi) IOP */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* Offset for arc cdb physical to virtual calculations */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* message unit ATU inbound base address0 virtual */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* stop RAID background rebuild */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* stop RAID background rebuild */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* iop ioctl data rqbuffer overflow */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* ioctl clear wqbuffer */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* ioctl clear rqbuffer */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* ioctl iop wqbuffer data readed */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore/* need hardware reset bus */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* serial ccb pointer array */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore struct CCB *pccb_pool[ARCMSR_MAX_FREECCB_NUM];
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* working ccb pointer array */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore struct CCB *ccbworkingQ[ARCMSR_MAX_FREECCB_NUM];
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* done ccb array index */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* start ccb array index */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* data collection buffer for read from 80331 */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* first of read buffer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* last of read buffer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* data collection buffer for write to 80331 */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* first of write buffer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* last of write buffer */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson /* id0 ..... id15,lun0...lun7 */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * Command Control Block (SrbExtension)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * CCB must be not cross page boundary,and the order from offset 0
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * structure describing an ATA disk request this CCB length must be
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * 32 bytes boundary
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore (ARCMSR_CCB_TIMEOUT | ARCMSR_CCB_ABORTED | ARCMSR_CCB_RESET)
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore#define ARCMSR_CCB_CAN_BE_FREE (ARCMSR_CCB_WAIT4_FREE | ARCMSR_CCB_BACK)
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore ddi_dma_cookie_t pkt_dmacookies[ARCMSR_MAX_SG_ENTRIES];
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson/* SenseData[15] */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ErrorCode :4, /* Vendor Unique error code */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson ErrorClass :3, /* Error Class- fixed at 0x7 */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint8_t SegmentNumber; /* segment number: for COPY cmd */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson IncorrectLength :1, /* Incorrect Length Indicator */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint8_t DevType; /* Periph Qualifier & Periph Dev Type */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint8_t Vers; /* ISO, ECMA, & ANSI versions */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint8_t RDF; /* AEN, TRMIOP, & response data format */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint8_t AddLen; /* length of additional data */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson uint8_t Flags; /* RelADr, Wbus32, Wbus16, Sync etc */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint8_t VendorID[VIDLEN]; /* Vendor Identification */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint8_t ProductID[PIDLEN]; /* Product Identification */
82beb6028da8d7d7f8562908ca027bd4a1cc7d37Garrett D'Amore uint8_t ProductRev[REVLEN]; /* Product Revision */
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * These definitions are the register offsets as defined in the Intel
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * IOP manuals. See (correct as of 18 January 2008)
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * http://developer.intel.com/design/iio/index.htm?iid=ncdcnav2+stor_ioproc
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson * for more details
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020
508aff1a85ed04f187fd074799bcaefd630490f1James C. McPherson#endif /* _SYS_SCSI_ADAPTERS_ARCMSR_H */