pcie_pci.c revision ae115bc77f6fcde83175c75b4206dc2e50747966
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* PCI-E to PCI bus bridge nexus driver
*/
#include <sys/autoconf.h>
#include <sys/ddi_impldefs.h>
#include <sys/pcie_impl.h>
#ifdef DEBUG
static int pepb_debug = 0;
#else
#define PEPB_DEBUG(args)
#endif
/*
*/
void *);
struct bus_ops pepb_bus_ops = {
0,
0,
0,
0, /* (*bus_get_eventcookie)(); */
0, /* (*bus_add_eventcall)(); */
0, /* (*bus_remove_eventcall)(); */
0, /* (*bus_post_event)(); */
0, /* (*bus_intr_ctl)(); */
0, /* (*bus_config)(); */
0, /* (*bus_unconfig)(); */
pepb_fm_init, /* (*bus_fm_init)(); */
NULL, /* (*bus_fm_fini)(); */
NULL, /* (*bus_fm_access_enter)(); */
NULL, /* (*bus_fm_access_exit)(); */
NULL, /* (*bus_power)(); */
i_ddi_intr_ops /* (*bus_intr_op)(); */
};
/*
* The goal here is to leverage off of the pcihp.c source without making
* changes to it. Call into it's cb_ops directly if needed.
*/
caddr_t, int *);
struct cb_ops pepb_cb_ops = {
pepb_open, /* open */
pepb_close, /* close */
nodev, /* strategy */
nodev, /* print */
nodev, /* dump */
nodev, /* read */
nodev, /* write */
pepb_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
pepb_prop_op, /* cb_prop_op */
NULL, /* streamtab */
CB_REV, /* rev */
nodev, /* int (*cb_aread)() */
nodev /* int (*cb_awrite)() */
};
static int pepb_probe(dev_info_t *);
DEVO_REV, /* devo_rev */
0, /* refcnt */
pepb_info, /* info */
nulldev, /* identify */
pepb_probe, /* probe */
pepb_attach, /* attach */
pepb_detach, /* detach */
nulldev, /* reset */
&pepb_cb_ops, /* driver operations */
&pepb_bus_ops /* bus operations */
};
/*
* Module linkage information for the kernel.
*/
&mod_driverops, /* Type of module */
"PCIe to PCI nexus driver %I%",
&pepb_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
(void *)&modldrv,
};
/*
* soft state pointer and structure template:
*/
static void *pepb_state;
typedef struct {
/*
* cpr support:
*/
struct {
/*
* hot plug support
*/
int inband_hpc; /* inband HPC type */
/*
* interrupt support
*/
int htable_size; /* htable size */
int intr_count; /* Num of Intr */
int intr_type; /* (MSI | FIXED) */
int pepb_fmcap;
int port_type;
/* soft state flags */
/* default interrupt priority for all interrupts (hotplug or non-hotplug */
#define PEPB_INTR_PRI 1
/* flag to turn on MSI support */
static int pepb_enable_msi = 1;
/* panic on unknown flag, defaulted to on */
int pepb_panic_unknown = 1;
int pepb_panic_fatal = 1;
extern errorq_t *pci_target_queue;
/*
* forward function declarations:
*/
static void pepb_uninitchild(dev_info_t *);
/* interrupt related declarations */
static int pepb_is_nvidia_root_port(dev_info_t *);
int
_init(void)
{
int e;
return (e);
}
int
_fini(void)
{
int e;
if ((e = mod_remove(&modlinkage)) == 0) {
/*
* Destroy pci_target_queue, and set it to NULL.
*/
if (pci_target_queue)
}
return (e);
}
int
{
}
/*ARGSUSED*/
static int
{
return (DDI_PROBE_SUCCESS);
}
static int
{
int instance;
int intr_types;
char device_type[8];
switch (cmd) {
case DDI_RESUME:
/*
* Get the soft state structure for the bridge.
*/
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
case DDI_ATTACH:
break;
}
/*
* If PCIE_LINKCTL_LINK_DISABLE bit in the PCIe Config
* Space (PCIe Capability Link Control Register) is set,
* then do not bind the driver.
*/
return (DDI_FAILURE);
/*
* Allocate and get soft state structure.
*/
return (DDI_FAILURE);
/*
* initalise fma support before we start accessing config space
*/
(void *)pepb->pepb_fm_ibc);
(void *)pepb->pepb_fm_ibc);
/*
* Make sure the "device_type" property exists.
*/
else
"device_type", device_type);
/* probe for inband HPC */
/*
* Initialize interrupt handlers.
*/
goto next_step;
goto next_step;
else
"%s#%d: Unable to attach MSI handler",
}
/*
* Only register hotplug interrupts for now.
* Check if device supports PCIe hotplug or not?
* If yes, register fixed interrupts if ILINE is valid.
*/
goto next_step;
"%s#%d: Unable to attach INTx handler",
}
/*
* Initialize hotplug support on this bus. At minimum
* (for non hotplug bus) this would create ":devctl" minor
* node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
* to this bus.
*/
else {
/*
* If there is an inband PCI-E HPC then initialize it.
* The failure is not considered fatal for the system
* so log the message and ignore the failure.
*/
"controller");
}
}
return (DDI_SUCCESS);
}
static int
{
switch (cmd) {
case DDI_SUSPEND:
return (DDI_SUCCESS);
case DDI_DETACH:
break;
default:
return (DDI_FAILURE);
}
/* remove interrupt handlers */
/* uninitialize inband PCI-E HPC if present */
(void) pciehpc_uninit(devi);
/*
* Uninitialize hotplug support on this bus.
*/
(void) pcihp_uninit(devi);
/*
* And finally free the per-pci soft state.
*/
return (DDI_SUCCESS);
}
static int
{
}
static int
{
int reglen;
int rn;
int totreg;
switch (ctlop) {
case DDI_CTLOPS_REPORTDEV:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_INITCHILD:
case DDI_CTLOPS_UNINITCHILD:
return (DDI_SUCCESS);
case DDI_CTLOPS_SIDDEV:
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE:
case DDI_CTLOPS_NREGS:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
break;
case DDI_CTLOPS_PEEK:
case DDI_CTLOPS_POKE:
&pepb->pepb_peek_poke_mutex));
default:
}
*(int *)result = 0;
®len) != DDI_SUCCESS)
return (DDI_FAILURE);
if (ctlop == DDI_CTLOPS_NREGS)
else if (ctlop == DDI_CTLOPS_REGSIZE) {
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
}
static int
{
char **unit_addr;
uint_t n;
/*
* For .conf nodes, use unit-address property as name
*/
if (ndi_dev_is_persistent_node(child) == 0) {
"cannot find unit-address in %s.conf",
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
return (DDI_SUCCESS);
}
/* get child "reg" property */
return (DDI_FAILURE);
}
/* copy the device identifications */
if (func != 0)
else
return (DDI_SUCCESS);
}
static int
{
struct ddi_parent_private_data *pdptr;
char name[MAXNAMELEN];
return (DDI_FAILURE);
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
extern int pci_allow_pseudo_children;
/*
* Try to merge the properties from this prototype
* node into real h/w nodes.
*/
/*
* Merged ok - return failure to remove the node.
*/
return (DDI_FAILURE);
}
/* workaround for ddivs to run under PCI-E */
return (DDI_SUCCESS);
/*
* The child was not merged into a h/w node,
* but there's not much we can do with it other
* than return failure to cause the node to be removed.
*/
return (DDI_NOT_WELL_FORMED);
}
-1) != -1) {
} else
}
return (DDI_SUCCESS);
}
static void
{
struct ddi_parent_private_data *pdptr;
/*
* Do it way early.
* Otherwise ddi_map() call form pcie_error_fini crashes
*/
}
}
/*
* Strip the node to properly convert it back to prototype form
*/
}
/*
* pepb_save_config_regs
*
* This routine saves the state of the configuration registers of all
* the child nodes of each PBM.
*
* used by: pepb_detach() on suspends
*
* return value: none
*
* XXX: Need to save PCI-E config registers including MSI
*/
static void
{
int i;
continue;
}
}
pepb_p->config_state_index = i;
}
/*
* pepb_restore_config_regs
*
* This routine restores the state of the configuration registers of all
* the child nodes of each PBM.
*
* used by: pepb_attach() on resume
*
* return value: none
*
* XXX: Need to restore PCI-E config registers including MSI
*/
static void
{
int i;
for (i = 0; i < pepb_p->config_state_index; i++) {
continue;
}
}
}
static int
{
return (DDI_FAILURE);
/* No PCIe CAP regs, we are not PCIe device_type */
if (*port_type < 0)
return (DDI_FAILURE);
/* check for all PCIe device_types */
if ((*port_type == PCIE_PCIECAP_DEV_TYPE_UP) ||
(*port_type == PCIE_PCIECAP_DEV_TYPE_DOWN) ||
(*port_type == PCIE_PCIECAP_DEV_TYPE_ROOT) ||
return (DDI_SUCCESS);
return (DDI_FAILURE);
}
/*
* This function initializes internally generated interrupts only.
* It does not affect any interrupts generated by downstream devices
* or the forwarding of them.
*
* Enable Device Specific Interrupts or Hotplug features here.
* Enabling features may change how many interrupts are requested
* by the device. If features are not enabled first, the
* device might not ask for any interrupts.
*/
static int
{
int ret;
int intr_cap = 0;
int inum = 0;
int isr_tab_size = 0;
/*
* Get number of requested interrupts. If none requested or DDI_FAILURE
* just return DDI_SUCCESS.
*
* in a FAILURE, if the device is not configured in a way that
* interrupts are needed. (eg. hotplugging)
*/
return (DDI_FAILURE);
}
/* Allocate an array of interrupt handlers */
goto fail;
}
/* Save the actual number of interrupts allocated */
#ifdef DEBUG
#endif /* DEBUG */
/* Get interrupt priority */
if (ret != DDI_SUCCESS) {
goto fail;
}
/* initialize the interrupt mutex */
intr_type == DDI_INTR_TYPE_MSI &&
isr_tab[0] = pepb_pwr_msi_intr;
} else
isr_tab[0] = pepb_intx_intr;
if (ret != DDI_SUCCESS) {
ret));
break;
}
}
/* If unsucessful, remove the added handlers */
if (ret != DDI_SUCCESS) {
for (x = 0; x < count; x++) {
}
goto fail;
}
if (intr_cap & DDI_INTR_FLAG_BLOCK) {
pepb_p->intr_count);
} else {
}
}
/* Save the interrupt type */
return (DDI_SUCCESS);
fail:
return (DDI_FAILURE);
}
static void
{
int x;
if ((flags & PEPB_SOFT_STATE_INIT_ENABLE) &&
(flags & PEPB_SOFT_STATE_INIT_BLOCK)) {
flags &= ~(PEPB_SOFT_STATE_INIT_ENABLE |
}
if (flags & PEPB_SOFT_STATE_INIT_MUTEX) {
/* destroy the mutex */
}
for (x = 0; x < count; x++) {
if (flags & PEPB_SOFT_STATE_INIT_ENABLE)
if (flags & PEPB_SOFT_STATE_INIT_ALLOC)
}
flags &= ~(PEPB_SOFT_STATE_INIT_ENABLE |
if (flags & PEPB_SOFT_STATE_INIT_HTABLE)
}
/*
* pepb_intx_intr()
*
* This is the common interrupt handler for both hotplug and non-hotplug
* interrupts. For handling hot plug interrupts it calls pciehpc_intr().
*
* NOTE: Currently only hot plug interrupts are enabled so it simply
* calls pciehpc_intr(). This is for INTx interrupts *ONLY*.
*/
/*ARGSUSED*/
static uint_t
{
int ret = DDI_INTR_UNCLAIMED;
return (DDI_INTR_UNCLAIMED);
/* if HPC is initialized then call the interrupt handler */
return (ret);
}
/*
* pepb_is_nvidia_root_port()
*
* This helper function checks if the device is a Nvidia RC or not
*/
static int
{
int ret = DDI_FAILURE;
return (ret);
ret = DDI_SUCCESS;
return (ret);
}
/*
* pepb_pwr_msi_intr()
*
* This is the MSI interrupt handler for PM related events.
*/
/*ARGSUSED*/
static uint_t
{
return (DDI_INTR_UNCLAIMED);
return (DDI_INTR_CLAIMED);
}
static int
{
/* Need to look at the port type information here */
}
/*ARGSUSED*/
int
{
return (pepb->pepb_fmcap);
}
/*ARGSUSED*/
int
{
return (derr->fme_status);
}
/*ARGSUSED*/
static uint_t
{
return (DDI_INTR_UNCLAIMED);
/* if HPC is initialized then call the interrupt handler */
fm_panic("%s-%d: PCI(-X) Express Fatal Error",
return (DDI_INTR_CLAIMED);
}
static int
{
int rval = 0;
return (rval);
if (pcie_cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
rval = 1;
}
return (rval);
}
static int
{
}
static int
{
}
static int
int *rvalp)
{
rvalp));
}
static int
{
}
static int
{
}