pcie_pci.c revision 49fbdd30212f016ddd49c4b5c997b0b827ff0962
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* PCI-E to PCI bus bridge nexus driver
*/
#include <sys/autoconf.h>
#include <sys/ddi_impldefs.h>
#include <sys/pcie_impl.h>
#ifdef DEBUG
static int pepb_debug = 0;
#else
#define PEPB_DEBUG(args)
#endif
/*
*/
void *);
struct bus_ops pepb_bus_ops = {
0,
0,
0,
0, /* (*bus_get_eventcookie)(); */
0, /* (*bus_add_eventcall)(); */
0, /* (*bus_remove_eventcall)(); */
0, /* (*bus_post_event)(); */
0, /* (*bus_intr_ctl)(); */
0, /* (*bus_config)(); */
0, /* (*bus_unconfig)(); */
pepb_fm_init, /* (*bus_fm_init)(); */
NULL, /* (*bus_fm_fini)(); */
NULL, /* (*bus_fm_access_enter)(); */
NULL, /* (*bus_fm_access_exit)(); */
NULL, /* (*bus_power)(); */
i_ddi_intr_ops /* (*bus_intr_op)(); */
};
/*
* The goal here is to leverage off of the pcihp.c source without making
* changes to it. Call into it's cb_ops directly if needed.
*/
caddr_t, int *);
struct cb_ops pepb_cb_ops = {
pepb_open, /* open */
pepb_close, /* close */
nodev, /* strategy */
nodev, /* print */
nodev, /* dump */
nodev, /* read */
nodev, /* write */
pepb_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
pepb_prop_op, /* cb_prop_op */
NULL, /* streamtab */
CB_REV, /* rev */
nodev, /* int (*cb_aread)() */
nodev /* int (*cb_awrite)() */
};
static int pepb_probe(dev_info_t *);
DEVO_REV, /* devo_rev */
0, /* refcnt */
pepb_info, /* info */
nulldev, /* identify */
pepb_probe, /* probe */
pepb_attach, /* attach */
pepb_detach, /* detach */
nulldev, /* reset */
&pepb_cb_ops, /* driver operations */
&pepb_bus_ops, /* bus operations */
NULL, /* power */
ddi_quiesce_not_needed, /* quiesce */
};
/*
* Module linkage information for the kernel.
*/
&mod_driverops, /* Type of module */
"PCIe to PCI nexus driver",
&pepb_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
(void *)&modldrv,
};
/*
* soft state pointer and structure template:
*/
static void *pepb_state;
typedef struct {
/*
* cpr support:
*/
struct {
/*
* hot plug support
*/
int inband_hpc; /* inband HPC type */
/*
* interrupt support
*/
int htable_size; /* htable size */
int intr_count; /* Num of Intr */
int intr_type; /* (MSI | FIXED) */
/* soft state flags */
/* default interrupt priority for all interrupts (hotplug or non-hotplug */
#define PEPB_INTR_PRI 1
#define PEPB_INTR_SRC_HP 0x1
#define PEPB_INTR_SRC_PME 0x2
#define PEPB_INTR_SRC_AER 0x4
/* flag to turn on MSI support */
int pepb_enable_msi = 1;
/* panic on PF_PANIC flag */
int pepb_die = PF_ERR_FATAL_FLAGS;
extern errorq_t *pci_target_queue;
/*
* forward function declarations:
*/
static void pepb_uninitchild(dev_info_t *);
/* interrupt related declarations */
/* Intel Workarounds */
int pepb_intel_workaround_disable = 0;
int
_init(void)
{
int e;
return (e);
}
int
_fini(void)
{
int e;
if ((e = mod_remove(&modlinkage)) == 0) {
/*
* Destroy pci_target_queue, and set it to NULL.
*/
if (pci_target_queue)
}
return (e);
}
int
{
}
/*ARGSUSED*/
static int
{
return (DDI_PROBE_SUCCESS);
}
static int
{
char device_type[8];
switch (cmd) {
case DDI_RESUME:
/*
* Get the soft state structure for the bridge.
*/
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
case DDI_ATTACH:
break;
}
/*
* If PCIE_LINKCTL_LINK_DISABLE bit in the PCIe Config
* Space (PCIe Capability Link Control Register) is set,
* then do not bind the driver.
*/
return (DDI_FAILURE);
/*
* Allocate and get soft state structure.
*/
return (DDI_FAILURE);
/*
* initialize fma support before we start accessing config space
*/
(void *)pepb->pepb_fm_ibc);
(void *)pepb->pepb_fm_ibc);
/*
* Make sure the "device_type" property exists.
*/
if (pepb_is_pcie_device_type(devi))
else
"device_type", device_type);
/* probe for inband HPC */
/*
* Initialize interrupt handlers.
*/
goto next_step;
goto next_step;
else
"%s#%d: Unable to attach MSI handler",
}
/*
* If we are here that means MSIs were not enabled. For errors fall back
* to the SERR+Machinecheck approach on Intel chipsets.
*/
if (PCIE_IS_RP(bus_p))
/*
* Only register hotplug interrupts for now.
* Check if device supports PCIe hotplug or not?
* If yes, register fixed interrupts if ILINE is valid.
* Fix error handling for INTx.
*/
goto next_step;
"%s#%d: Unable to attach INTx handler",
}
/*
* Initialize hotplug support on this bus. At minimum
* (for non hotplug bus) this would create ":devctl" minor
* node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
* to this bus.
*/
else {
/*
* If there is an inband PCI-E HPC then initialize it.
* The failure is not considered fatal for the system
* so log the message and ignore the failure.
*/
"controller");
}
}
/* Must apply workaround only after all initialization is done */
return (DDI_SUCCESS);
}
static int
{
switch (cmd) {
case DDI_SUSPEND:
return (DDI_SUCCESS);
case DDI_DETACH:
break;
default:
return (DDI_FAILURE);
}
/* remove interrupt handlers */
/* uninitialize inband PCI-E HPC if present */
(void) pciehpc_uninit(devi);
/*
* Uninitialize hotplug support on this bus.
*/
(void) pcihp_uninit(devi);
/*
* And finally free the per-pci soft state.
*/
return (DDI_SUCCESS);
}
static int
{
}
static int
{
int reglen;
int rn;
int totreg;
struct detachspec *ds;
struct attachspec *as;
switch (ctlop) {
case DDI_CTLOPS_REPORTDEV:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_INITCHILD:
case DDI_CTLOPS_UNINITCHILD:
return (DDI_SUCCESS);
case DDI_CTLOPS_SIDDEV:
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE:
case DDI_CTLOPS_NREGS:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
break;
case DDI_CTLOPS_PEEK:
case DDI_CTLOPS_POKE:
case DDI_CTLOPS_ATTACH:
return (DDI_SUCCESS);
(void) pcie_postattach_child(rdip);
/*
* For leaf devices supporting RBER and AER, we need
* to apply this workaround on them after attach to be
* notified of UEs that would otherwise be ignored
* as CEs on Intel chipsets currently
*/
}
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_DETACH:
return (DDI_SUCCESS);
return (DDI_FAILURE);
return (DDI_SUCCESS);
default:
}
*(int *)result = 0;
®len) != DDI_SUCCESS)
return (DDI_FAILURE);
if (ctlop == DDI_CTLOPS_NREGS)
else if (ctlop == DDI_CTLOPS_REGSIZE) {
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
}
static int
{
char **unit_addr;
uint_t n;
/*
* For .conf nodes, use unit-address property as name
*/
if (ndi_dev_is_persistent_node(child) == 0) {
"cannot find unit-address in %s.conf",
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
return (DDI_SUCCESS);
}
/* get child "reg" property */
return (DDI_FAILURE);
}
/* copy the device identifications */
if (func != 0)
else
return (DDI_SUCCESS);
}
static int
{
struct ddi_parent_private_data *pdptr;
char name[MAXNAMELEN];
return (DDI_FAILURE);
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
extern int pci_allow_pseudo_children;
/*
* Try to merge the properties from this prototype
* node into real h/w nodes.
*/
/*
* Merged ok - return failure to remove the node.
*/
return (DDI_FAILURE);
}
/* workaround for ddivs to run under PCI-E */
return (DDI_SUCCESS);
/*
* The child was not merged into a h/w node,
* but there's not much we can do with it other
* than return failure to cause the node to be removed.
*/
return (DDI_NOT_WELL_FORMED);
}
-1) != -1) {
} else
return (DDI_FAILURE);
return (DDI_SUCCESS);
}
static void
{
struct ddi_parent_private_data *pdptr;
}
/*
* Strip the node to properly convert it back to prototype form
*/
}
/*
* pepb_save_config_regs
*
* This routine saves the state of the configuration registers of all
* the child nodes of each PBM.
*
* used by: pepb_detach() on suspends
*
* return value: none
*
* XXX: Need to save PCI-E config registers including MSI
*/
static void
{
int i;
continue;
}
}
pepb_p->config_state_index = i;
}
/*
* pepb_restore_config_regs
*
* This routine restores the state of the configuration registers of all
* the child nodes of each PBM.
*
* used by: pepb_attach() on resume
*
* return value: none
*
* XXX: Need to restore PCI-E config registers including MSI
*/
static void
{
int i;
for (i = 0; i < pepb_p->config_state_index; i++) {
continue;
}
}
}
static boolean_t
{
return (B_TRUE);
return (B_FALSE);
}
/*
* This function initializes internally generated interrupts only.
* It does not affect any interrupts generated by downstream devices
* or the forwarding of them.
*
* Enable Device Specific Interrupts or Hotplug features here.
* Enabling features may change how many interrupts are requested
* by the device. If features are not enabled first, the
* device might not ask for any interrupts.
*/
static int
{
int intr_cap = 0;
int inum = 0;
request = 0;
request++;
}
/*
* Hotplug and PME share the same MSI vector. If hotplug is not
* supported check if MSI is needed for PME.
*/
(vendorid == NVIDIA_VENDOR_ID)) {
if (!is_hp)
request++;
}
/* Setup MSI if this device is a Rootport and has AER. */
if (intr_type == DDI_INTR_TYPE_MSI) {
request++;
}
if (request == 0)
return (DDI_FAILURE);
/*
* Get number of supported interrupts.
*
* in a FAILURE, if the device is not configured in a way that
* interrupts are needed. (eg. hotplugging)
*/
return (DDI_FAILURE);
}
/* Allocate an array of interrupt handlers */
goto FAIL;
}
/* Save the actual number of interrupts allocated */
}
/*
* NVidia (MCP55 and other) chipsets have a errata that if the number
* of requested MSI intrs is not allocated we have to fall back to INTx.
*/
if (intr_type == DDI_INTR_TYPE_MSI) {
goto FAIL;
}
}
/* Get interrupt priority */
if (ret != DDI_SUCCESS) {
goto FAIL;
}
/* initialize the interrupt mutex */
if (ret != DDI_SUCCESS) {
ret));
break;
}
}
/* If unsucessful, remove the added handlers */
if (ret != DDI_SUCCESS) {
for (x = 0; x < count; x++) {
}
goto FAIL;
}
/*
* Get this intr lock because we are not quite ready to handle
* interrupts immediately after enabling it. The MSI multi register
* gets programmed in ddi_intr_enable after which we need to get the
*/
if (intr_cap & DDI_INTR_FLAG_BLOCK) {
pepb_p->intr_count);
} else {
}
}
/* Save the interrupt type */
if (intr_type == DDI_INTR_TYPE_MSI) {
if (hp_msi_off >= count) {
goto FAIL;
}
if (is_hp)
if (is_pme)
} else {
/* INTx handles only Hotplug interrupts */
if (is_hp)
}
/*
* Get the MSI offset for errors from the AER Root Error status
* register.
*/
if (PCIE_HAS_AER(bus_p)) {
if (aer_msi_off >= count) {
" AER cap > max allocated %d\n",
aer_msi_off, count));
goto FAIL;
}
} else {
/*
* This RP does not have AER. Fallback to the
* SERR+Machinecheck approach.
*/
}
}
return (DDI_SUCCESS);
FAIL:
return (DDI_FAILURE);
}
static void
{
int x;
if ((flags & PEPB_SOFT_STATE_INIT_ENABLE) &&
(flags & PEPB_SOFT_STATE_INIT_BLOCK)) {
flags &= ~(PEPB_SOFT_STATE_INIT_ENABLE |
}
if (flags & PEPB_SOFT_STATE_INIT_MUTEX) {
/* destroy the mutex */
}
for (x = 0; x < count; x++) {
if (flags & PEPB_SOFT_STATE_INIT_ENABLE)
if (flags & PEPB_SOFT_STATE_INIT_ALLOC)
}
flags &= ~(PEPB_SOFT_STATE_INIT_ENABLE |
if (flags & PEPB_SOFT_STATE_INIT_HTABLE)
}
/*
* Checks if this device needs MSIs enabled or not.
*/
static int
{
return (DDI_FAILURE);
/*
* Intel ESB2 switches have a errata which prevents using MSIs
* for hotplug.
*/
if ((vendor_id == INTEL_VENDOR_ID) &&
return (DDI_FAILURE);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
}
static int
{
PCIE_LINKCTL_LINK_DISABLE) ? 1 : 0);
}
static int
{
}
static int
{
}
static int
int *rvalp)
{
rvalp);
/*
* like in attach, since hotplugging can change error registers,
* we need to ensure that the proper bits are set on this port
* after a configure operation
*/
}
return (rv);
}
static int
{
}
static int
{
}
void
}
typedef struct x86_error_reg {
typedef struct x86_error_tbl {
int error_regs_len;
/*
* Chipset and device specific settings that are required for error handling
* (reporting, fowarding, and response at the RC) beyond the standard
* registers in the PCIE and AER caps.
*
* The Northbridge Root Port settings also apply to the ESI port. The ESI
* port is a special leaf device but functions like a root port connected
* to the Southbridge and receives all the onboard Southbridge errors
* including those from Southbridge Root Ports. However, this does not
* include the Southbridge Switch Ports which act like normal switch ports
* and is connected to the Northbridge through a separate link.
*
* PCIE errors from the ESB2 Southbridge RPs are simply fowarded to the ESI
* port on the Northbridge.
*
* Currently without FMA support, we want UEs (Fatal and Non-Fatal) to panic
* the system, except for URs. We do this by having the Root Ports respond
* with a System Error and having that trigger a Machine Check (MCE).
*/
/*
* 7300 Northbridge Root Ports
*/
static x86_error_reg_t intel_7300_rp_regs[] = {
/* Command Register - Enable SERR */
/* AER UE Mask - Mask UR */
/* PEXCTRL[21] check for certain malformed TLP types and MSI enable */
{0x48, 32, 0xFFFFFFFF, 0xC0200000, 0x200000},
/* PEXCTRL3[7]. MSI RAS error enable */
{0x4D, 32, 0xFFFFFFFF, 0x1, 0x0},
/* PEX_ERR_DOCMD[7:0] */
{0x144, 8, 0x0, 0x0, 0xF0},
/* EMASK_UNCOR_PEX[21:0] UE mask */
/* EMASK_RP_PEX[2:0] FE, UE, CE message detect mask */
{0x150, 8, 0x0, 0x0, 0x1},
};
#define INTEL_7300_RP_REGS_LEN \
(sizeof (intel_7300_rp_regs) / sizeof (x86_error_reg_t))
/*
* 5000 Northbridge Root Ports
*/
static x86_error_reg_t intel_5000_rp_regs[] = {
/* Command Register - Enable SERR */
/* AER UE Mask - Mask UR */
/* PEXCTRL[21] check for certain malformed TLP type */
{0x48, 32, 0xFFFFFFFF, 0xC0200000, 0x200000},
/* PEXCTRL3[7]. MSI RAS error enable. */
{0x4D, 32, 0xFFFFFFFF, 0x1, 0x0},
/* PEX_ERR_DOCMD[7:0] */
{0x144, 8, 0x0, 0x0, 0xF0},
/* EMASK_UNCOR_PEX[21:0] UE mask */
/* EMASK_RP_PEX[2:0] FE, UE, CE message detect mask */
{0x150, 8, 0x0, 0x0, 0x1},
};
#define INTEL_5000_RP_REGS_LEN \
(sizeof (intel_5000_rp_regs) / sizeof (x86_error_reg_t))
/*
* 5400 Northbridge Root Ports.
* MSIs are not working currently, so the MSI settings are the same as the
* machinecheck settings
*/
static x86_error_reg_t intel_5400_rp_regs[] = {
/* Command Register - Enable SERR */
/* AER UE Mask - Mask UR */
/* PEXCTRL[21] check for certain malformed TLP types */
{0x48, 32, 0xFFFFFFFF, 0x200000, 0x200000},
/* PEX_ERR_DOCMD[11:0] */
{0x144, 16, 0x0, 0xFF0, 0xFF0},
/* PEX_ERR_PIN_MASK[4:0] do not mask ERR[2:0] pins used by DOCMD */
{0x146, 16, 0x0, 0x10, 0x10},
/* EMASK_UNCOR_PEX[21:0] UE mask */
/* EMASK_RP_PEX[2:0] FE, UE, CE message detect mask */
{0x150, 8, 0x0, 0x1, 0x1},
};
#define INTEL_5400_RP_REGS_LEN \
(sizeof (intel_5400_rp_regs) / sizeof (x86_error_reg_t))
/*
* ESB2 Southbridge Root Ports
*/
static x86_error_reg_t intel_esb2_rp_regs[] = {
/* Command Register - Enable SERR */
/* UEM[20:0] UE mask (write-once) */
};
#define INTEL_ESB2_RP_REGS_LEN \
(sizeof (intel_esb2_rp_regs) / sizeof (x86_error_reg_t))
/*
* ESB2 Southbridge Switch Ports
*/
static x86_error_reg_t intel_esb2_sw_regs[] = {
/* Command Register - Enable SERR */
/* AER UE Mask - Mask UR */
};
#define INTEL_ESB2_SW_REGS_LEN \
(sizeof (intel_esb2_sw_regs) / sizeof (x86_error_reg_t))
/* Intel 7300: 3600 = ESI, 3604-360A = NB root ports */
{0x8086, 0x3600, 0x3600, 0x0, 0xFF,
{0x8086, 0x3604, 0x360A, 0x0, 0xFF,
/* Intel 5000: 25C0, 25D0, 25D4, 25D8 = ESI */
{0x8086, 0x25C0, 0x25C0, 0x0, 0xFF,
{0x8086, 0x25D0, 0x25D0, 0x0, 0xFF,
{0x8086, 0x25D4, 0x25D4, 0x0, 0xFF,
{0x8086, 0x25D8, 0x25D8, 0x0, 0xFF,
/* Intel 5000: 25E2-25E7 and 25F7-25FA = NB root ports */
{0x8086, 0x25E2, 0x25E7, 0x0, 0xFF,
{0x8086, 0x25F7, 0x25FA, 0x0, 0xFF,
/* Intel 5400: 4000-4001, 4003 = ESI and 4021-4029 = NB root ports */
{0x8086, 0x4000, 0x4001, 0x0, 0xFF,
{0x8086, 0x4003, 0x4003, 0x0, 0xFF,
{0x8086, 0x4021, 0x4029, 0x0, 0xFF,
/* Intel 631xESB/632xESB aka ESB2: 2690-2697 = SB root ports */
{0x8086, 0x2690, 0x2697, 0x0, 0xFF,
/* Intel Switches on esb2: 3500-3503, 3510-351B */
{0x8086, 0x3500, 0x3503, 0x0, 0xFF,
{0x8086, 0x3510, 0x351B, 0x0, 0xFF,
/* XXX Intel PCIe-PCIx on esb2: 350C */
};
static int x86_error_init_tbl_len =
sizeof (x86_error_init_tbl) / sizeof (x86_error_tbl_t);
static int
{
int reglen;
int rv;
if (rv != DDI_SUCCESS)
return (rv);
if (reglen < (sizeof (pci_regspec_t) / sizeof (int))) {
return (DDI_FAILURE);
}
/* Get phys_hi from first element. All have same bdf. */
return (DDI_SUCCESS);
}
/*
* The main goal of this workaround is to set chipset specific settings if
* MSIs happen to be enabled on this device. Otherwise make the system
*/
static void
{
int i, j;
return;
return;
}
for (i = 0; i < x86_error_init_tbl_len; i++, tbl++) {
continue;
case 32:
break;
case 16:
break;
case 8:
break;
}
" mask:0x%x value:0x%x + orig:0x%x -> 0x%x", bdf,
}
}
}
/*
* For devices that support Role Base Errors, make several UE have a FATAL
* severity. That way a Fatal Message will be sent instead of a Correctable
* Message. Without full FMA support, CEs will be ignored.
*/
static void
{
return;
/*
* Check Root Port's machinecheck setting to determine if this
* workaround is needed or not.
*/
if (!pcie_get_rber_fatal(dip))
return;
return;
if (!rber)
return;
}
/*
* Workaround for certain switches regardless of platform
*/
static void
{
return;
return;
/*
* Intel and PLX switches require SERR in CMD reg to foward error
* messages, though this is not PCIE spec-compliant behavior.
* To prevent the switches themselves from reporting errors on URs
* when the CMD reg has SERR enabled (which is expected according to
* the PCIE spec) we rely on masking URs in the AER cap.
*/
}
}
/*
* Common interrupt handler for hotplug, PME and errors.
*/
static uint_t
{
int sts = 0;
int ret = DDI_INTR_UNCLAIMED;
int isrc;
goto FAIL;
if (isrc == PEPB_INTR_SRC_UNKNOWN)
goto FAIL;
if (isrc & PEPB_INTR_SRC_HP)
if (isrc & PEPB_INTR_SRC_PME) {
}
/* AER Error */
if (isrc & PEPB_INTR_SRC_AER) {
/*
* Status Reg before claiming it. For now it's ok since
* we know we get 2 MSIs.
*/
fm_panic("%s-%d: PCI(-X) Express Fatal Error",
}
FAIL:
return (ret);
}